Test mismatch in switched-current circuits using wavelet analysis

TSINGHUA SCIENCE AND TECHNOLOGY ISSN 1007-0214 41/49 pp229-234 Volume 12, Number S1, July 2007

Test Mismatch in Switched-Current Circuits Using Wavelet Analysis*

GUO Jierong (郭杰荣)†,**, HE Yigang (何怡刚), LIU Meirong (刘美容), TANG Shengxue (唐圣学), LI Hongmin (李宏民)

College of Electrical and Information Engineering, Hunan University, Changsha 410082, China † Institute of Information Technology，Hunan University of Arts and Science , Changde 415000, China

Abstract: Errors of mismatch and currents calibration caused by channel geometrical variety in switched-

current are investigated in this paper. The relation and computing of mismatch and sensitivity are discussed

also, and then a measure method of switched current mismatch using wavelet decomposition is proposed. A

selected group of same transconductance is choosing as a cohort firstly, and the sensitivities of cohort in re-

lation to the variation of transconductance are computed. Compared with the nominal deviation and toler-

ance borderline, the optimization and testing can be performed. As an example, a sixth order chebyshev

low-pass filter is simulated and tested. The results have justified the reliability and feasibility of the method.

Key words: switched-current; mismatch; sensitivity; cohort parameter; wavelet; decomposition

Introduction

For instance, many of switched-current (SI) circuits have been reported as the switched-current technology needs only a standard digital VLSI which do not need linear capacitors. However, concerning the testing as-pect, the existing analog circuit testing methods are not suitable for switching current circuit. There are some literature discussed testing on the switch current in-cluding testing principles, processes as well as BIST exists. These documents approaches can basically be divided into two categories: (1) based on DC signal testing technology[1-3], these methods can test the

changes of static characteristics in switching currents circuit, which caused by MOS malfunctions such as leakage current changes, export conductance, and voltage transmission characteristics and bias, but cannot test frequency dynamics and distortions characteristics; (2) based on testing phase clock[4-6], through changing the clock sequence, divide-by-two circuit is restructured into cascade connected current mirror circuit and then contrast the import and export current signal. The pro-posed techniques suffer from being applicable only to some specific structures. There are few papers dedi-cated to divide-by-two circuit and all of the methods only use DC and low-frequency parameters for implicit functional testing. The tolerate range and failure or er-ror in parameters have not been discussed.

A basal switched current cell commonly weights the input stage through scales the weighting (ratio of W/L) of output stage. This ratio of W/L is corresponding to ratio of capacitors in switched-capacitor circuits di-rectly[7]. In this paper, the deviation of transconduc-tance and current scales is investigated which is caused by channel geometrical change on technology factors and would create mismatch and deviation of response. In addition a parameter cohort scheme using normal-

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Received: 2007-02-01 Supported by the National Natural Science Foundation of China (No. 50677014), Specialized Research Fund for the Doctoral Pro-gram of Higher Education of MOE (No. 20060532002), the Pro-gram for New Century Excellent Talents in University (No. NCET-04-0767), the Science and Technology foundation of Hu-nan Province (Nos. obJJ2024 and 05GK 2005), and the key Tech-nologies Research and Development Program of the Eleventh Five Year Plan of China. To whom correspondence should be addressed. E-mail: [email protected]

Tsinghua Science and Technology, July 2007, 12(S1): 229-234 230

ized transconductance value corresponding to ratio of W/L is described. The sensitivity on transconductance method is applied to analyze and test mismatch error of switched current circuits, the optimization of test configuration and tolerance range are defined conse-quently.

1 Symmetry and Mismatch of Switched Current

1.1 Scale symmetry of switched current

Switched current circuits use MOSFET to compose switch, transconductance, and current source. The in-put capacitor Cgs store charges and transfers them to current through MOS transistor. This technique relies on precise current mirror to realize high-speed sam-pling data conversion. The algorithmic structure of cur-rent transfer circuits could be realized using simple form. The basic current mirror is shown in Fig. 1. Due to pn junction of input transistor, the input resistance is very small. The bidirectional current obtained from in-put caused the bias of T1 changed in company with current signal and transfer backwards. The channel ra-tio of W/L of output transistor T2 is α times to input; therefore, oi iα′ = − . The scaling of current can be real-ized using an appropriate choice of W/L ratio of output transistor T2. Based on this current mirror, calculate the W/L ratio and use cascade connection mode, various practical circuits such as delay, integrators, differenti-ators, and biquadratic filter. On account of the con-formability of switched current technique, variant transconductance and bias current source are created by regulating the W/L ratio of transistor, the change of W/L ratio would produce sizeable infection on per-formance of switched current circuits, which also is the primary reason for mismatch.

Fig. 1 SI basic current mirror and clock wave

1.2 Mismatch of transconductance

In an integrated circuit process, designer customarily consider about two variations, global variation ac-counts for the total variation in the value of a compo-nent over a wafer or a batch. Local variation or mis-match reflects the variation in a component value with reference to an adjacent component on the same chip[8-11]. The uppermost characteristic of mismatch in switched current circuits is the mismatch of MOS, which is more complex than mismatch of capacitors[11]. The primary parameter is transconductance, which is defined as the change of drain current relative to grid voltage, transconductance in saturation is expressed as

( )GS GS Tms Dg I V V Vβ= ∂ ∂ = − (1)

where oxWCL

β µ= ， µ is channel mobility, oxC is

the unit gate capacitance. The expression of mismatch response is

( )WL

A

WL

A

LW

A LW2

2

2

2

2

2

2 222 β

ββσ

++= (2)

where 22WA , 2

2LA , and 22βA are constant. According

to Eq. (2), ( ) WL1∝βσ . Threshold voltage mis-match has similar configuration:

( ) VTOT

AVWL

σ ∆ = (3)

VTOA is constant and the W and L should be calcu-lated using effective channel length and width, if the extracted value expressed as drawnW and drawnL , we have threshold voltage mismatch:

( )( )( )

VTO

drawn drawn

T

W L

AV

W D L Dσ ∆ =

− − (4)

where DL and DW are the total reduction parameters of length and width, respectively.

In switched current circuits, the ratio of mirror cur-rent is the linchpin of transmission function because the function modules of switched current circuits are composed of basic current mirror. However, these ra-dios are not integral customarily which certainly de-press the precision of current ratio and the function of circuits. As an example, a current mirror with current radio is r, and the width/length ratio of input and out-put transistor are W1/L1 and W2/L2, the deviation of cur-rent radio is

GUO Jierong (郭杰荣) et al：Test Mismatch in Switched-Current Circuits … 231

( )2

21 1 2 2

1 12

r KW L W Lr

σσ ⎡ ⎤≈ + +⎢ ⎥

⎣ ⎦sε (5)

where σK is constant, sε is the width and length system error caused by diffuse in technologic process. Use Wδ and Lδ denote the system error of width and length, respectively, sε is

2 1 1 2

1 1 1 1W LW W L L

= δ − + δ −sε (6)

On account of the identity in switched current tran-sistor technologic process, variant transconductance value and bias current source are obtained from alter the channel width and length. Therefore, the ratio change of channel width and length caused by variant factors not only create the deviation of transconduc-tance value and also cause current scaling errors, which would result in mismatch and response distor-tion.

1.3 Sensitivity analysis of switching currents circuit

Sensitivity is a kind of measurement about the circuit performance change with circuit components value. It is effect on the circuit transmission performance pa-rameters Ei caused by change of circuit components xi. According to the general cycle switching linear circuit analysis methods, based on small signal conditions and combined node analysis methods, the node voltage cir-cuit accompanying matrix could be solved and then we could analyze the relevant characteristics of the circuits. For a switching current circuit with switching cycle is T, each switching cycle divided into N-phase. There are two different roles of each phase components when resistance value in the same circumstances: one is con-ductance and the other one is the import and export of transconductance in a different phase. Therefore, the derivative component of node voltage value on the de-vice parameters is sum of all these emergence value. The sensitivity of node voltage ( )zEi on parameters

( )zx is

,

1 1 1

i

f f fi mkE

xm k li l

ExSE x= = =

∂=

∂∑∑∑ (7)

where m＝1, 2,…, f is output phase, k＝1, 2,…, f is in-put phase, ( )zxl is the parameters ( )zx in phase 1. Sensitivity of node voltage ( ), i mkE z on transconduc-tance ( )zGmab of the input branch and output branch

b in different phase

, ,1 1 1

i

mab

f f fE mabG a lk b lm

m k li

GS V V

E = = =

= ∑∑∑ (8)

In a given random error conditions of transconduc-tance, the absolute or statistical error can be calculated, error tolerate achieved through plus or minus deviation from the standard curve. Statistical error calculation formula can be expressed as follows:

( ) ( )( )2jj 0.05 8.686 Re a

mi

Ea G

iE S ωω∆ = × ∑ (9)

1.4 Cohort parameter of switched current

Switching current circuit is a fully compatible digital CMOS technology. It constitutes only MOS transistors, through changes in the channel width of MOS to ob-tain switches, transconductance, and current sources. To obtain the requested response, the size of transmis-sion at all levels must strictly comparable with the value through the current scaling calculation. We can choose the normalized transconductance value of im-port sampling-circuit transistor to maintain 1, the other transistor according to the current scaling. Using three switching currents biquads can constitute a cascading 6-th order chebyshev low-pass filter. All of transistors could be grouping in term of the normalized transcon-ductance value. All of transistors could be grouping in term of the normalized transconductance value such as 1, 3α , 4 ,α and 5α . There are 11 kinds of normal-ized transconductance value including 1, 0.4255, 1.9845, 0.3455, 0.9845, 0.5827, 1.9134, 0.085, 0.8577, 2.1021, and 0.2787. Import-sampling transistor can be simplified for the ideal transconductance device, set its value to 1. To calculate absolute or statistical error use the method of groups will be greatly enhance the effi-ciency of matrix analysis.

2 Wavelet Decomposition

On account of wavelet transform provides high time resolution, and low-frequency resolution for high fre-quencies (low scales). And low time resolution, and high-frequency resolution for low frequencies (high scales), the fault signals of circuits could be hierarchi-cally decomposed using wavelet[12]. Those components of signal in vary frequency can be chosen as fault characteristic and then introduced into ANN. This pre-processing of the network input data can drastically


simplify the network architecture, improve its per-formance, and reduce the number of input vectors needed for the network training. Wavelet transform of a continuous-time signal is defined as

( ) ( )13

, dx a bt bW a x t t

aψ− −⎛ ⎞= ⎜ ⎟

⎝ ⎠∫ (10)

where function ( )tψ is the so-called wavelet or mother wavelet, defined as

( )12

,a bt bt a

aψ ψ− −⎛ ⎞= ⎜ ⎟

⎝ ⎠ (11)

Coefficients a and b define degree of scaling and time shift of the mother wavelet, respectively. These coefficients characterized x(t) and introduced into ANN. Most of wavelet transform have to be calculated approximately in numerical (discrete wavelet) by com-puter, which assumed that a=2j and b= k2j= ka, and (j, k) ∈Z2 (integer) the express of discrete wavelet trans-form is

( ) ( ) ( )2, 2 2j j

nC j k T x t n kψ− −⎡ ⎤= ∆ −⎣ ⎦∑ ( ) 2,j k ∈ Z

(12) where the discrete wavelet ( )kψ is a sampled ver-sion of a continuous ( )tψ , and x(k) is a discrete sig-

nal. Discrete wavelet transform, where a signal is de-composed into so-called approximations and details, can be realized by the multi-rate filter bank.

To preserve originality signal, after every wavelet decomposition levels, the sampling radio could be halved. That is to say, we can get sampling date every other points in component of signal (low frequency and high frequency essential). Thus, the number of date point of component of signal in the j levels is half of that in the j−1 levels; the sizes of the training vector sets which would be introduced into ANN are smaller. The taper sampling process is shown in Fig. 2.

Fig. 2 Wavelet decomposition of signal

The proper choice of the mother wavelet plays a crucial role in the signal preprocessing. Several fami-lies have been proven to be useful in signal and image processing (such as the studies by Daubechies, Bior-thogonal, Haar, and Shanon). Each family has specific properties which make them suitable for certain appli-cations. The Shanon wavelet has poor time localization, but its frequency localization is good because it has the spectrum of an ideal bandpass filter. On the other hand, Haar wavelet has good time localization, which is ex-traordinarily suited to extract those signal with brief duration and change rapidly[6]. Therefore, we use Harr wavelet as a starting point for the final wavelet type se-lection.

3 Simulation of Wavelet Decomposed and Low-Frequency Coefficient Extracted

This will now be illustrated by a sixth order 0.5-dB equi-ripple Chebychev low pass filter with a−3 dB cutoff at 5 MHz using a clock frequency of 20 MHz. it assumed that all of transistors have the same random error, hence the correlative sensitivity and absolute or statistical error can be figure out using Eqs. (6) and (7). The fault tolerance would be obtained after add or sub-tract the deviation from normal curve.

To analyze the infection of transistor width and length system errors caused by technics and pervasion, using the cohor of which normalized transconductance value is 1 and the error is ±15％, the correlative sensi-

GUO Jierong (郭杰荣) et al：Test Mismatch in Switched-Current Circuits … 233

tivity and deviation are calculated. The lower bound of gain tolerance formed from the difference between normal curve and deviation as shown in Fig. 3. Along with the increase of mismatch, the lower bound of gain tolerance goes beyond the nominal value and descends gradually. The lower bound of reverse mismatch has the unambiguous distortion.

Fig. 3 Mismatch lower bound of gain tolerance

The programmed of HAAR decomposed and low frequency coefficient extracted is shown as follows:

[c, 1] wavedec (s, 3, “HAAR”): % the third scale decomposed using HAAR;

ca1 = appcoef (c, 1, “HAAR”, 1); % extracted the first scale low frequency coefficient A1 from [c, 1]

ca2 = appcoef (c, 1, “HAAR”, 2); % extracted the second scale A2 from [c, 1]

ca3 =appcoef (c, 1, “HAAR”, 3); % extracted the third scale low frequency coefficient A3 from [c, 1].

ca1, ca2, and ca3 are the low frequency coefficients of the first, second, and third scale, respectively. Figure 4

Fig. 4 Ideal frequency response after wavelet decom-position at level 3

is the ideal frequency response after wavelet decompo-sition and the Fig. 5 is the fault frequency response, re-spectively.

Fig. 5 Fault frequency response after wavelet decom-position at level 3

4 Conclusions and Future Work

Mismatch effect and circuit performance deviation er-ror caused by current scaling could be decomposed as coefficient of “low frequency essential” (Aj) and “high frequency essential” (Dj) via wavelet transform. The exact identification of fault signal could be achieved after multilayer decomposed. The analysis of sensitiv-ity based on transconductance in the design process provides an accurate selection for optimization pa-rameters and a forecast of performance results. Circuit test could be achieved through the comparison of de-viations calculated from sensitivity of the results with the nominal circuits.

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Test mismatch in switched-current circuits using wavelet analysis