Test and Test Equipment July 2011 San Francisco, California Dave Armstrong ITRS 2011 Test and Test Equipment – San Francisco, CA

Test and Test Equipment July 2011

San Francisco, CaliforniaDave Armstrong

ITRS 2011 Test and Test Equipment – San Francisco, CA

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2011 Test TeamAkitoshi NishimuraAmit MajumdarAnne GattikerAtul GoelBill PriceBurnie WestCalvin CheungChris Portelli-HaleDave ArmstrongDennis ContiErik VolkerinkFrancois-Fabien FerhaniFrank PoehlHirofumi TsuboshitaHiroki IkedaHisao HoribeBrion Keller Nilanjan 'Mukherjee'Rohit Kapur

Sanjiv TanejaSatoru TakedaSejang OhShawn FetterolfShoji IwasakiStefan EichenbergerSteve ComenSteve TildenSteven SlupskyTakairo NagataTakuya KobayashiTetsuo TadaUlrich SchoettmerWendy ChenYasuo SatoYervant ZorianYi Cai

Jerry McbrideJody Van HornKazumi HatayamaKen LanierKen TaokaKen-ichi AnzouKhushru ChhorMasaaki NambaMasahiro KanaseMichio MaekawaMike BienekMike Peng LiMike RodgersPaul RoddyPeter MaxwellPhil NighPrasad MantriRene SegersRob AitkenRoger Barth


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2011 Changes

• New Section on 3D Device Test Challenges• Updated Adaptive Testing section• Logic / DFT

– Major re-write of this section thanks to the addition of some new team members representing the major three EDA vendorsr

• Numerous other changes to specialty devices info.• Test Cost

– Test cost survey completed that quantifies industry view

• Other updates will be published for the Logic, Consumer/SOC, RF, ad Analog section.

ITRS 2011 Test and Test Equipment San Francisco, CA

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Test Cost Components

NRE•DFT design and validation•Test development

Device•Die area increase•Yield loss

UntestedUnits

Work Cell•Building•People•Consumables•DUT Interface•Test Equipment•Handling Tools•Factory Automation

Good Units

Reject Units

FalsePassUnits

False Fail Units

Previous DataMore challenges in the future


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Test Cost Components


Device•Die area increase•Yield loss

UntestedUnits Test Cell

Good UnitsReject Units

FalsePassUnits

False Fail Units

3D Technology AddMany Challenges

ProbablyGood Units

ProbablyGood Units




ProbablyGood Units

Test Cell

Rejected Units

Pass/Fail

Good Die in a Failing Stack

SmartManufacturing


Wafer ProbeWafer Probe

Final TestFinal Test

Burn-inBurn-in

Stack / Card / Stack / Card / System TestSystem Test

• Fab data• Design data• Business data• Customer specs

“RT A/O” stands for “Real-Time Analysis &

Optimization”

ETestETestOptical InspectionOptical Inspection

Other inline dataOther inline dataAssembly/Build DataAssembly/Build Data

FABFAB

Field OperationField Operation

RT A/OPTAD

“PTAD” is “Post-Test Analysis & Dispositioning” PTAD

PTAD

PTAD

PTAD

Databases & Automated Databases & Automated Data AnalysisData Analysis

(This may include multiple databases. ‘Analysis’ includes

capabilities like post-test statistical analysis, dynamic routings and

feedforward data.)

Databases & Automated Databases & Automated Data AnalysisData Analysis

(This may include multiple databases. ‘Analysis’ includes

capabilities like post-test statistical analysis, dynamic routings and

feedforward data.)

Assembly Assembly OperationsOperations

(This includes test operations at any

level of assembly.)

RT A/O

RT A/O

RT A/O

Adaptive Test FlowAdaptive Test Flow

Unchanged

Revised

New

Drop

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2011 Drivers

• Device trends– Increasing device interface bandwidth and data rates– Increasing device integration (SoC, SiP, MCP, 3D packaging)– Integration of emerging and non-digital CMOS technologies– Complex package electrical and mechanical characteristics– Device characteristics beyond the deterministic stimulus/response model– 3 Dimensional silicon - multi-die and Multi-layer– Multiple Power modes and Multiple time domains– Fault Tolerant architectures and protocols

• Test process complexity– Device customization / configuration during the test process– “Distributed test” to maintain cost scaling– Feedback data for tuning manufacturing– Adaptive test and Feedback data– Higher Order Dimensionality of test conditions– Concurrent test within a DUT– Maintaining unit level test traceability


2011 Drivers (2)• Economic Scaling of Test

– Physical and economic limits of packaged test parallelism– Test data volume and feedback data volume– Effective limit for speed difference of HVM ATE versus DUT– Managing interface hardware and (test) socket costs– Trade-off between the cost of test and the cost of quality– Balancing General Purpose Equipment vs. Multiple Insertions for System Test

and BIST

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UnchangedRevised

NewDrop


2011 Difficult Challenges• Cost of Test and Overall Equipment Efficiency

– Progress made in terms of test time, capital cost, multisite test– Continued innovation in DFT, Concurrent Test, Balancing DPM vs. Cost– Gains in some cases are now limited by Overall Equipment Efficiency

• Test Development as a Gate to Volume Production (Time to Market)

– Increasing device complexity driving more complex test development.– Complexity also driven by the diversity of different types of device interfaces on a single

chip.

• Potential yield losses– Tester inaccuracies (timing, voltage, current, temperature control, etc)– Over testing (e.g., delay faults on non-functional paths)– Mechanical damage during the testing process– Defects in test-only circuitry or spec failures in a test mode e.g., BIST, power, noise– Some IDDQ-only failures– Faulty repairs of normally repairable circuits– Decisions made on overly aggressive statistical post-processing– Multi-die stacks / TSV– Power management issues

9ITRS 2011 Test and Test Equipment San Francisco, CA

UnchangedRevised

NewDrop

2011 Difficult Challenges (2)

• Detecting Systemic Defects – Testing for local non-uniformities, not just hard defects– Detecting symptoms and effects of line width variations, finite dopant

distributions, systemic process defects

• Screening for reliability– Effectiveness and Implementation of burn-in, IDDQ, and Vstress testing– Screening of multiple power down modes and binning based on power

requirements– Detection of erratic, non deterministic, and intermittent device behavior

10ITRS 2011 Test and Test Equipment – San Francisco, CA

UnchangedRevised

NewDrop

2011 Future Opportunities• Test Program Automation

– Automatic generation of an entire test program.– Tester independent test programming language.– Mixed Signal still a test programming challenge

• Scan Diagnosis in the Presence of Compression

• Simulation and Modeling– Seamless integration of simulation & modeling into the testing process.– A move to a higher level of abstraction with Protocol Aware test resources.– Focused test generation based on layout, modeling, and fed back fabrication

data.

• Convergence of Test and System Reliability Solution– Re-use of test collateral in different environments (ATE, Burn-in, System,

Field)11

UnchangedRevised

NewDrop


Summary• Stacked devices change many things for test.

– The methods and approach seem available.– Considerable work ahead of us to implement.

• Adaptive testing is becoming a standard approach– Significant test data accumulation, distribution, and analysis

challenges.

• Ongoing changes to the RF, Analog, and Specialty devices.

• Many more details to be published in the final document.

Thank You!

Backup

TesterTester

Local DatabaseLocal DatabaseFor real-time data analysis & actions. For real-time data analysis & actions.

Resident on Tester or in Test Cell.Resident on Tester or in Test Cell.Latency: <1 second Retention: “hours”Latency: <1 second Retention: “hours”

Local DatabaseLocal DatabaseFor real-time data analysis & actions. For real-time data analysis & actions.

Resident on Tester or in Test Cell.Resident on Tester or in Test Cell.Latency: <1 second Retention: “hours”Latency: <1 second Retention: “hours”

Adaptive Test Database Architecture ExampleAdaptive Test Database Architecture Example

DatabaseDatabaseData availability for production – lot setup or Data availability for production – lot setup or

dispositioning.dispositioning.Latency: “minutes” Retention: “hours to days”Latency: “minutes” Retention: “hours to days”

DatabaseDatabaseData availability for production – lot setup or Data availability for production – lot setup or

dispositioning.dispositioning.Latency: “minutes” Retention: “hours to days”Latency: “minutes” Retention: “hours to days”

Large DatabaseLarge DatabaseFor long-term storageFor long-term storage

Latency: “minutes”Latency: “minutes”Retention: “months” … with longer-term Retention: “months” … with longer-term

retrieval options. (data is available “forever”)retrieval options. (data is available “forever”)

Large DatabaseLarge DatabaseFor long-term storageFor long-term storage

Latency: “minutes”Latency: “minutes”Retention: “months” … with longer-term Retention: “months” … with longer-term

retrieval options. (data is available “forever”)retrieval options. (data is available “forever”)

World-wide, World-wide, cross-company cross-company

databasesdatabases

3D Device Testing Challenges

• Test Access• Die level Access• Die in Stack Access

• Test Flow/Cost/Resources• Heterogeneous Die in the Stack

• Die in Stack Testing• Die to Die Interactions

• Debug/Diagnosis• DFT• Test data managements, distribution, & security• Power Implications

SOC / Logic Update• Takes the device roadmap data and calculates:

• Fault Expectations both inside and outside the various cores using multiple fault models.

• Required test pattern lengths given five different assumptions:» Flat test patterns» Test implemented taking advantage of the circuit

hierarchy» Tests implemented using compressed flat patterns.» Tests implemented using compressed hierarchal test

patterns.» Using low power scan test approach.

LCD Device Probing Challenge OvercomeNew probe needle arrangement 4 layers + 4 layers = 8 layers

could provide solution for LCD driver probe pad continually narrow down.

Higher Site Count Camera Chips

Chief º

Max º

Max º

Min º

Chief ray

EP

D

D

Tan()= (D/2)/EPD

D=Pupil diameter

F-number = EPD / D

Single site Four sites

MEMs Sensors For Handheld DevicesGyro AccelerometersE-Compass Pressure

Expect a 10% yearly growth

Documents

Test and Test Equipment July 2011 San Francisco, California Dave Armstrong ITRS 2011 Test and Test Equipment – San Francisco, CA