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TEMPERATURE-AWARE DESIGN OF ANALOG BUILDING
BLOCKS FOR SIGMA-DELTA CONVERTERS
Adriano Vianna Fonseca
Projeto de Graduação apresentado ao Curso
de Engenharia Eletrônica e de Computação
da Escola Politécnica, Universidade Federal
do Rio de Janeiro, como parte dos requisitos
necessários à obtenção do título de Engenheiro.
Orientador: Fernando A. P. Barúqui
Rio de Janeiro
Março de 2019
UNIVERSIDADE FEDERAL DO RIO DE JANEIRO
Escola Politécnica - Departamento de Eletrônica e de Computação
Centro de Tecnologia, bloco H, sala H-217, Cidade Universitária
Rio de Janeiro - RJ CEP 21949-900
Este exemplar é de propriedade da Universidade Federal do Rio de Janeiro, que poderá
incluí-lo em base de dados, armazenar em computador, microfilmar ou adotar qualquer
forma de arquivamento.
É permitida a menção, reprodução parcial ou integral e a transmissão entre bibliotecas
deste trabalho, sem modificação de seu texto, em qualquer meio que esteja ou venha a
ser fixado, para pesquisa acadêmica, comentários e citações, desde que sem finalidade
comercial e que seja feita a referência bibliográfica completa.
Os conceitos expressos neste trabalho são de responsabilidade do(s) autor(es).
iv
DEDICATÓRIA
Dedico este trabalho a todos os meus amigos da UFRJ que passam ou já passaram por
momentos em que a pressão do curso foi insuportável. O curso tem sim um fim, então
não desistam. Espero que este trabalho sirva de motivação.
v
AGRADECIMENTO
Aos meus pais, avós e irmãos pelo apoio incondicional em minha formação humana
e acadêmica. A todos os professores do Departamento de Engenharia Eletrônica e de
Computação da Escola Politécnica, minha gratidão por todo o aprendizado ao longo do
curso. Aos meu orientadores, Prof. Fernando Barúqui e Prof. Pietro Maris pela paciência
e dedicação ao longo do desenvolvimento do projeto. De modo especial, a todos os meu
amigos e companheiros sem os quais esse curso teria sido impossivel. A minha vida foi
marcada pela ajuda e companhia de cada um de vocês.
"Se eu vi mais longe, foi por estar sobre ombros de gigantes" - Sir Isaac Newton
vi
RESUMO
O advento da Internet das Coisas (IoT) trouxe a necessidade de novos estudos para se
adequar aos seus requisitos extensivos, direcionados especificamente pelo setor de Veícu-
los Inteligentes, os quais devem ser capazes de detectar e se comunicar de forma eficiente
com outros veículos próximos, incluindo carros, ônibus e caminhões. Por razões óbvias, o
projeto e as especificações dos circuitos microeletrônicos utilizados nessas aplicações são
regulados por uma grande quantidade de rigorosos padrões de confiabilidade e segurança.
Estas características, além da garantir a robustez na operação do dispositivo, devem ser
asseguradas para condições adversas, incluindo a faixa de temperatura operacional re-
querida de −50 oC a 175 oC, que é, possivelmente, o desafio ambiental mais difícil para
a eletrônica na indústria automotiva. Ou seja, para enfrentar o desafio IoT, os veícu-
los inteligentes devem integrar sistemas eletrônicos de alto desempenho em uma ampla
faixa de temperatura. No domínio da detecção inteligente de veículos, a interface analóg-
ica para digital também é um desafio. Os conversores analógico-digitais (ADCs) devem
permanecer confiáveis mesmo diante dessas variações ambientais. Uma das arquiteturas
mais comuns é o conversor Sigma Delta, que é projetado com circuitos comparadores e
amplificadores operacionais de última geração. Tendo em vista estas necessidades, este
estudo visa a minimização das variações de parâmetros de um ADC oriundas de variações
de temperatura. Este trabalho analisa os efeitos da temperatura em dispositivos MOS e
estende esta análise para cobrir os parâmetros dos blocos análogicos basicos dos con-
versores Sigma Delta, comparadores e amplificadores operacionais de transcondutância
(OTA), a fim de abordar as variações de desempenho e propor uma metodologia de pro-
jeto insensível à temperatura. No que diz respeito à literatura, esta é a primeira tentativa
de expor os trade-offs de temperatura com a conhecida metodologia gm
ID.
Palavras-Chave: temperatura, confiabilidade, ADC, Sigma Delta, comparadores, OTA,
gm/ID.
vii
ABSTRACT
The advent of the Internet of Things (IoT) has brought the need for novel studies to con-
form to its extensive requirements. One IoT domain is the Smart Vehicle industry. These
Smart Vehicles have many special needs that must be attended to. They must be able to
efficiently sense and communicate with other nearby vehicles, including cars, buses and
trucks, and efficiently and reliably manage their resources. For obvious reasons, the de-
sign and specification of the microelectronic circuits, which are used in these applications,
are regulated by a large number of strict security and safety standards. These character-
istics, besides guaranteeing robustness in device operation, must be ensured for harsh
environments, including the required operating temperature range from −50 oC to 175
oC, which is arguably the most difficult environmental challenge for electronics in the au-
tomotive industry. So in order to meet the IoT challenge, smart vehicles should integrate
high performance electronic systems over a wide range of temperature. In the field of
intelligent vehicle detection, the analog to digital interface is also a challenge. Analog-to-
digital converters (ADCs) must remain reliable even when faced with these environmental
variations. One of the most common architectures is the Sigma Delta converter, which is
designed with comparator circuits and state-of-the-art operational amplifiers. In view of
these needs, the goal of this study is to minimize changes in ADC parameters caused by
temperature variations. This work analyzes the effects of temperature on MOS devices
and extends the analysis to cover the parameters of the basic analog blocks of the Sigma
Delta converters, comparators and operational transconductance amplifiers (OTA). This is
done in order to address the performance variations and propose a temperature-insensitive
design methodology. As far as the literature is concerned, this is the first attempt to expose
the temperature trade-offs with the well-known gm
IDmethodology.
Key-words: temperature, reliability, ADC, Sigma Delta, latched-comparators, OTA,
gm/ID.
viii
Contents
1 Introduction 1
2 Sigma Delta 5
2.1 Sigma Delta Converter Analysis . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Noise Shaping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 System Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 MOS Transistor Models 10
3.1 Quadratic and Sub-threshold Models . . . . . . . . . . . . . . . . . . . . 10
3.1.1 Quadratic Model Equations . . . . . . . . . . . . . . . . . . . . 13
3.1.2 Sub-threshold Equations . . . . . . . . . . . . . . . . . . . . . . 15
3.2 EKV Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2.1 WI Approximation . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.2 SI Approximation . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.3 Lambert’s W Function . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.4 Lambert Small-Signal Parameters . . . . . . . . . . . . . . . . . 21
3.3 The gm
IDMethodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3.1 gm
IDas an Inversion Region Model . . . . . . . . . . . . . . . . . 22
3.3.2 gm
IDTestbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3.3 gm
IDDesign Example . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4 Temperature Effects in MOS Transistors 28
4.1 Bias-dependent Temperature Instability . . . . . . . . . . . . . . . . . . 28
4.2 gm/ID -Based Temperature Effects . . . . . . . . . . . . . . . . . . . . . 31
ix
4.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5 Temperature-Aware Analysis of Latched Comparators 37
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.2 Temperature Dependent Analysis . . . . . . . . . . . . . . . . . . . . . . 38
5.2.1 Temperature Effects . . . . . . . . . . . . . . . . . . . . . . . . 38
5.2.2 StrongArm Delay . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.2.3 Double-Tail Delay . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.2.4 Comparator Offset . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.3 Post-Layout Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6 Operational Transconductance Amplifier 50
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.2 Understanding the OTA Topology . . . . . . . . . . . . . . . . . . . . . 50
6.3 Temperature-Aware OTA Design . . . . . . . . . . . . . . . . . . . . . . 52
6.3.1 Temperature-Aware OTA design . . . . . . . . . . . . . . . . . . 52
6.3.2 Temperature-Aware OTA design examples . . . . . . . . . . . . . 55
6.4 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
7 Conclusion 63
Bibliography 65
A Appendix A 69
x
List of Figures
1.1 ADC architectures and their sampling rate against resolution trade-offs.
(adapted from: www.analog.com/en/analog-dialogue/ articles/the-right-
adc-architecture.html). . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 A bottom-up approach for hierarchical reliability analysis [1]. . . . . . . 4
2.1 Pulse-density modulated output for an input sinusoidal wave. . . . . . . . 5
2.2 First-order Sigma Delta converter topology. . . . . . . . . . . . . . . . . 7
2.3 Noise shaping phenomenon for an input tone in a First-order Sigma Delta
converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 The n-channel MOS transistor [2] . . . . . . . . . . . . . . . . . . . . . 11
3.2 The n-channel MOS transistor schematic [2] . . . . . . . . . . . . . . . . 11
3.3 The n-channel MOS biasing scheme [2] . . . . . . . . . . . . . . . . . . 12
3.4 The n-channel in a MOS transistor [2] . . . . . . . . . . . . . . . . . . . 12
3.5 Saturation in a MOS transistor [2] . . . . . . . . . . . . . . . . . . . . . 13
3.6 IDS × VDS for various values of VGS. . . . . . . . . . . . . . . . . . . . . 14
3.7 Channel modulation in a MOS transistor [2] . . . . . . . . . . . . . . . . 14
3.8 IDS for NMOS and PMOS in EKV model . . . . . . . . . . . . . . . . . 16
3.9 IDS versus VGS in WI and MI . . . . . . . . . . . . . . . . . . . . . . . . 19
3.10 IDS versus VGS in MI and SI . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.11 IDS versus VDS for Lambert and quadratic models . . . . . . . . . . . . . 20
3.12 gm
IDRatio for nel and pel transistors . . . . . . . . . . . . . . . . . . . . . 23
3.13 A pseudo-Wilson current mirror test bench for electrical simulation ex-
periments: nel transistor illustration (similar setup for pel transistor). . . . 24
3.14 Transistor fT versus JDS for nel and pel . . . . . . . . . . . . . . . . . . 25
3.15 Transistor VGS versus JDS for nel and pel . . . . . . . . . . . . . . . . . 25
xi
3.16 Transistor gds
IDversus JDS for nel and pel . . . . . . . . . . . . . . . . . . 26
3.17 Example active load amplifier. . . . . . . . . . . . . . . . . . . . . . . . 26
3.18 Simulated AV voltage gain for example amplifier. . . . . . . . . . . . . . 27
4.1 JDS variation due to temperature instability for diode-connected transis-
tors (VGS = VDS) biased from 0.4 to 1.0 V for nel (continuous line) and
pel (dashed line) transistors. The temperatures are -55 oC (black), 27 oC
(dark gray), and 175 oC (light gray). . . . . . . . . . . . . . . . . . . . . 31
4.2 SJDS
T for a W = 1 µm and L = 180 nm nel transistor simulated using the
Lambert’s W function and the EKV model. . . . . . . . . . . . . . . . . 32
4.3 Sensitivity analysis from simulation experiments for nel (continuous line)
and pel (dashed line) transistors at temperature range from -55 to 175 oC
(T0 = 27 oC): (a) JDS sensitivity; (b) gm/ID sensitivity. . . . . . . . . . . . 35
4.4 Sensitivity analysis from simulation experiments for nel (continuous line)
and pel (dashed line) transistors at temperature range from -55 to 175 oC
(T0 = 27 oC): (a) gm/gDS sensitivity; (b) fT sensitivity. . . . . . . . . . . 36
5.1 Comparator Schematic of (a) StrongArm; (b) Double-tail. . . . . . . . . . 38
5.2 Latched comparators’ layout of (a) SA having an area of 49 x 10 µm2 and
(b) DT having 52 x 10 µm2. . . . . . . . . . . . . . . . . . . . . . . . . 44
5.3 Post-layout transient simulation of (a) X1 and VOUT m for SA; and (b) fp
and VOUT p for DT comparators in a temperature variation of −40 oC
(dashed blue line), 27 oC (continuous black line), and 175 oC (dashed-
dotted red line). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.4 A 151-points Monte Carlo post-layout simulation for a 11-points tem-
perature variation in a range from −40 oC to 175 oC for SA and DT
comparator delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.5 A 151-points Monte Carlo post-layout simulation for a 11-points tem-
perature variation in a range from −40 oC to 175 oC for SA and DT
comparator σVOS,i−total. . . . . . . . . . . . . . . . . . . . . . . . . . . 47
xii
5.6 A 151-points Monte Carlo post-layout simulation for a 11-points tem-
perature variation in a range from −40 oC to 175 oC for SA (solid line)
and DT (dotted line) comparator input-referred noise mean and standard
deviation (square marks). . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1 OTA Topology Operation. . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.2 OTA Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.3 OTA block representation. . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.4 GBW sensitivity analysis with unfixed current in the differential pair M1,2
and M9 transistors at temperature range from -55 to 175 oC (T0 = 27 oC). 54
6.5 SGBWT for a W = 1 µm and L = 180 nm nel transistor simulated using the
Lambert’s W function and the EKV model. . . . . . . . . . . . . . . . . 55
6.6 Electrical Simulation of LP (circle-marked continuous line), SR ZTC (diamond-
marked dashed line), and GBW ZTC (square-marked dotted line) designs
for temperature variation from −55oC to 175oC: (a) gain bandwidth in
MHz, (b) gain in dB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.7 Electrical Simulation of LP (circle-marked continuous line), SR ZTC (diamond-
marked dashed line), and GBW ZTC (square-marked dotted line) designs
for temperature variation from −55oC to 175oC: (a) slew-rate in V/µs,
(b) power consumption in µW. . . . . . . . . . . . . . . . . . . . . . . . 61
6.8 Electrical Simulation of LP (circle-marked continuous line), SR ZTC (diamond-
marked dashed line), and GBW ZTC (square-marked dotted line) designs
for temperature variation from −55oC to 175oC: (a) common-mode re-
jection ratio in dB, and (b) power-supply rejection ratio in dB. . . . . . . 62
xiii
List of Tables
5.1 Transistor Sizing of SA and DT Comparators in (W x L). . . . . . . . . . 43
5.2 Performance Comparison of Comparators in 180nm Technology and 1.8V
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.1 Transistor sizing: width in µm having L = 0.72 µm. . . . . . . . . . . . . 56
6.2 Temperature Coefficient calculated from -55 oC to 175 oC. . . . . . . . . 58
A.1 Nel parameters in 180nm Technology for W = 1µm and L = 1µm . . . . 69
A.2 Nel parameters in 180nm Technology for W = 1µm and L = 0.18µm . . 69
A.3 Nel mismatch and temperature parameters in 180nm Technology . . . . . 70
A.4 Pel parameters in 180nm Technology for W = 1µm and L = 1µm . . . . 70
A.5 Pel parameters in 180nm Technology for W = 1µm and L = 0.18µm . . . 70
A.6 Pel mismatch and temperature parameters in 180nm Technology . . . . . 70
xiv
Chapter 1
Introduction
This work is a synthesis of the research done for the final graduation project. It was
developed in accordance with the requirements for the Electronics Engineering bachelor’s
degree at the Federal University of Rio de Janeiro (UFRJ).
The advent of the Internet of Things (IoT) has brought the need for novel studies
to conform to its extensive requirements. One IoT domain that has been getting much
attention is the Smart Vehicle industry. Companies such as Tesla and Google have put
much effort into such vehicles while attempting to automate them. These Smart Vehicles
have many special needs that must be taken care of. They must be able to efficiently sense
and communicate with nearby vehicles, including cars, buses and trucks, and efficiently
and reliably manage their resources. For obvious reasons, the design and specification of
the microelectronic circuits, which are used in these applications, are regulated by a large
number of strict security and safety standards.
Reliability and robustness in the device operation must be ensured for harsh envi-
ronments [3], to account for these safety standards. This includes the required operating
temperature range from −40 oC to 175 oC. This temperature range is arguably the most
difficult environment challenge for electronics in the automotive industry [4]. Hence,
to meet the IoT challenge, smart vehicles must integrate high performance electronics
in this adverse environment. This challenge calls for a reliability-aware methodology,
more specifically temperature reliability. These methodologies must be independent of
the CMOS technology [1].
This work focuses on the analog-to-digital converters (ADCs) in the smart vehicle
sensor, which are crucial for its autonomy. These ADCs should remain reliable even under
1
performance variation [5]. In smart sensing, Sigma Delta ADCs are the most common
solution to address low-power and high-speed. Figure 1.1 shows the difference types of
ADC used for different combinations of sampling rate and resolution. As can be seen
from this figure, this type of ADC trades sampling rate or conversion speed for a very
high resolution. This high resolution is in part provided by its noise immunity or noise
shaping, as will be explained in Chapter 2. However, Cai et al. have highlighted that the
Σ∆ modulator is a sensitive and unreliable building block [6].
This unreliability is manly due to the integrators and quantizers that compose the
converter. Usually the integrators are switched-capacitor or gm −C filters made up of
transconductance amplifier (OTA) circuits, and the quantizers are clocked comparators.
These blocks will be the main focus of this research.
The most common comparator designs are the StrongArm (SA) [7] and the Double-
Tail (DT) latched comparators [8]. Many studies compare the SA and DT topologies,
compiling a series of well-defined design parameters and considerations, even propos-
ing changes to further improve comparator performance. However, they lack the anal-
ysis of performance variability considering temperature variation. The same goes for
the OTA circuit: although some temperature-aware studies have been done [9], a formal
temperature-aware gm
Iddesign methodology is yet to be proposed.
This work overviews the temperature effects on MOS devices and extends the
overview to cover the comparators and OTA design parameters in order to address per-
formance variations and propose a temperature-aware design methodology. As far as the
literature goes, this is the first attempt at exposing temperature trade-offs with the well-
known gm
IDdesign methodology. The designs in this study are implemented using the
XH018 technology from the XFAB Silicon Foundries. The XH018 technology is ideal
for system-on-chip (SoC) devices inside combustion engine compartments or electric en-
gine housings with temperature range of up to 175 oC, as well as embedded low-voltage
applications in the communications, consumer and industrial market [10].
The methodology follows a bottom-up hierarchical reliability analysis such as the
one proposed in [1]. As seen in Figure 1.2 this begins as a process-level analysis of tran-
sistor physical parameters variation with temperature. This is followed by the effects of
such parameters on MOS transistor parameters (i.e. mobility µ and threshold voltage
VT H). It then move up to the effects of such variations on circuit performance, the perfor-
2
10 100 1K 10K 100K 1M 10M 100M 1G
Sampling Rate (Hz)
Res
olu
tion
(b
its)
24
22
20
18
16
14
12
10
Σ-Δ
Σ-Δ
SAR
PipelineState-of-the-
art
Industrial
Measurement
Voiceband,
audioData acquisition
High speed:
Instrumentation,
SDR, etc.
Figure 1.1: ADC architectures and their sampling rate against resolution trade-
offs. (adapted from: www.analog.com/en/analog-dialogue/ articles/the-right-adc-
architecture.html).
mance of the OTA and the comparators. The final step includes a full Sigma Delta system
verification of the temperature effects. This unfortunately is out of the scope of this study.
The main contributions of this work are as follows:
• A. V. Fonseca, Ludwig Cron, F. A. P. Baruqui, C. F. T. Soares, Philippe Benabes and
P. M. Ferreira, "A Temperature-Aware Analysis of SAR ADCs for Smart Vehicle
Applications," in Vol 13 No 1 (2018): Journal of Integrated Circuits and Systems.
— [11]
• A. V. Fonseca, R. E. Khattabi, W. A. Afshari, F. A. P. Baruqui, C. F. T. Soares, and
P. M. Ferreira, "A Temperature-Aware Analysis of Latched Comparators for Smart
Vehicle Applications," in ACM/IEEE Proc of SBCCI, 2017. — [12] Best Paper
Award
• P. M. Ferreira, A. V. Fonseca and J. Ou, "A Temperature-Aware OTA Design Method-
ology ," IEEE Trans. Circuits and Systems II:Express Briefs. — submitted
This text is organized as follows: Chapter 2 presents a brief introduction to the
3
Figure 1.2: A bottom-up approach for hierarchical reliability analysis [1].
Sigma Delta ADC. Chapter 3 overviews the MOS transistor models used in this study
and presents the gm
Iddesign methodology. Chapter 4 presents temperature effects on MOS
transistors. Chapter 5 is a study of the temperature effects on the well-known comparator
topologies, while Chapter 6 presents a gm/ID design methodology for temperature reliable
OTAs. The last chapter concludes the work.
4
Chapter 2
Sigma Delta
This chapter presents a brief introduction to the Sigma Delta (Σ∆) ADCs and what
aspects are critical for its operation. As previously stated, this type of converter is widely
used in SoC and IoT applications due to its robustness and high resolution together with a
low power consumption. Essentially a pulse-density modulator (PDM), the Σ∆ converter
boasts a higher quantization noise immunity when compared to other topologies.
A PDM converts an analog signal into a series of pulses of the same width, with
the density of pulses being higher where the analog signal level is higher. Figure 2.1 is a
visual representation of this. At time instances when the analog signal level is higher (0
to 1 V), there are more pulses per second, whereas for low analog levels (0 to -1 V) we
see fewer pulses. At the lowest and highest analog levels, the modulated output levels are
constant at a logic 1 or a logic 0 respectively. A 0 V modulator input causes the highest
switching frequency at the output.
Figure 2.1: Pulse-density modulated output for an input sinusoidal wave.
In order to be able to modulate the signal using this technique, the converter ana-
log input must first be sampled and oversampled, usually through polyphase filters. Over-
sampling essentially means sampling a signal well above the Nyquist rate to create redun-
dancy in its samples. This stage permits a spread of the input noise over the spectrum.
5
By raising the oversampling ratio (OSR), the same noise power is maintained except it is
now spread over a wider frequency range. For example, if the total input noise power is
N0 after an interpolation with OSR = M, the new total noise power in the signal band isN0M
.
The amount of oversampling is described by the oversampling ratio (OSR), which
is the ratio of the sampling frequency to the signal bandwidth:
OSR =fs
2 fc
, (2.1)
where fs is the sampling frequency and fc is the signal bandwidth. This oversampling
increases the converter resolution. This resolution can be measured by the equivalent
number of bits (ENOB), which is essentially how many bits of dynamic range are left
after the signal is distorted by noise. It is given by:
ENOB = n+0.5·log2OSR (2.2)
where n is the original resolution in bits.
This study focuses only on the modulation stage and not the oversampling stage.
2.1 Sigma Delta Converter Analysis
In this analysis, it is assumed that the input signal e[n] has already been sampled
and oversampled as it enters the Σ∆ converter. Figure 2.2 shows the topology of a first-
order Σ∆ converter. The 1z−1 block is the integrator, that will be implemented with the
OTA circuit, and the quantizer block is implemented using a latched comparator. The
quantizer block compares the y(n) signal to a reference signal (ref), usually VDD
2 , where
VDD is the supply voltage of the comparator. In other words,
s(n) =
1 if y[n]≥ ref
0 if y[n]< ref
The input-referred transfer function found from the diagram in Figure 2.2 is then:
S(z)
E(z)for N(z) = 0, (2.3)
6
Figure 2.2: First-order Sigma Delta converter topology.
where E(z), S(z) and N(z) are the Z-Transform of the input, output and quantization noise,
respectively. The quantization noise is defined as the noise added from y(n) to s(n) by the
quantizer. It follows that:
X(z) =E(z)−S(z)
z−1, (2.4)
where X(z) is the Z-transform of the integrator output. Therefore:
Y (z) = X(z)+E(z) = S(z)
S(z) =E(z)−S(z)
z−1+E(z)
(1
z−1+1)S(z) = (
1z−1
+1)E(z)
S(z) = E(z)
(2.5)
In other words, the input signal e(n) is directly represented at the output of the
converter, s(n). Supposing now that there is quantization noise, one may find its transfer
function:
S(z)
N(z)for E(z) = 0
S(z) =Y (z)+N(z)
S(z) =−S(z)
z−1+N(z)
N(z) = (1+1
z−1)S(z)
S(z)
N(z)=
z−1z
(2.6)
7
This effect on the quatizer noise is the known as noise shaping. The noise is
"shaped" as to have its power spectrum accumulated at higher frequencies.
2.2 Noise Shaping
Equation 2.6 shows the highpass filter behavior of the quantization noise transfer
function. This noise shaping is one of the key advantages of this type of converter and it is
what provides it with its considerably high resolution. Figure 2.3 shows this phenomenon.
This system simulation was made by applying gaussian white noise and a sampled tone
into the converter.
100
101
102
103
104
105
Frequency (Hz)
-80
-60
-40
-20
0
20
40
Ou
tpu
t S
pec
tru
m
Figure 2.3: Noise shaping phenomenon for an input tone in a First-order Sigma Delta
converter.
In this output spectrum, the tone, represented by an impulse at a single frequency,
is unchanged and the noise spectrum is pushed to a much higher frequency interval, ef-
fectively reducing the noise around the tone. A simple lowpass filter can then be added to
the output, to filter the shaped noise. Since in this example a first-order highpass filter is
acting on the noise, one may note that the noise-shaping slope increases at 20 dB/dec, so
by raising the order of the converter, the noise shaping slope can be even steeper:
S(z)
N(z)= (
z−1z
)L (2.7)
where is L is the filter order and the new slope will be L × 20dB.
8
2.3 System Considerations
In [1], Cai et al. identified aging effects in the Sigma Delta system parameters
and the most sensible blocks. More specifically, Negative Bias Temperature Instability
(NBTI) is identified as the most important component in system degradation. NBTI is the
generation of positive oxide charge and interface traps at the Si-SiO2 interface in CMOS
transistors with negative gate bias, in particular at elevated temperature [1]. This begins
to show temperature effects acting on the system.
Cai et al. identified the quantizer and DAC feedback blocks as the most critical
to system degradation, with a 25% increase in loop delay being considered failure. As
discussed in Chapter 5, temperature variations in comparator delay causes a greated delay
than permitted. As for the analog path, the integrator gain-bandwidth product was found
to be the most critical.
2.4 Conclusions
This chapter presented a brief overview of the Sigma Delta ADC. All the assump-
tions made in this chapter require that its analog blocks (i.e. OTA as high-gain amplifiers
and instantaneous comparators with no offset voltage) function reliably. This is not the
case for the wide temperature range studied in this research, as will be seen in the fol-
lowing chapters. The fact that this is the preferred topology in smart vehicle applications
makes identifying its temperature-related problems relevant.
9
Chapter 3
MOS Transistor Models
This chapter introduces the reader to the MOS (Metal Oxide Semiconductor) tran-
sistor models used in this text. First of all the quadratic model is explained, as well as
the small signal parameters extracted from it. From there, the reader is introduced to a
more complex inversion model, the EKV model [13]. Finally this model is applied to mo-
tivate and explain the gm
IDmethodology with parameter curves extracted from the XH018
technology used in this study.
3.1 Quadratic and Sub-threshold Models
The MOS transistor is a four-terminal device that marked the revolution of elec-
tronics in the 1970’s. There are many models available that attempt to emulate its be-
haviors (i.e. ACM [14], EKV [13], BSIM [15], quadratic), the most common being the
quadratic and exponential models, Sections 3.1.1 and 3.1.2. A physical understanding of
the MOS transistor is crucial to understand the equations used to describe it. The deduc-
tions focus on the n-channel transistors, but the p-channel equations can easily be derived
from them.
The n-channel MOS transistor is formed on a p-type silicon substrate where two
n-type diffusions are made, which comprise the source and drain of the device. Between
the diffusions, a very thin layer of silicon oxide is grown. This oxide layer is topped with a
high-conductivity polycrystalline silicon that forms the transitor gate, as shown in Figure
3.1. The Gate, Source, Drain and Bulk terminals are identified as G, S, D and B. The
channel that gives the device its name is formed under the gate oxide, which is a rectangle
10
of width W and length L. Figure 3.2 is a schematic representation of the device.
Figure 3.1: The n-channel MOS transistor [2]
Figure 3.2: The n-channel MOS transistor schematic [2]
The MOS transistor works in three operating regions: Cut-off, Ohmic or Triode,
and Saturation. In the Cut-off region the device is off and the Drain-to-Source current
(IDS) is zero. In the Triode region, the relation between IDS and Drain-to-Source voltage
(VDS) is basically linear, Figure 3.6. In the Saturation region, the device works as a current
source dependent on the Gate-to-Source voltage (VGS) and independent of VDS, Figure 3.6.
In Figure 3.3, the reader can see a bias scheme for the MOS transistor. If VGS < 0,
the device is Cut-off, however in this figure a small positive VGS is applied and a depletion
region is formed under the gate. For a very small VGS the channel is not yet formed
but IDS is not zero. In fact, electrons move through diffusion (diffusion current) from
Source to Drain due to the difference in charge concentration created by the VDS bias. In
this model the channel is only completely formed for VGS >VT H , the so-called threshold
voltage. The sub-threshold operation is known as Weak Inversion (WI), in other words
the substrate under the Gate has not yet completely inverted from p-type to the n-type
channel.
11
Figure 3.3: The n-channel MOS biasing scheme [2]
As soon as VGS > VT H , the gate is completely formed and the p-type substrate
has completely inverted into the n-type channel this is known as Strong Inversion (SI).
Between WI and SI, when the channel is not completely formed, is the Moderate Inversion
(MI). This region requires a more complex model. The IDS current is now composed by
the drift current induced in the channel by the electric field created by the VDS bias and
negligible diffusion current. Figure 3.4 shows the channel created under the Gate.
Figure 3.4: The n-channel in a MOS transistor [2]
As long as VDS < VGS −VT H , in SI, IDS is linearly proportional to the VDS voltage
following Ohm’s Law, VDS = κIDS where κ is a generic ratio. This is the Triode operating
region.
As VDS increases, the depletion region around Drain becomes bigger until it "pinches"
the channel at a voltage known as VDSsat or saturation VDS. This so called "pinch off" effect
can be seen in Figure 3.5.
From this on, IDS no longer increases with VDS and saturates at a value, hence
Saturation. The current does however still increase with VGS due to the increase in channel
size. In fact, the current increases approximately as the square of VGS, hence the Quadratic
Model.
12
Figure 3.5: Saturation in a MOS transistor [2]
Before deriving the equations, it should be clear to the reader the difference be-
tween operating and inversion region. The operating region has to do with the relation
of IDS with VDS and the channel "pinch-off". The inversion region has to do with how
completely the channel is formed. It is therefore possible to have Saturation or Triode in
WI, MI and SI. However, since the VGS required for WI is very small, the VDS necessary
to keep the device in the Triode region is impractical.
3.1.1 Quadratic Model Equations
In SI, IDS is expressed as a function of VGS and VDS by Equations 3.1 and 3.2 for
the Triode region and the Saturation region respectively,
IDS = µCOX
W
L[(VGS −VT H)VDS −
n
2V 2
DS] (3.1)
IDS =1
2nµCOX
W
L(VGS −VT H)
2 (3.2)
where µ is the carrier mobility (electron in the case of the n-channel MOS transistor),
and COX is the Gate oxide capacitance. The notation n is usually only used for the EKV
model and the notation α is usually chosen for this case, however these are equivalent
and represent the same parameter. This semi-empirical parameter is added to the Level
3 Spice model to account for narrow width and short channel effects in the "pinch-off"
voltage. Equation 3.2 is derived by making VDS =VDSsat =VGS −VT H in Equation 3.1.
Figure 3.6 shows the IDS × VDS curves for various values of VGS. The low VDS
linear region is the Triode region and the constant IDS is the Saturation region. The voltage
VDSsat indicates the transition between regions.
13
Figure 3.6: IDS × VDS for various values of VGS.
The small signal-parameters in Saturation can be derived from Equation 3.2. These
parameters exist in Triode but the Saturation equations are more interesting in most ap-
plications. These are the transconductance (gm), bulk transconductance (gmb) and the
Drain-to-Source conductance (gds).
gm = ∂ IDS
∂VGS=
õCOXW
nLIDS
gmb =∂ IDS
∂VBS= µCOXW
2nL(n−1)
gds =∂ IDS
∂VDS= λ IDS
(3.3)
The reason the partial derivative of IDS with respect to VDS is non-zero is that
the channel modulation phenomenon was ignored when deriving the equations. This
phenomenon causes IDS not to be completely independent of VDS, in fact it increases
slightly and linearly as VDS increases. The depletion region pushes the "pinch-off" point
towards the Source and decreases the effective L of the transistor. This effect can be seen
in Figure 3.7.
Figure 3.7: Channel modulation in a MOS transistor [2]
14
Therefore a more realistic equation for the effective IDS is:
IDSe f f = IDS{W
L−∆L} ≈ IDS(1+λVDS) (3.4)
3.1.2 Sub-threshold Equations
In WI, IDS is expressed as an exponential function of VGS and VDS instead of the
quadratic function seen in SI. Since the device is operating in the Saturation region, the
equation is independent of VDS. Equation 3.4 is used to express this function:
IDS = ID0eVGS−VTH
nφT (3.5)
where φT is the thermal voltage, usually around 26 mV, and n is dependent on the Fermi
voltage of the semiconductor substrate. These are given by:
φT =kBT
q(3.6)
n = 1+γ
2√
2φF +VSB
(3.7)
where kB is the Boltzmann constant, T is the temperature in Kelvin, q is the electron
charge, γ is a body effect constant and φF is the Fermi voltage of the substrate semicon-
ductor.
The small-signal parameters can be derived according to the following equations:
gm = ∂ IDS
∂VGS= IDS
nφT
gmb =∂ IDS
∂VBS= (n−1)IDS
nφT
gds =∂ IDS
∂VDS= λ IDS
1+λVDS
(3.8)
Other phenomena that were not explained in this section affect the MOS transistor.
These include the body effect, according to which the threshold voltage varies with VSB
(in a way this effect was used when deriving the equation for gmb), electron velocity
saturation and others.
In order to derive the same equations for the p-channel device, simple changes
must be made to the equations. The reference for every current and voltage must be
15
switched (i.e. IDS−> ISD,VGS−>VSG) and the threshold voltage VTH should be changed
to |VT H |.Figures 3.1, 3.3, 3.4, 3.5 and 3.7 were adapted from [2] with permission from the
author.
3.2 EKV Model
The models seen in Section 3.1.1 are very limited and do not generalize for all
inversion regions. They present a considerably large error in the MI and WI, as well as
some imprecision in SI. Most deductions in this study require a more complex inversion
model.
The EKV model was developed by C. C. Enz, F. Krummenacher and E. A. Vittoz,
hence the initials [13]. It is a compact, symmetrical model that covers all modes of oper-
ation and inversion regions. In this model, IDS is composed of two currents, the forward
and reverse currents, IF and IR, as,
IDS = IF − IR (3.9)
These can be seen for the NMOS (n-channel) and PMOS (p-channel) in Figure
3.8.
Figure 3.8: IDS for NMOS and PMOS in EKV model
If IF ≈ IR the device is in the Triode region, if IF >> IR or IR >> IF the device is in
forward or reverse Saturation respectively. In this model, forward and reverse Saturation
are defined due to symmetry in the MOS transistor. To be in accordance with the models
16
previously seen, only forward saturation will be considered. These currents are given by
the equation:
IF,R =VG −VT H −nVS,D
nφT
=√
1+4 · ICF,R−1+ ln(√
1+4 · ICF,R−1)
− ln(2) (3.10)
where ISP or specific current is given by:
ISP = 2nφ 2T µ COX
W
L(3.11)
and IC is the inversion coefficient given by:
ICF,R =IF,R
ISP
(3.12)
This inversion coefficient can be used to define the device inversion region. A
low ICF,R characterizes a diffusion-dominated IF,R and a high coefficient characterizes a
drift-dominated IF,R. Therefore, the device inversion (IC) is defined as max(ICR, ICF). If
IC << 1, the device is diffusion-dominated and therefore in WI. If IC ≈ 1 the device has
an equal order of magnitude of both and is therefore in MI. Finally if IC >> 1 the device
is drift-dominated and in SI.
IC << 1 →W I (3.13)
IC ≈ 1 → MI (3.14)
IC >> 1 → SI (3.15)
Some solutions make it possible to find a direct equation for the current as a func-
tion of the bias voltages. One can approximate the function in both inversion extremes,
suppose IC >> 1 or IC << 1, as in sections 3.2.1 and 3.2.2. There is also an interpolation
function that attempts to define Equation 3.10 in all inversion regions. This interpolation
function, however, is not shown as this study presents an analytic solution to this equa-
tion. Lastly, one may find an analytic solution for all inversion regions using Lambert’s
W function [16], Section 3.2.3.
17
3.2.1 WI Approximation
In WI, IC << 1 and therefore√
1+4 · IC ≈ 1+2 · IC. This comes from√
1+ x ≈1+ x
2 for x << 1. The new equation is thus given by:
VG −VT H −nVS
nφT
= 2 · IC+ ln(2 · IC)− ln(2) (3.16)
Equation 3.16 is simplified into an exponential form such as the one in Section
3.1.2,
IDS = ISP eVG−VT H−nVS
nφT (3.17)
3.2.2 SI Approximation
In SI, IC>> 1 and therefore√
1+4 · IC+ ln(√
1+4 · IC−1)≈√
1+4 · IC. This
comes from x+ ln(x−1) ≈ x for x >> 1. The new equations for Triode and Saturation
are thus given by,
IDS = µCOX
W
L[(VG−VT H)VDS −
n
2(V 2
D −V 2S )] (3.18)
IDS =1
2nµCOX
W
L(VG−VT H −nVS)
2 (3.19)
These are similar to the Quadratic model in Section 3.1.1.
3.2.3 Lambert’s W Function
These approximations suppose a device well into these inversion regions, leaving
MI inversion unaccounted for. Equation 3.16 can, however, be solved in an analytic form
giving exact results in every inversion region by using Lambert’s W function (W). W
solves for y in the form,
x = yey ⇒ y =W (x) (3.20)
Therefore Equation 3.16 is manipulated as to be in the form,
2eVG−VTH−nVS,D
nφT︸ ︷︷ ︸
x
=(√
1+4 · ICF,R−1)
︸ ︷︷ ︸
y
)e
√
1+4 · ICF,R−1︸ ︷︷ ︸
y (3.21)
Equations 3.21 and 3.12 give the exact solution found in Equation 3.22.
18
IF,R =ISP
4·[(
W
(
2eVG−VT H−nVS,D
nφT
)
+1
)2
−1
]
(3.22)
Figure 3.9 compares the natural log of Equation 3.22 in WI with the exponential
model, Equation 3.1.2, and Figure 3.10 Equation 3.22 with the quadratic model, Equation
3.1.1. These curves were found for a fixed VDS and a VGS varying from 0 to 0.6 V for
WI and MI and from 0.4 to 1.8 V for MI and SI. Figure 3.11 plots IDS versus VDS in
SI using the quadratic and EKV models for different VGS. The values φT = 0.026V ,
k = 293.4e−6 cm2/(V ·s), n= 1.2 and VT H = 0.4V were used as extracted from the XH018
technology.
Figure 3.9: IDS versus VGS in WI and MI
The error becomes apparent when the models are plotted together. Taking the
EKV model as the precise value, the exponential function has an error of 90% in WI and
in MI. The quadratic model, however, presents a greater error of 100% in MI but a much
smaller error of 10% in SI. This indicates that the quadratic model is a reasonably precise
model for a basic estimate of IDS versus VGS in SI.
The quadratic model also shows some difference, however, when plotting the IDS
versus VDS curves, as can be seen in Figure 3.11. The black line is the EKV model and
the gray line the quadratic model for different values of VGS. Each black EKV line has
its corresponding gray quadratic curve above it, each pair corresponds to the same value
of VGS. This discrepancy is due to the quadratic model suposition that the device is in
the strongest inversion possible, with IC → ∞. As the device IC increases, the difference
19
Figure 3.10: IDS versus VGS in MI and SI
between the two curves decreases.
Figure 3.11: IDS versus VDS for Lambert and quadratic models
From these current definitions, it is then possible to move on to some useful small-
signal parameters, especially the ones that will be used in the gm
IDanalysis.
20
3.2.4 Lambert Small-Signal Parameters
W can also be used to derive the small-signal parameters of the MOS device. Its
derivative is well defined,∂W (x)
∂x=
W (x)
x(1+W (x))(3.23)
From Equations 3.22 and 3.25,
gm = ∂ IDS
∂VG= ISP
2nφT
[
W
(
2eVG−VTH−nVS
nφT
)
−W
(
2eVG−VT H−nVD
nφT
)]
gms =∂ IDS
∂VS=− ISP
2φTW
(
2eVG−VT H−nVS
nφT
)
gmd = ∂ IDS
∂VD=− ISP
2φTW
(
2eVG−VTH−nVD
nφT
)
gds =∂ IDS
∂VDS= λ |IDS|
(3.24)
In the case of Saturation, where IF >> IR, Equation 3.24 for gm can be rewritten as:
gm =∂ IDS
∂VG
=ISP
2nφTW
(
2eVG−VT H−nVS
nφT
)
(3.25)
If rewritten as a function of IC, Equations 3.24 become:
gm = ISP
2nφT
(√4IC+1−1
)
gms =− ISP
2φT
(√4ICF +1−1
)
gmd =− ISP
2φT
(√4ICR +1−1
)
(3.26)
3.3 The gm
IDMethodology
This gm/ID methodology was introduced in [17] by Silveira et al., and has proven
to be exceedingly successful in nano-scaled transistor design. This methodology is appli-
cable whenever design is constrained by a parameter that is independent of a transistor
width. The basis for gm/ID is: transistors connected in parallel behave as a stand-alone
transistor with an equivalent width which is the sum of all the devices’ widths. The only
hypothesis behind this principle is that devices are biased at the same VGS. Thus, parallel
transistors have the same gm/ID characteristic as the equivalent stand-alone transistor.
The gm
IDratio versus the current density JDS =
IDS
W/Lis a powerful tool that visually
indicates the inversion level of the transistor as a function of its current per unit area.
21
Directly it translates into a lower gm
IDratio in SI and a higher ratio in WI. By deriving
the circuit expressions and representing them as a function of this ratio, it is possible to
achieve a detailed study of the circuit characteristics as a function of the inversion region.
Characteristics such as power consumption, speed and bandwidth can be easily traded-
off and the optimum inversion region can be found, either through simple equations or
through optimization algorithms [18],[19]. It also allows the user to operate the transistor
with the precision of more complex models such as the BSIM model or higher-level Spice
models, in all inversion regions. Its application in the optimization of trade-offs can be
found in [18] and a starter kit for those interested in learning about this methodology can
be found in [20].
3.3.1 gm
IDas an Inversion Region Model
The gm
IDratio is the derivative of the ID versus VG curve in a logarithmic scale,
gm
ID
=1ID
∂ ID
∂VG
=∂ (ln(ID))
∂VG
(3.27)
The maximum slope of this curve is the maximum gm
IDratio in WI and the minimum
in SI. This indicates that WI and MI are preferred for low-power designs due to their small
current per unit area and small VGS. The gm
IDratio also describes the transistor efficiency to
transform current (IDS) into transconductance (gm). The greater the gm
IDratio is, the greater
the transconductance is for a given current. This ratio can be best visualized in Figure
3.12. These were obtained for the nel and pel transistors (NMOS and PMOS transistors
in the XH0180 technology) at a fixed VDS of 900 mV and W/L (W = 1 um and L = 720
nm). The values of VDS and W do not have a considerable effect on these curves [19]. The
value of L does however, due to the channel modulation previously discussed. For these
curves, four times the minimum Lmin = 180 nm permitted by this technology was used.
The gm
IDratio can also be expressed as a function of the EKV inversion coefficient
as,gm
ID=
√4IC+1−12nφT IC
(3.28)
By applying the previously discussed limits for WI (IC << 1), MI (IC ≈ 1) and
SI (IC >> 1), it is possible to find the inversion limits in this new representation. For this
technology, these limits can be set in the following manner: for gm
IDhigher than 20 V−1
22
the transistor is in WI, for gm
IDlower than 10 V−1 the transistor is in SI, and for gm
IDbetween
these limits the transistor is in MI.
1n 10n 0.1u 1u 10u 0.1m 1mJDS
(A/ m)
0
10
20
30
gm
/ID
(V
-1)
nelpel
Figure 3.12: gm
IDRatio for nel and pel transistors
It is also important to note that for a given current, in order to increase the gm
IDratio,
the transistor must increase in size. Since L is usually set to a multiple of Lmin in order
to decrease channel modulation or set to Lmin for speed, the transistor channel width (W )
has to be increased. From this moment on, JDS is normalized to W = 1 um and L = 720
nm.
This brings about the first important trade-off. In order to yield a high gm while
maintaining the same gm
ID, both ID and W have to be increased. Increasing ID results in
an increase in power consumption, whereas increasing transistor size, and therefore the
gate-referred capacitance Cgg, results in a decrease in bandwidth.
3.3.2 gm
IDTestbench
The gm
ID× JDS curve and all other curves used in this design methodology can
be obtained through two main testbenches. The first and most simple one comprises of
varying all bias voltages of the transistor and saving the important parameters. gm
IDcan be
thought of as a function of VG, VD, VS and VB, although it tends to be fairly independent
of VDS and only certain values of VB are needed to populate the database.
The second testbench is the one shown in Figure 3.13. In this testbench, the curves
are obtained by setting the current on a normalized transistor (W = 1 µm and L= 780 nm)
biased with VSB = 0 V and VDS = 0.9 V, once again with the n-type (nel) and p-type (pel)
transistors. A similar setup was used for the pel transistor. Based on a pseudo-Wilson
23
JDS
I0 = ids
cccs
R ≈ 0
W = 1 µm
Lmin = 180 nm
VDS
ids
Figure 3.13: A pseudo-Wilson current mirror test bench for electrical simulation experi-
ments: nel transistor illustration (similar setup for pel transistor).
current mirror, the mirror is used to bias VGS so that IDS matches the reference current.
The provided feedback forces the transistor to a stable operating point as a function of a
reference JDS. In this way the testbench forces whatever VGS voltage is necessary to fix
the transistor drain current. When the device current ids is greater than JDS, there is excess
current in I0 and the gate voltage is decreased, thus reducing ids until ids = JDS. The same
is true if ids is smaller than JDS: the gate voltage is increased until ids = JDS.
Using these testbenches, a series of important curves, that will be used in the
design example, are derived. These curves include the fT × JDS, which is shown in
Figure 3.14, where fT is the transistor transition frequency. Device operation is usually
limited to fT/10. The transition frequency is given by:
fT =gm
Cgg
(3.29)
It can be concluded that although lower gm
IDratios provide low gain efficiency and
higher power consumption, they allow for much faster device operation.
Another important curve is VGS × JDS, it is used for biasing the transistor at the
correct current density. This curve is shown in Figure 3.15. gds
ID× JDS for the transistor
output impedance is shown in Figure 3.16. Other often used curves include gm
gds× JDS for
the transistor intrinsic voltage gain and CGS x JDS for small-signal models, among others.
3.3.3 gm
IDDesign Example
In order to demonstrate the usefullness of the gm
IDmethodology, it is applied to the
design of an active load amplifier such as the one shown in Figure 3.17. The design spec-
ifications are a voltage gain of at least 15 V/V, a bias current of 1 uA and operation in
24
1n 10n 0.1u 1u 10u 0.1m 1m
JDS
(A/ m)
0
10
20
30
40
50
f T (
GH
z)
nelpel
Figure 3.14: Transistor fT versus JDS for nel and pel
1n 10n 0.1u 1u 10u 0.1m
JDS
(A/µm)
0
0.2
0.4
0.6
0.8
1
VG
S
nel
pel
Figure 3.15: Transistor VGS versus JDS for nel and pel
WI. As is seen in the design, the gm
IDcoefficient chosen sets the gain directly in this topol-
ogy. This allows for a gain/speed/power trade-off that can be visualized solely through
the coefficient.
An adequate start would be to analyze Figure 3.16 and note that, in WI, this co-
efficient is constant. In fact for the nel transistor (Mn), gds
ID= 0.6446. For the pel (Mp),
gds
ID= 0.6806. In order to take advantage of this, a maximum JDS of 0.1 uA is set. From
3.12, this is still within the WI limits, and it allows for faster transistors at the limit of WI,
as can be seen from Figure 3.14.
The amplifier voltage gain is given by:
AV =gmn
gdsn +gdsp
(3.30)
25
1n 10n 0.1u 1u 10u 0.1m
JDS
(A/µm)
0.3
0.4
0.5
0.6
0.7
gds/I
D
nel
pel
Figure 3.16: Transistor gds
IDversus JDS for nel and pel
VDD
Mp
VOUT
Mn
VIN
VB1
VB2
Figure 3.17: Example active load amplifier.
where the n and p subscripts refer to the NMOS and PMOS.
From Equation 3.30, the amplifier voltage gain is given by:
AV =
gm
ID ngdsn
ID+
gdsp
ID
(3.31)
For the chosen current density, gmnID
= 25.7 V−1, by applying Equation 3.31, the
amplifier voltage gain comes out to ≈ 19 V/V. Since we want a bias current of 1 uA and a
JDS of 0.1 uA and both transistors share the same current, their width is given directly by:
W =ID
JDS
=1u
0.1u= 10 (3.32)
Since JDS is normalized for W = 1 um, both transistors need W = 10 um. The
26
length L is given by the parameters used in the extraction, therefore L = 720 nm. In order
to have this JDS, from Figure 3.15, VB1 = 1.8− 0.25 = 1.55 V and VB2 = 2.61 V. The
simulation results can be seen in Figure 3.18. A voltage gain of 19.376 V/V is achieved
and if the design approximations are taken into account, the result is very satisfactory.
10-1
100
101
102
103
104
105
Frequency (Hz)
19.373
19.3735
19.374
19.3745
19.375
19.3755
19.376
19.3765
Gai
n(V
/V)
Figure 3.18: Simulated AV voltage gain for example amplifier.
Straight away some trade-offs have been made. Maximizing voltage gain would
mean highest possible gm
ID, but that would mean longer transistor length, which would
mean lower cut-off frequency. Therefore a compromise in WI inversion limit while still
maintaining necessary voltage gain was found. It also important to note that the voltage
gain is tied down by the gm
IDratio, therefore one could simply plot a voltage gain × JDS
or gm
IDcurve. The design was also made easy by the curves obtained from the simulator
transistor model. When the design was tested, it yielded the necessary results.
3.3.4 Conclusion
This chapter presented MOS transistors and different ways they can be modeled.
The EKV model using the Lambert W function, as well as model parameters extracted
from the simulator models, will be used in the temperature-aware models. The motivation
behind the gm
IDtrade-offs was made clear by a simple amplifier design. The next chapter
improves the models to include temperature dependencies that are crucial for going up
the methodology hierarchy.
27
Chapter 4
Temperature Effects in MOS
Transistors
This chapter focuses on giving an overview of temperature-related effects on MOS
transistors. All simulations and curve fittings were done using the XH018 technology
from the XFAB Silicon Foundries. When deriving the temperature dependencies, this
technology allowed for a model that had been tested in the desired temperature range
from -40 oC to 175 oC. A brief discussion of the semiconductor physics involved is made
in this chapter, followed by a sensitivity analysis of the most important parameters and gm
ID
curves.
4.1 Bias-dependent Temperature Instability
Temperature variation has been widely studied in semiconductor physics. In 1995,
C. Park et al. described the trade-off between mobility (µ) and threshold voltage (Vth)
under temperature variation [21]. Two phenomena have been explored in later works.
The first phenomenon is an increase in IDS due to increasing temperature, resulting in
a positive temperature coefficient. The second phenomenon is a decrease in IDS due to
increasing temperature, resulting in a negative temperature coefficient.
Both phenomena are a combination of the resulting variation of µ and Vth. These
quantities are related to temperature variation according to Mathiessen’s equation and the
BSIM device model:
µ(T ) = µ0
[
∑s
As · (ξDS)βµs ·
(T
T0
)αµ]−1
[4], (4.1)
28
VT H(T ) =VT H0 +αVT H(T −T0) [15], (4.2)
where ξDS is the Drain-to-Source electric-field; µ0 and Vth0 are these quantities evaluated
at T0 = 300 K; αµsand αVth
are temperature coefficients; βµsis a bias coefficient; and As
are physical parameters independent of ξDS and temperature (T ).
While αVth≈−0.7 mV/K depends on oxide thickness (tox) and dopant concentra-
tion, Chain et al. have presented values for αµsand βµs
according to scattering mecha-
nisms that affect MOSFET inversion layer carrier mobility [4]. This temperature depen-
dence of the carrier mobility can be simplified to:
µ(T ) = µ0·(
T
T0
)−βµ
[4], (4.3)
where an overall value of βµ ≈ 1.7 for the nel and βµ ≈ 1.2 for the pel can be found
through electrical simulations.
A third temperature effect can also be considered when in WI diffusion-dominated
operation. The thermal voltage φT can be written as:
φT (T ) = φT 0·(
T
T0
)−1
(4.4)
One can observe the effect of temperature instability even in the simple model
equations. If the device is operating in SI drift-dominated operation, its current is given
by 3.19, therefore its current density simplifies to:
JDS =IDS
W=
12n
µCOX
L(VG −VT H)
2 (4.5)
by deriving this with respect to temperature:
∂JDS
∂T=
µCOX (VG −VT H)
2nL
(
−βµ(VG −VT H)
T−2αVT H
)
(4.6)
It is important to note that in all temperature-related derivations, VT H , µ and φT
represent the parameter at a given temperature and are not equivalent to VT H0, µ0 and φT 0.
By applying the parameters found on Appendix A for a 1 um2 device in Equation
4.6, one can show that this derivative is negative for any value of VG:
∂JDS
∂T< 0, for any VG (4.7)
This model, however, does not hold for WI and is only valid for VG >> VT H .
Therefore it can be assumed that in a drift-dominated regime, device current decreases
29
with temperature. When applying device current given by Equation 3.17, the current
density is given by:
JDS = 2nφ 2T
µ COX
Le
VG−VTHnφT (4.8)
By deriving this with respect to temperature:
∂JDS
∂T=
2nφT
Le
VG−VTHnφT
(2φT µ COX
T0− βµφT µ COX
T− µ COX αVTH
n− µ COX(VG−VT H)
nT
)
(4.9)
This equation is not as obvious to show the temperature dependence, but by ap-
plying the same parameters, one can show that this derivative is always positive for any
value of VG <VT H :
∂JDS
∂T> 0, for any VG <VT H (4.10)
This model is limited to WI on the other hand and is only valid for VG << VT H .
Therefore it can be assumed that in a diffusion-dominated regime, device current increases
with temperature.
Thus, temperature instability in semiconductor has a complex mechanism able to
either increase or decrease JDS. To clarify both phenomena, a simulation experiment is
carried out using a n-type (nel) and p-type (pel) low-Vth MOSFET of XH018 technology
of XFAB. Both nel and pel transistors are sized with W = 1 µm and L = 180 nm. Tran-
sistors are connected as diodes (i.e. VGS = VDS) from 0.4 to 1.0 V. Figure 4.1 illustrates
JDS at -55 oC (black), 27 oC (dark gray), and 175 oC (light gray) for nel (continuous line)
and pel (dashed line) transistors. Increasing- and decreasing-JDS regions can be noted. In
this experiment, JDS changes from diffusion to drift regime when VGS ≈ 0.67 V for nel
transistor and VGS ≈ 0.83 V for pel transistor.
This work focuses on transistor performance, which is mainly driven by JDS and
the two main parameters of mobility µ and threshold voltage VT H and their variation over
temperature. From a system point of view, it is important to highlight that performance
variation would mostly be influenced by leakage currents and physical interconnections
failure due to electromigration. Studies have proven that subthreshold leakage current
is exponentially dependent on temperature; and it doubles for every 10 oC increase in
temperature [22]. Physical interconnection failure due to electromigration is character-
ized by a mean time-to-failure equation derived by J. R. Black [23]. Black’s equation
30
0.4 0.6 0.8 1
VGS
(V)
10u
0.1m
1m
J DS (
A/m
)
nel @ -55 oC
nel @ 27 oC
nel @ 175 oC
pel @ -55 oC
pel @ 27 oC
pel @ 175 oC
Figure 4.1: JDS variation due to temperature instability for diode-connected transistors
(VGS = VDS) biased from 0.4 to 1.0 V for nel (continuous line) and pel (dashed line)
transistors. The temperatures are -55 oC (black), 27 oC (dark gray), and 175 oC (light
gray).
presents exponential dependence on temperature, being most problematic in wires having
high current density (e.g. power supply). Under temperature variation, the bottleneck of
system performance degradation would be power consumption increase and power supply
interconnections failure.
4.2 gm/ID -Based Temperature Effects
The sensitivity of any circuit variable y to a parameter x is defined as Syx = x/y ·
δy/δx. The sensitivity of JDS to T , calculated from from Equation 4.6, reveals that in SI
SJDS
T =−βµ − 2αVTHT
(VG−VT H)(4.11)
and in WI
SJDS
T =2T
T0−βµ − αVTH
T
nφT− (VG−VT H)
nφT(4.12)
The analysis done on the signs of these equations suggests that there is a bias operating
point where SJDS
T ≈ 0. This point, however, is difficult to show with these simple models,
and the more complete intrinsic EKV model is needed. In order to calculate the point of
31
insensitivity, one must use Lambert’s W equation for its analytical solution. The interpo-
lated model does not yield correct results in its derivatives.
A simulation of the current sensitivity at 300 K with respect to temperature using
Lambert’W equation yielded Figure 4.2. These are done for a nel device sized with W =
1 µm and L = 180 nm, all parameters were taken from Appendix A. One can see the point
of insensitivity and that it is a global minimum. The minimum is found to be at JDS = 43.9
uA/um and a gm/ID of 6.95 V−1. It is important to note that the point of insensitivity is
not ZTC in itself and in fact varies slightly with temperature. This minimum is specific to
300K as the sensitivity is calculated for a certain temperature.
10n 0.1u 1u 10u 0.1m 1m
JDS@ 27
oC (A µm)
-60
-40
-20
0
20
STJDS(dB)
Figure 4.2: SJDS
T for a W = 1 µm and L = 180 nm nel transistor simulated using the
Lambert’s W function and the EKV model.
In strong-inversion, the gm/ID characteristic is described under a square law; and
one can note that its sensitivity approaches asymptotically towards a negative coefficient
in strong inversion described by
Sgm/ID
T =2αVth
(VGS −Vth)2 , where
gm
ID=
2(VGS −Vth)
. (4.13)
In other words, in strong inversion, the temperature dependence of gm/ID is a result of
a decreasing Vth over temperature [4]. In the subthreshold bias region [22], temperature
coefficient in (4.13) approaches asymptotically towards
Sgm/ID
T =−1, wheregm
ID=
q
nkT. (4.14)
32
This dependence on temperature effect is a result of diffusion-dominated JDS having a
quadratic-dependent temperature coefficient, but no bias dependency. In moderate inver-
sion, however, this temperature-dependency is the result of the interactions between the
drift-dominated and the diffusion-dominated JDS [9].
A sensitivity analysis of gm/gDS reveals that
Sgm/gDS
T = Sgm/ID
T , wheregm
gDS
=gm
λ ID, (4.15)
if the channel-length-modulation coefficient (λ ) does not vary with temperature [22]. A
similar analysis can be carried out from Sgm/ID
T for strong-inversion and subthreshold bias
region sensitivity. A sensitivity analysis for the fT is described by
SfT
T = Sgm
T , where fT =gm
CGS
, (4.16)
if gate-to-source capacitance (CGS) is temperature independent.
To validate the theoretical sensitivity analysis, SJDS
T , Sgm/ID
T , Sgm/gDS
T , and SfT
T are
calculated from electrical simulations. The experiment is carried out using same tran-
sistors and conditions as previously illustrated in Figure 4.1. Figure 4.3(a) illustrates a
minimum SJDS
T at JDS = 67 uA/um for nel and JDS = 49 uA/um for pel (6 < gm/ID < 11).
These results show that the model used with Lambert’s W function works as a fine approx-
imation of the current sensitivity with respect to temperature, the point of insensitivy pre-
sented a gm
IDerror of 15%.Considering the complexity in modelling the temperature effects
and the fact that no other model of its kind can predict this point, these are satisfactory
results . Figure 4.3(b) shows the simulated Sgm/ID
T , and demonstrates that sensitivity does
not achieve a minimum. Figure 4.4(a) shows a minimum for JDS in the range of uA/um
(gm/ID ≈ 20), and a smaller sensitivity for nel transistors. Figure 4.4(b) shows a similar
trade-off for SfT
T as presented in Sgm/ID
T for nel; but pel transistor shows a smaller SfT
T with
a minimum in hundreds of nA/µm (i.e. gm/ID ≈ 25, weak-inversion). This bias point is
very interesting, but it has a drawback of using slower transistors biased in a low- fT point
(pel fT < 1 GHz).
4.3 Conclusions
It is possible to conclude in this chapter, that when deriving a temperature-aware
design, the inner workings of the trade-off between the mobility and the threshold voltage
33
are complex and significant enough that they must be accounted for. One thing is clear,
transistor parameters do not always presents an optimum temperature invariant point. Al-
though, as will be seen in later chapters, it is possible to take advantage of some of these
bias points, notably the point where JDS varies minimally with temperature.
These temperature related trade-off come down to the usual speed, consumption
and gain constraints that are present in every electronic system. This will become more
obvious when studying the OTA. In future chapters, the sensibility analysis presented here
will serve to explain the temperature-related effects observed in the system’s different
metrics, more specifically speed and gain.
34
1n 10n 0.1u 1u 10u 0.1m 1mJ
DS (A/ m)
-20
0
20S
TJds (
dB
)nel
pel
(a)
1n 10n 0.1u 1u 10u 0.1m 1m
JDS
(A/ m)
-15
-10
-5
0
5
10
STg
m/I
D (
dB
)
nelpel
(b)
Figure 4.3: Sensitivity analysis from simulation experiments for nel (continuous line) and
pel (dashed line) transistors at temperature range from -55 to 175 oC (T0 = 27 oC): (a) JDS
sensitivity; (b) gm/ID sensitivity.
35
1n 10n 0.1u 1u 10u 0.1m 1m
JDS
(A/ m)
-30
-20
-10
0
10S
Tgm
/gD
S (
dB
)nelpel
(a)
1n 10n 0.1u 1u 10u 0.1m 1mJDS
@27°C (A/ m)
-20
-10
0
10
STf T
(dB
)
nel
pel
(b)
Figure 4.4: Sensitivity analysis from simulation experiments for nel (continuous line) and
pel (dashed line) transistors at temperature range from -55 to 175 oC (T0 = 27 oC): (a)
gm/gDS sensitivity; (b) fT sensitivity.
36
Chapter 5
Temperature-Aware Analysis of
Latched Comparators
5.1 Introduction
One of the main blocks of the Sigma Delta ADC, the latched comparator is crucial
for the final quantization stage. This stage is responsible for converting the analog output
of the integrator filter into a 1 bit (VDD or VSS) value. The latched comparator works by
taking a logic decision at each clock cycle allowing for synchronization and fast response.
The most common comparator designs are the StrongArm (SA) [7] and the Double-Tail
(DT) latched comparator [8]. These comparators must be make fast decisions within the
allowed time and present low offset so as to not affect the output of the modulator. This
chapter will focus on explaining how these comparators work and why they are widely
used.
Another discussion in this chapter will be that many studies compare both SA and
DT topologies, compiling a series of well defined design parameters and considerations,
even proposing changes to better increase the comparators’ performances. However, they
lack the analysis of performance variability considering temperature variation. The ob-
jective of this chapter is then to propose a temperature-aware analysis of performance
variability in state-of-the-art latched SA and DT comparators. The temperature effects on
MOS devices derived in Chapter 4 will be used in order to cover the comparators design
parameters and address performance variations (i.e. offset, delay and noise).
37
5.2 Temperature Dependent Analysis
5.2.1 Temperature Effects
The effects of temperature on the transistor’s mobility (µ) and threshold voltage
(Vth) as deduced in Chapter 4 can be simplified to two equations. According to Math-
iessen’s equation 4.3 and the BSIM device model for threshold voltage 4.2.
In order to find temperature coefficients, electrical simulations were carried out
with approximately the same conditions as the transistors in the differential pairs of com-
parators. In other words VGS =VDD
2 = 900 mV and VDS =VDD = 1.8 V while maintaining
the same sizing. The extracted temperature coefficients in the XH018 180 nm technol-
ogy using n-type transistor are: αVth≈−0.7 mV/K, βµ ≈ 1.7. These results are required
when deriving the system dependencies in the comparators. One may note that the mobil-
ity presents a positive coefficient as this bias point is in the vicinity of the strong inversion
part of Figure 4.3(a). Since the transistors in the differential pair are biased with a com-
mon mode voltage of VDD/2, it is possible to conclude a near to strong inversion bias and
thus a drift-dominated current that decreases with the increase of temperature.
CLK
S2S1
CLK
S3 S4
CLK
VOUT pVOUTm
CLK
M7
M6
M4
M1 M2
M5
M3
VDD
X1 X2
CLK
VIN p VINm
(a)
CLKMtail1
M1 M2 VINmVIN p
M7 M8
¯CLK Mtail2
M9MR1
M10MR2
VDD
VDD
VOUT p VOUTm
fnfp
M3 M4CLK CLK
(b)
Figure 5.1: Comparator Schematic of (a) StrongArm; (b) Double-tail.
38
5.2.2 StrongArm Delay
The SA comparator, shown in Figure 5.1(a), is the improved version as designed
by [7]. The proposed temperature-aware analysis is based on a previous study presented
by Babayan-Mashhadi and Lotfi on the delay analysis of SA and DT comparators [24].
The operation of the SA comparator can be separated into three main phases: a pre-
charge, a decision delay and a regeneration phase. The pre-charge phase occurs for CLK
= 0 and the two latter for CLK = 1. In the pre-charge phase, switches S1-S4 are turned
on charging nodes X1, X2, VOUT p, and VOUT m to VDD. It will be assumed that by the time
CLK rises to 1 these nodes are completely charged. This is a very plausible assumption
considering a 100 MHz operating frequency for the comparator.
During the decision delay phase, M7 turns on permitting transistors M1 and M2 to
conduct. Each branch current, i.e. IDM1 and IDM2, begins to discharge nodes X1 and X2.
Assuming VIN p >VINm, the node X1 will discharge faster until it reaches the voltage level
of VDD −VT H , considering a node capacitance of CLX this would cause a first delay time
to1 described by,
to1 =CLXVT HN
IDM1,2, (5.1)
where the voltage difference is too small in this case. Thus, it can be considered that,
IDM1,2 = Ibias +gm∆V ≈ Ibias, (5.2)
where IDM1,2 is the total current that passes through either the transistor M1 or M2, gm is
the transistor’s transconductance; and VCM is the common mode bias voltage at the inputs
of the comparator.
When employing the quadratic model for the MOS transistor,
Ibias =12
µCoxW
L(VCM −VT H)
2. (5.3)
As soon as X1 reaches the voltage level of VDD−VT HN , the transistor M3 begins to
conduct and successively discharges the node VOUT m. This next step adds an extra delay
time to2 as
to2 =CLo |VT HP|
IDM1,2. (5.4)
The total time (to) to the latch enters in regeneration phase is then calculated by
the to1 + to2. Considering that |VT HP| ≈VT HN =VT H and CLo ≈CLX =CL,
to = to1 + to2 =2·CLVT H
IDM1,2. (5.5)
39
The to temperature dependency is obtained by analyzing the two temperature-
dependent parameters VT H and µ . The VT H and µ dependencies described in Eq (4.2)
and (4.3) are used to derive the to temperature dependency as
∂ to
∂T= 2· CL
Ibias
(
αVTH−αIbias
VT H
Ibias
)
, (5.6)
where αIbiasand αVT H
are the temperature coefficients. The value of αIbiascan be found
using,
αIbias=
∂ Ibias
∂T=
12
gm
(
−βµ(VCM −VT H)
T−2·αVTH
)
, (5.7)
in order to prove that to delay increases as temperature increases, it is sufficient to prove
that
αVT H−αIbias
VT H
Ibias
> 0. (5.8)
Considering the average VT H ≈ 400 mV in the XH018 technology and a gm in the order of
magnitude of hundreds of µS and Ibias in the order of magnitude of tens of µA, one may
conclude that the condition in Eq. (5.8) is met.
5.2.3 Double-Tail Delay
The DT-comparator topology analyzed in this study was first proposed by Schinkel
at al. in [8]. DT comparators were introduced because of their improved performance,
specially in kick-back noise. The DT comparator’s behavior can be separated into three
phases: pre-charge, decision, and regeneration. Figure 5.1(b) presents a schematic illus-
tration of the DT topology.
In the pre-charge phase, CLK = 0 switches M3 and M4 to charge the nodes fp and
fn to VDD respectively. It is assumed that these nodes are completely charged by the time
of CLK = 1. These nodes charged to VDD force the transistors MR1 and MR2 to conduct.
Thus, the two output nodes are forced to ground.
In this case, the decision (to) delay can be identified as the time it takes either
the fp or the fn node voltage to discharge from VDD to VT H . As soon as Mtail1 begins to
conduct, M1 and M2 begin to discharge fp and fn respectively. Considering VIN p >VINm,
fp node discharges faster than fn. As soon as fp reaches the voltage value of VT H , MR1 no
longer forces the ground voltage on VOUT p; and the comparator latches in its regenerative
phase. In order to calculate the decision delay time to in this topology, it is considered the
40
variation in the voltage fp and its final voltage VT H as
VDD− ID
CL
to =VT H , (5.9)
where ID ≈ Ibias is the current provided by M1; and CL is the output node capacitance.
Considering the temperature variation of the current Ibias and VT H , the temperature
effects on the delay are due to a decrease of VT H and of Ibias, that implies a decrease on
the discharge rate of the fp node voltage. This combined effect increases even more the
delay in both cases. To clearly demonstrate the delay to, the following relation is found
to =CL (VDD −VT H)
Ibias
. (5.10)
In order to derive a temperature-sensitive behavior, the total to delay is derived
with respect to the temperature as
∂ to
∂T=
CL
Ibias
(
−αVT H−αIbias
(VDD −VT H)
Ibias
)
, (5.11)
where the rise in the to delay in relation to temperature increase is proven by showing that
−αVT H−αIbias
(VDD −VT H)
Ibias
> 0. (5.12)
Considering the same values as previously, the condition in Eq. (5.8) is met and the
delay will always increase with temperature. In the instant that VDS drops low enough, the
transistor changes its operating region to the ohmic region. From this point, the current
will continue to reduce independent of the temperature effects. In other words, it can
be assumed that delay time always increases when the temperature increases. Eq (5.11)
also shows that theoretically the to delay in the DT comparator is much more sensitive to
temperature variations than in SA comparators.
In both the SA and the DT comparators, one can identify the effects on to as the
main agent of the system delay degradation. However, it is possible to show how the
delay of the regeneration phase (tlatch) is also affected by the temperature variations. In
fact both SA and DT comparators have similar tlatch degradation. The time it takes for the
differential signal to regenerate to a stable value is inversely dependent on the the gain of
the back to back inverters as shown by the equation developed in [25]. To evaluate tlatch,
one may express
tlatch =CL
Gmln
(VDD/2
∆Vo
)
, (5.13)
41
where CL represents the capacitance of the output node, Gm the gain of the inverters
and ∆Vo the voltage difference between the output nodes. It can then be deduced that by
increasing the temperature, and thus reducing the gain of the transistors, tlatch is increased.
5.2.4 Comparator Offset
The input-referred offset in latched comparators can be separated into two main
parts, the offset coming from the mismatch of the transistors in the differential pair and
those from the latch [26] in the following way
VOS,i−total =
√
V 2OS−di f f pair +
1G2V 2
OS−latch, (5.14)
where VOS−di f f pair and VOS−latch are the offsets in each stage and G the gain before the
latch. In the case of the SA comparator this gain comes from the differential pair, but for
the DT comparator it is the differential-pair gain multiplied by the gain from MR1 or MR2
transistors. If one considers that the gain G is significant enough to neglect the effects of
the latch offset, a simple differential pair mismatch analysis can be done. The standard
deviation of the offset in a differential pair is given by
σ 2VOS−di f f pair =σ 2∆ID
g2m
[27], (5.15)
where σ 2∆ID is given by,
σ 2∆ID =2
W L
[
g2mA2
V T 0 +
(ID
K
)2
A2K
]
, (5.16)
where K = µCox
(WL
); AV T 0 is a technology-defined variability constant for the VT H and
AK for the K. One can find the offset of the differential pair as
σ 2VOS−di f f pair =2
W L
[
A2V T 0 +
(ID
Kgm
)2
A2K
]
, (5.17)
Assuming the comparators’ layout is compact enough, the temperature variation
equally affects all transistors. In fact, all transistors maintain the same temperature gradi-
ent; and temperature effects behave as a common-mode variation. Since one may assume
that process variation does not vary with temperature, AV T 0 and AK remain constants [25].
Although the the coefficients multiplying A2K are temperature variant, A2
V T 0 will always
dominate. As a result, the offset voltage in both topologies is mostly unaffected by tem-
perature variation in the differential pair. Since the differential pair provides the biggest
42
impact on the offset voltage, it is reasonable to conclude that the offset will present a
negligible dependence on temperature. These matching parameters may be found on Ap-
pendix A.
5.3 Post-Layout Results
Both SA and DT comparators were designed using the XH018 180 nm technol-
ogy. Table 5.1 presents transistor sizing for SA (see Fig 5.1(a)) and DT comparators (see
Fig 5.1(b)). Then, the layout of both comparator topologies is implemented using state
of the art techniques. To efficiently compare both topologies, the layout is carried out
minimizing mismatch, achieving a similar area, and placing I/O in same positions. Figure
5.2(a) shows the SA comparator layout, having an area of 49 x 10 µm2. Figure 5.2(b)
shows the DT comparator layout, having an area of 52 x 10 µm2.
Table 5.1: Transistor Sizing of SA and DT Comparators in (W x L).
SA [7] DT [8]
M1−2 14.4 µm x 720 nm M1−2 14.4 µm x 720 nm
M3−6 7.2 µm x 720 nm M3−4 1.1 µm x 180 nm
M7 1.1 µm x 180 nm MR1,2 3.6 µm x 720 nm
S1−4 1.1 µm x 180 nm M7−10 7.2 µm x 720 nm
Mtail1,2 1.1 µm x 180 nm
To prove the to temperature dependency described in Subsec. 5.2.2 and 5.2.3, a
first experiment is drawn based on a post-layout transient simulation. The simulation
parameters are: 100 MHz clock, a 1ps strobe period, a common mode voltage of 900 mV
and a differential voltage of 10 mV between input nodes. At the clock’s rising edge, the
simulation time is started as 0 ns in the X-axis; and it runs until 1 ns (sufficient time to
observe to for a 10 mV differential input). For the SA comparator, X1 and VOUT m nodes are
inspected (Y-axis). For the DT comparator, fp and VOUT p nodes are inspected (Y-axis).
It is expected that X1 and fp discharge until to according to Eq. (5.5) for SA comparator
and Eq. (5.10) for DT comparator. Figure 5.3 shows SA and DT post-layout simulation
results for temperatures of −40 oC (dashed blue line), 27 oC (continuous black line), and
175 oC (dashed-dotted red line).
43
(a)
(b)
Figure 5.2: Latched comparators’ layout of (a) SA having an area of 49 x 10 µm2 and (b)
DT having 52 x 10 µm2.
Figure 5.3(a) highlights SA operation when decision is being taken. One can
notice that the VOUT m begins to latch around the same instant of time as the node X1
achieves the voltage level VDD − 2·VT H . This voltage level represents that by the time
VOUT m decreases to VDD −VT H , the node X1 discharges two times the value of VT H . This
point indicates the beginning of the latching phase; and it marks to for SA comparator.
Among temperature variation curves, it is remarkable the to increase due a decreasing
in the discharge rate and in the transistor VT H . This validates the analysis presented in
Subsec. 5.2.2 derived in Eq (5.6).
Figure 5.3(b) highlights DT operation while fp is discharging and VOUT p is rising.
The delay to can be identified as the time the fp node voltage reaches around one VT H .
Also, DT comparator latching is delayed as temperature increases due to the decrease
of the discharge rate and the threshold voltage. This validates he analysis presented in
Subsec. 5.2.3 derived in Eq (5.11).
Since latched comparators are linear time-varying circuits, the following experi-
ments are run using a post-layout periodic-steady-state simulation. The test-bench that
inspired the one used for the presented results was previously published in [28] and [29].
Delay, offset, and power consumption are evaluated in a 151-point Monte Carlo simula-
tion for a 11-point temperature variation in a range from −40 oC to 175 oC. The test-bench
proposed in [28] is able to put latched comparator as close as possible of its metastable
operation. In this case it achieves maximum delay for an input differential voltage equal
44
0 0.2 0.4 0.6 0.8 10.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Vo
ltag
e (V
)
Time (ns)
−40 oC
27 oC
175 oC
X1
VOUTm
(a)
0 0.2 0.4 0.6 0.8 10
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Vo
ltag
e (V
)
Time (ns)
−40 oC
27 oC
175 oCf
p
VOUTp
(b)
Figure 5.3: Post-layout transient simulation of (a) X1 and VOUT m for SA; and (b) fp and
VOUT p for DT comparators in a temperature variation of −40 oC (dashed blue line), 27 oC
(continuous black line), and 175 oC (dashed-dotted red line).
to the comparator offset voltage. Power consumption is obtained by the RMS power
consumed for one cycle in a periodic-steady-state regime.
Figure 5.4 presents the statistical results of the comparator delay in both archi-
tectures. The data is represented as a plot of the average delay values with an error bar
representing the standard deviation for each temperature point. Post-layout results are
presented as solid line for the SA delay and dotted line for the DT delay. While temper-
ature increases, a linear increase of the mean delay is noticeable. This behavior was also
predicted in the previous transient simulations and both are in agreement with the theoret-
ical analysis presented in Eq. (5.6) and (5.11) (see Sec. 5.2 for details). From a linear fit,
a delay temperature-coefficient of 6.3 ps/K for the SA comparator and 6.29 ps/K for the
DT comparator is found. In fact, both SA and DT comparators delays vary with the same
temperature coefficient. It can be highlighted though that DT comparator is always slower
due to its larger to for all temperatures. The temperature effect in delay standard deviation
45
is diminished in the DT comparator, this may be due to the much faster regeneration phase
as compared to the SA comparator. Additionally, a worse case delay bigger than 2.5 ns
(a quarter of clock period) is found. Theses results might suggest a comparator failure in
high-temperature operations.
0 50 100 1501.4
1.8
2.2
2.6
3t d
elay
(n
s)
Temperature (oC)
SADT
Figure 5.4: A 151-points Monte Carlo post-layout simulation for a 11-points temperature
variation in a range from −40 oC to 175 oC for SA and DT comparator delay.
The average offset of both comparators is around zero as expected, that is why
Figure 5.5 shows only the standard deviation of the comparators’ input-referred off-
set (σVOS,i−total). The solid line is the SA σVOS,i−total; and the dotted one is the DT
σVOS,i−total. The σVOS,i−total data over temperature does not change significantly. This
behavior validates the theory as predicted in Eq (5.17) in Sec. 5.2. One may concludes
that the SA σVOS,i−total is less sensitive to temperature variation. Even if the SA presents
a higher σVOS,i−total than the DT, due to the additional gain provided by the MR1,2 tran-
sistors, DT σVOS,i−total variation is three times bigger than SA σVOS,i−total variation over
the temperature range.
In high-temperature conditions, thermal noise becomes a major issue for a correct
decision as it is statistically added to the comparator offset. The output-referred noise
is estimated from a periodic noise analysis. Input-referred noise is estimated from the
output-referred noise and the comparator gain. This gain is obtained from a periodic
AC analysis evaluated at the instant the comparator achieves its decision threshold (i.e.
VDD/2) at the output nodes. Details of the test-bench setup are presented in [28] and [29].
Figure 5.6 presents the mean and the standard deviation of SA and DT input-
referred noise obtained from a 151-points Monte Carlo post-layout simulation for a 11-
point temperature variation. The solid line is the SA mean and standard deviation; and
46
0 50 100 1501.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
σ Voff
set (
mV
)
Temperature (oC)
SADT
Figure 5.5: A 151-points Monte Carlo post-layout simulation for a 11-points temperature
variation in a range from −40 oC to 175 oC for SA and DT comparator σVOS,i−total .
the dotted one is the DT mean and standard deviation. Input-referred noise standard de-
viations are marked with squares in Figure 5.6. Since thermal noise is linearly dependent
on temperature, SA and DT input-referred noise increase linearly; but the standard devi-
ation increases slightly faster than the mean. It is noticeable that the DT presents more
noise than the SA; and DT noise increases at a much faster rate. Considering noise as
an additive source of decision errors as offset voltage, it can be remarked that the lower
offset voltage of the DT comparator is payed off by a higher noise. This trade-off is due
to the extra DT transistors increasing gain, reducing offset voltage, but generating more
noise. Indeed, thermal noise may vary input voltage incurring in a bit-flip and a Single
Event Upset (SEU) [3]. At the best of our knowledge, this drawback is first revealed in
this work.
0 50 100 1500.2
0.4
0.6
0.8
1
σ n,i (
mV
)
Temperature (oC)
µSA
σSA
µDT
σDT
Figure 5.6: A 151-points Monte Carlo post-layout simulation for a 11-points temperature
variation in a range from −40 oC to 175 oC for SA (solid line) and DT (dotted line)
comparator input-referred noise mean and standard deviation (square marks).
47
To summarizes the SA and DT performance comparison, Table 6.2 draws perfor-
mance trade-offs under temperature variation. A linear fit of the presented post-layout
simulations for a 11-point temperature variation is done in order to determine a temper-
ature coefficient for each SA and DT comparator characteristic. One may conclude that
the DT comparator achieves a smaller offset in the expense of power consumption and
noise. DT offset and noise has a bigger temperature coefficient than SA. Both SA and DT
comparator’s delays are equally sensitive to temperature variation. At high temperatures,
however, the variation of the comparators’ characteristics may incur in a circuit failure.
However, the DT comparator is found to be less reliable than the SA comparator at these
temperatures.
Table 5.2: Performance Comparison of Comparators in 180nm Technology and 1.8V
Supply Voltage
Performance SA [7] DT[8]
Total Delay/10 oC 63 ps 62.9 ps
σVOS,i−total/10 oC 4.88 µV 13.9 µV
σn,i σ/10 oC 4.1 µV 11.8 µV
σn,i µ/10 oC 3.0 µV 8.0 µV
Average Power Consumption 0.35 mW 1.7 mW
5.4 Conclusions
This chapter has lead one to conclude that at 175 oC, the DT presented a 3.1 ns
worst case delay and 1.4 mV offset, while the SA showed 2.7 ns and 2.7 mV respec-
tively. Moreover, the DT’s input-referred noise achieves worst-case levels of 0.89 mV;
while SA’s noise is below 0.4 mV. Post-layout simulations validated the delay analysis,
which demonstrated a high sensitive to temperature variation incurring in circuit failure at
high temperatures. Offset voltage was found to be less sensitive to temperature, however
it is overcome by input-referred noise. Combining comparators’ offset and noise, input
voltage uncertainty may incur in a bit-flip and thus a Single Event Upset (SEU). All this
points to the DT being less reliable than the SA. Additionally, the proposed analysis fore-
tells failure conditions in harsh environments for the quantizer stage. If the quantization
48
cannot be done in time or the output signal is corrupted by the inherent offset voltage,
the assumptions made in chapter 2 no longer represent the Sigma Delta modulator system
well enough.
49
Chapter 6
Operational Transconductance
Amplifier
6.1 Introduction
This chapter will present a novel approach to OTA design using a gm/ID temperature-
aware methodology. The OTA, as presented on Chapter 2, is the block responsible for the
integrators in the filter. In order to be able to assure the full functionality of the circuit, a
few metrics must withstand temperature variations. These metrics include speed, gain and
rejections rates. As seen on Chapter 4 the transistors’ parameters did not always present
a global minimum that could be satisfying when designing these amplifiers. As will be
seen, a few compromises will need to be made.
6.2 Understanding the OTA Topology
An operational transconductance amplifier, is an amplifier that converts a differen-
tial voltage input into a current output. Ideally it is possible to say that the current output
(Iout) is linearly dependent on the voltage input (Vin) by a transconductance gain:
Iout = gmVin, (6.1)
where gm is the transconductance gain.
Such operational amplifiers present high input and output impedances. This high
output impedance is useful for driving capacitive loads. Figure 6.1 is the ideal OTA
50
representation.
Figure 6.1: OTA Topology Operation.
Two metrics, that will be used momentarily, must be defined for the OTA: the
Slew-Rate (SR) and the unit-gain frequency ( ft ). The slew-rate is defined as the maximum-
rate at which the output voltage of an amplifier can change [27]. In other words,
SR =
∣∣∣∣
dVo
dt|max
∣∣∣∣. (6.2)
In other words that maximum current it can provide for a given load. The SR value
for an OTA with a capacitive load is given by,
SR =IOUT
CL
, (6.3)
The ft of an amplifier is defined as the frequency at which it has 0dB of gain [27],
hence unity-gain frequency. In an OTA that can be considered a firs-order single pole
circuit, with the pole given by the load being dominant, the value of ft is given by,
ft =gm
CL, (6.4)
The OTA used in the study is the one illustrated in Figure 6.2. A brief idea of this
OTA’s operation can be seen in Figure 6.3.
In the positive input, the VIN p becomes a common-mode current (gm2VIN p) plus a
∆, this current is mirrored to the M6 transistor The same happens on the negative input
with a common-mode minus a ∆ being mirrored to M5. The current through M5 is then
mirrored to M8 through M7. Kirchoff’s current Law then makes it so that the output
current is the current ar M6 minus the current at M8 giving 2∆. Where,
∆ = gmvd
2, (6.5)
where gm is the differential pair’s transconductance and vd is the input differential voltage.
51
M3 M6
VINn
M9
VDD
M4
VIN p
M5
M7 M8
M1 M2
Vbias
IOUT
CL
Figure 6.2: OTA Topology
Figure 6.3: OTA block representation.
6.3 Temperature-Aware OTA Design
6.3.1 Temperature-Aware OTA design
The procedure for designing of a classic OTA is proposed using this new gm/ID
temperature-aware design methodology (presented in chapter 4). The sensitivity analysis
presented on Chapter 4 drive the OTA design considerations.
One can fully design the OTA by the gain bandwidth (GBW) required, the chosen
gm/ID and the capacitive load CL. This gm/ID ratio is chosen in order to optimize a given
metric. The GBW being the product of the amplifier’s bandwidth by the gain at which
the bandwidth is measured. Due to the large capacitive load the OTA can be considered a
52
first-order circuit and the gain bandwidth can be approximated by the ft ;
GBW =gm
CL= gm/ID · JDS ·W
CL, (6.6)
where CL, gm and ID are the load capacitance and the differential pair’s (transistor M1 and
M2) transconductance and drain current respectively. This means that the temperature
sensitivity of the GBW can be defined as,
SGBWT = S
gm/ID
T +SJDS
T , (6.7)
where Sgm/ID
T and SJDS
T are the temperature sensitivity of the differential pair’s (transistor
M1 and M2) gm/ID ratio, and JDS respectively presented in Figures 4.3(b) and 4.3(a).
The OTA’s SR is given by
SR =IOUT
CL
, where IOUT = 2K · ID, (6.8)
is the output current injected on the load and K is the gain ratio of the current mirror. The
SR’s temperature sensitivity can be directly given by the tail transistor (M9) and current
mirrors’ current temperature sensitivity,
SSRT = S
(JDS·W )/CL
T = SJDS
T , (6.9)
where CL and W are temperature invariant. Equations (6.6) and (6.8) lead to the following
property:
GBW = gm/ID · IOUT
2KCL= gm/ID · SR
2K. (6.10)
Equation (6.10) means that when setting the gm/ID ratio and the drain current, the slew-
rate is fixed. This brings about another advantage of this OTA topology, where the K ratio
adds a degree of freedom. The output current can be changed by setting K ratio and the
SR can be increased. The K ratio is then limited by the mismatch in the current mirrors
due to a large size difference, and the power consumption.
The ZTC point in terms of JDS, as seen in Figure 4.3(a), is useful for biasing
current mirrors or any other circuit block that present a need for an invariant current.
The problem arises when biasing a block that calls for a temperature invariant gain (i.e.
differential pair). If the current of the differential pair is fixed, as would be the case if
M1, M2 and M9 were biased in the JDS ZTC region, the GBW sensitivity to temperature
becomes
SGBWT = S
gm/ID
T , (6.11)
53
in other words, the GBW would vary according to the variation of the gm/ID ratio; and,
from Figure 4.3(b), Sgm/ID
T does not have a temperature coefficient minimum, in other
words the temperature effects cannot be easily compensated.
This means that although the current is fixed, the gain of the differential pair is
not. In fact, a different region is needed where the current can change with temperature
but its variation is compensated by the inverse variation of the gain in a way that
Sgm/ID
T =−SJDS
T . (6.12)
This point can be identified if the differential pair’s bias current can vary with
temperature and is not fixed by an invariant current source or JDS ZTC current mirror.
Figure 6.4 shows the sensitivity of GBW to T using an unfixed current bias. A minimum
is found according to Eq. (6.7) for JDS from 10 to 30 µA/µm (gm/ID ≈ 6).
1n 10n 0.1u 1u 10u 0.1m 1mJDS
(A/ m)
-20
-10
0
10
20
STG
BW
(dB
)
nelpel
Figure 6.4: GBW sensitivity analysis with unfixed current in the differential pair M1,2 and
M9 transistors at temperature range from -55 to 175 oC (T0 = 27 oC).
As can be seen, in a bias JDS of 21µA for nel or 13µA for pel, gm/ID coefficients
of 11 and 10 respectively, the GBW presents a global minimum and is insensitive to
temperature variations. From this point, this will be noted as the gain bandwidth ZTC
region. In Figure 6.4 it can be noted that although the current varies significantly with
temperature at this bias point, the gain bandwidth is kept constant.
This point can also be found using Lambert’s W equation. A simulation of the
GBW sensitivity with respect to temperature yielded Figure 6.5. One can see the point of
54
insensitivity for the nel device. The minimum is found to be at JDS = 12.4µA/µm and a
gm/ID of 11.75V−1.
1n 10n 0.1u 1u 10 0.1m 1m
JDS
@ 27oC (A µm)
-40
-30
-20
-10
0
10
20
30
STG
BW
(dB
)
Figure 6.5: SGBWT for a W = 1 µm and L = 180 nm nel transistor simulated using the
Lambert’s W function and the EKV model.
Another important metric, the OTA’s DC gain (AvDC) is given by
AvDC =K ·gm
gDS6 +gDS8, (6.13)
where gm, gds6, and gds8, are the differential pair’s transconductance and output conduc-
tances of M6 and M8, respectively. This will provide a temperature sensitivity of
SAvDC
T = Sgm/gDS
T , (6.14)
where Sgm/gDS
T is the temperature sensitivity of the transistor’s self-gain as seen in Figure
4.4(a), one may consider that the sensitivity of the intrinsic gain of a transistor is equal
to that of the transconductance of the differential pair divided by the sum of the output
transistors’ conductances. This sensitivity does not present a minimum and cannot be
optimized using the ZTC methodology.
6.3.2 Temperature-Aware OTA design examples
The increasing demand for low-power applications has led to many solutions mak-
ing low-power (named LP) OTA a favorite in innovative designs [30] and temperature
awareness [31]. However, high-speed applications have led some solutions in another di-
rection where speed ZTC design in terms of GBW (named GBW ZTC) and SR (named
SR ZTC) are good candidates to accomplish temperature awareness.
55
In total, three designs examples are made comprising of:
1. LP design, using a gm/ID ratio of 18 to achieve weak inversion operation and biased
with a Vbias coming from a bandgap circuit.
2. SR ZTC design, using a gm/ID ratio of 6 (a minimum in Figure 4.3(a)) to achieve
ZTC condition expressed in Eq (6.9), biased with a PTAT Vbias in order to keep
current bias fixed [9].
3. GBW ZTC design using a gm/ID ratio of 11 (a minimum in Figure 6.4) for the
differential pair (M1 and M2), and a gm/ID ratio of 6 for the current mirrors (M3 −M8). For M9 transistor bias, current should be allowed to vary at the same rate as
the differential pair (ie. having a gm/ID ratio of 11), although its width will be twice
as big as M1,2. The Vbias voltage comes from a bandgap circuit.
To complete the OTA design specification, a gain greater than 40 dB, a GBW of
60 MHz and a capacitive load (CL) of 1 pF are chosen; the value of K is set to 1 for power
consumption minimization. These specifications are sufficient to set the design of the
OTA for LP, SR ZTC, and GBW ZTC. To minimize short-channel effects transistor length
is set to L = 4 ·Lmin (i.e. L = 720 nm). Table 6.1 shows the final sizing for transistor width
in µm.
Table 6.1: Transistor sizing: width in µm having L = 0.72 µm.
Sizing LP SR ZTC GBW ZTC
gm/ID (V−1 ) 18 6 11
M1,2 (µm) 21 4.2 7.2
M9 (µm) 56 8.4 14.4
M3,4,5,6 (µm) 80 12.72 21
M7,8 (µm) 24 4.8 8
6.4 Simulation Results
The LP, the SR ZTC, and the GBW ZTC OTA proposals are designed using XH018
technology according to Sec 6.3 considerations. To clarify speed ZTC design improve-
56
ments compared to LP design, three simulation test benches are considered. In this Sec-
tion, a trade-off between SR ZTC and GBW ZTC designs is highlighted. Both designs are
constrained by the gm/ID ratio choice presented in Table 6.1.
Figure 6.6(a) illustrates the GBW and Figure 6.6(b) illustrates the DC Gain of the
OTA designs as it varies with temperature. These results were obtained using Virtuoso
Spectre AC stability analysis, via the open loop frequency response of the OTA for tem-
perature variation from −55oC to 175oC. As predicted by the sensitivity analysis of the
GBW with temperature (see Fig. 6.4), the GBW ZTC design presents the least variation
among the three as it is biased in the point of minimum sensitivity. Whereas, the LP de-
sign presents the greater variation. As for the DC Gain, the LP bias point is located in the
vicinity of the minimum in Fig. 6.4 and presents the least variation.
Figure 6.7(a) represents the SR and Figure 6.7(b) represents the RMS power con-
sumption of the different designs as it varies with temperature. These results were found
using a Virtuoso Spectre transient analysis where an input source’s frequency was varied
until achieving the maximum charging slope (i.e. SR) of the OTA. As predicted by the
sensitivity analysis of the SR (see Eq (6.9) and Fig. 4.3(a)), the SR ZTC design presents
the least variation among them as it is biased in the point of minimum JDS sensitivity.
Since power consumption only depends on the current of each branch in the circuit, it
makes sense that the SR ZTC would also present the least variation.
Figure 6.8(a) represents the common-mode rejection rate (CMRR) and Figure
6.8(b) represents the power-supply rejection rate (PSRR) of the different designs as it
varies with temperature. These results were found using a Virtuoso Spectre XF analysis
where the frequency response was found for a common-mode input and a power-supply
variation. The CMRR variation is approximately the same for all designs, with LP pre-
senting the greater overall rejection ratio in dB. The SR ZTC design presents a very low
rejection ratio, which might represent a failure condition in some applications. As for
the DC Gain, the LP is a better candidate for least variation and greatest rejection ratio,
whereas the other two ZTC designs vary equally.
Table 6.2 summarizes the ppm/oC variation of these performance. From these
results, it can be noted that although the LP design presents better performance in AvDC,
but this improvement are not significant compared to ZTC proposals. The noticeable
variations of the LP for PRMS, GBW and SR, disqualify it down for harsh environment
57
applications. The GBW ZTC topology proved to be a better choice over the SR ZTC design
when considering the least variation for most metrics. These are not, however, enough to
make it the obvious choice for a temperature-aware system. From Equation (6.10), one
can note that the relation between GBW and SR is limited by the gm/ID ratio, so the
system design should take into account which metric (GBW or SR) is more important for
the specific application.
Table 6.2: Temperature Coefficient calculated from -55 oC to 175 oC.
Per f ormance LP GBW ZTC SR ZTC
PRMS (ppm/oC) 121.2 32.3 −3.9
GBW (ppm/oC) −52.9 −5.9 −28.4
SR (ppm/oC) 136.8 30.4 −16.1
AvDC (ppm/oC) −1.9 −4.3 −2.8
CMRR (ppm/oC) −10.0 −13.6 −9.0
PSRR (ppm/oC) −2.2 −4.1 −2.9
6.5 Conclusions
A temperature-aware design methodology was studied in this chapter for the de-
sign of an OTA; this methodology can, however, be extended to any circuit that have
parameters that can be expressed as a function of gm/ID. This temperature-aware solution
was introduced using the sensitivity analysis previously derived.
The methodology allowed for the conception of three OTA designs, a low-power
design and speed ZTC designs. The low-power OTA design achieved better performance
in terms of gain over temperature, but this improvement is not significant compared to the
speed ZTC proposals. The OTA performance comparison has demonstrated a trade-off
between GBW and SR, which is limited by the gm/ID ratio. Since sensitivity of gm/ID
to temperature does not achieve a minimum, both speed ZTC designs presents their own
advantages and drawbacks.
In can then be concluded that the optimum temperature-invariant design depends
on the system specifications. It is impossible to gain in every aspect so, as always, a
compromise must be made. Since the complete Sigma-Delta systems depends on all of the
58
OTA’s metrics being temperature-invariant, it is impossible to achieve a fully temperature
independent design using this solution. It possible, however, to reduce significantly the
effects of temperature for a given metric.
59
-50 0 50 100 150
Temperature (oC)
10
20
30
40
50
60
70
GB
W (
MH
z)
LPSR ZTCGBW ZTC
(a)
-50 0 50 100 150
Temperature (oC)
35
40
45
Gai
n (
dB
)
LPSR ZTCGBW ZTC
(b)
Figure 6.6: Electrical Simulation of LP (circle-marked continuous line), SR ZTC
(diamond-marked dashed line), and GBW ZTC (square-marked dotted line) designs for
temperature variation from −55oC to 175oC: (a) gain bandwidth in MHz, (b) gain in dB.
60
-50 0 50 100 150
Temperature (oC)
0
20
40
60
80
100
120
SR
(V
/s)
LPSR ZTCGBW ZTC
(a)
-50 0 50 100 150
Temperature (oC)
0
100
200
300
400
500
PR
MS (
W)
LPSR ZTCGBW ZTC
(b)
Figure 6.7: Electrical Simulation of LP (circle-marked continuous line), SR ZTC
(diamond-marked dashed line), and GBW ZTC (square-marked dotted line) designs for
temperature variation from −55oC to 175oC: (a) slew-rate in V/µs, (b) power consump-
tion in µW.
61
-50 0 50 100 150
Temperature (oC)
40
60
80
100
120
CM
RR
(dB
)
LPSR ZTCGBW ZTC
(a)
-50 0 50 100 150
Temperature (oC)
70
75
80
85
90
PS
RR
(dB
)
LPSR ZTCGBW ZTC
(b)
Figure 6.8: Electrical Simulation of LP (circle-marked continuous line), SR ZTC
(diamond-marked dashed line), and GBW ZTC (square-marked dotted line) designs for
temperature variation from −55oC to 175oC: (a) common-mode rejection ratio in dB, and
(b) power-supply rejection ratio in dB.
62
Chapter 7
Conclusion
In conclusion, this work aimed at presenting a temperature-aware methodology in
analog circuit design for Smart Vehicle applications. As a focus system, this study chose
the Sigma Delta ADC converter present in these applications. The harsh environments
where the smart vehicles must operate encompass a temperature range from −40oC to
175oC. Reliability and robustness in the device operation must be ensured for these en-
vironments, so it is of paramount importance to be able to adapt to these temperature
variations.
More specifically, two blocks of the Sigma Delta converter were analysed: the
integrator and the quantizer. The integrator is often implemented with switched-capacitor
circuits that require OTAs, and the quantizer is usually implemented with clocked com-
parators. The objective was then to propose a temperature-aware analysis of perfor-
mance variability in state-of-the-art latched SA and DT comparators, and in classic OTA
topologies. They were all designed using the XH018 technology from the XFAB Silicon
Foundries. The XH018 technology is ideal for a temperature range of up to the needed
175 oC.
Thus, a temperature-aware analysis of performance variability in state-of-the-art
latched SA and DT comparators was proposed. At 175 oC, the DT presented a 3.1 ns
worst case delay and 1.4 mV offset, while the SA showed 2.7 ns and 2.7 mV respectively.
Moreover the DT input-referred noise achieved a worst-case level of 0.89 mV; while the
SA noise was below 0.4 mV. Post-layout simulations validated the delay analysis, which
showed a high sensitive to temperature variation incurring in circuit failure at temperatures
above 100oC. Offset voltage was found to be less sensitive to temperature, however it is
63
overcome by input-referred noise. Combining comparator offset and noise, input voltage
uncertainty may incur in a bit-flip, and thus in a Single Event Upset (SEU). This work
has found that the DT is less reliable than the SA. Additionally, the proposed analysis
foretells failure conditions in harsh environments.
Afterwards, a temperature-aware design methodology was studied in order to in-
tegrate high performance electronics for harsh environment for Smart Vehicle industry.
A new temperature-aware design methodology using gm
IDwas introduced using sensitiv-
ity analysis. Using the proposed methodology, three class-A OTA designs were imple-
mented for low-power consumption and speed ZTC. Low-power OTA design achieved
better performance in terms of gain over temperature, but this improvement is not signifi-
cant compared to speed ZTC proposals. OTA performance comparison has demonstrated
a trade-off between GBW and SR, which is limited by the gm
IDratio. Since sensitivity of gm
ID
to temperature does not achieve a minimum, both speed ZTC designs present their own
advantages and drawbacks.
The next step in this study is then to implement the full Sigma-Delta ADC system
using the knowledge acquired in this study. An integrator with a temperature-invariant
OTA is already a possibility, and the considerations found for the comparator can yield
a more reliable design decision. This work also leaves a few questions open, such as a
possible temperature-invariant comparator design or a more complex OTA circuit that is
better applicable to real situations. To the best of our knowledge, an in-depth study of
these questions has not yet been done. Attempts to formalize a design methodology for
such application have been made. This work, however, allows for the designer to easily
integrate gm
IDdesign methodologies to this novel temperature-aware research.
64
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Appendix A
Appendix A
This Appendix presents the extracted nel and pel paramters used in model deriva-
tions. These device parameters are valid only for the XH018 180nm technology, new
parameters must be esxtracted for other technologies.
Table A.1: Nel parameters in 180nm Technology for W = 1µm and L = 1µm
Parameters Saturation Triode
Vto 0.39 V 0.48 V
kpo 293.4 µA/V 2 293.4 µA/V 2
φTo 0.58 V 0.58 V
n 1.23 1.23
Table A.2: Nel parameters in 180nm Technology for W = 1µm and L = 0.18µm
Parameters Saturation Triode
Vto 0.30 V 0.47 V
kpo 360.5 µA/V 2 360.5 µA/V 2
φTo 0.4 V 0.4 V
n 1.24 1.24
69
Table A.3: Nel mismatch and temperature parameters in 180nm Technology
Parametersσ2
kp
kp2 21 ·10−18 /WL
σ2Vt
Vt2 42 ·10−18 /WL
Cox 9.1 ·10−3F/m2
αVT H−0.74 ·10−3
βµ −1.72
Table A.4: Pel parameters in 180nm Technology for W = 1µm and L = 1µm
Parameters Saturation Triode
Vto −0.38 V −0.47 V
kpo 74.4 µA/V 2 74.4 µA/V 2
n 1.21 1.21
Table A.5: Pel parameters in 180nm Technology for W = 1µm and L = 0.18µm
Parameters Saturation Triode
Vto −0.34 V −0.46 V
kpo 124.1 µA/V 2 124.1 µA/V 2
n 1.17 1.17
Table A.6: Pel mismatch and temperature parameters in 180nm Technology
Parametersσ2
kp
kp2 21 ·10−18 /WL
σ2Vt
Vt2 42 ·10−18 /WL
Cox 9.1 ·10−3F/m2
αVT H−0.88 ·10−3
βµ −1.2
70
