TELL-1 and TDC board: present status and future plans

B. Angelucci, A. Burato, S. Venditti

OUTLINE

• Improvements on hardware and firmware wrt previous reports• Experimental setup used to perform tests• Analysis of collected data• Troubleshooting• Where we stand and todo list

NEW HARDWARE: TDCB

TDCB: V4 version delivered in Nov 2010:• New connectors, allowing the use of new cables (standard SCSI). • Power supply plug moved by mistake by about 2mm wrt the original projects, incompatible with TELL1/TEL62TDCB V5 in production,first 2 expected in 2 weeks

LVDS probeCables

Patch panel

SCSI connector

s

PG

RAM

PLL (clock 40Mhz)

Transfer FIFOI2C

TDC control JTAG master

Switch

Time Stamp

FIRMWARE: TDCB

QUARTUS II V.10.1

FIRMWARE: TDCB• TDCB can be programmed through a USB blaster either directly (Active serial interface, .pof file) or indirectly (JTAG interface, .sof and .jic files)• The TDCB clock can be taken directly from FPGA’s PLL or refined using the TDCB internal QPLL• RAM blocks available (2 MB/TDCB), firmware allows to write on them but readout only through I2C by now

JTAG chain

DATA FORMATTDC data are in the form of 32 bit words

01010100010111010101100100010101

event time (1 bit=98ps,TDC rollover

=219=51,38µs)

19 bit

5 bit

TDC channel (32) leading 0x4trailing 0x5

4 bit

4 bit

TDC number & board (4x4)

Lead/trail

#words in a TDC trigger

TDC TS

Periodic triggers (12.8 µs normally used) are sent to the TDCB in order to read its data. A search window and a match window must be properly set to collect the TDC words in the right time windows

TRIGGER MATCHING MODE

THE GOAL

• Setting up an automated TDCB test system in view of a massive TDCB production• Use ad hoc patterns to test some crytical characteristics of the TDCBs: resolution, sustainability of high rates, possible faulty paths on PCBs

The present tests were performed on only 8 channels and on the only two available V4 boards, but up to 32 channels can be presently pulsed.The final test system will be able to pulse 128/512 channels (1 TDCB/1 TELL62) at the same time, using predetermined patterns

EXPERIMENTAL SETUP

The tests we performed on the TELL1 and TDCBs require the following items:• A pattern generator with an input and output to trigger logic conditions in the pattern• A LTUvi module to distribute the trigger sequence (given by the PG) to the TELL1 via the TTCex module• Probe(s) to produce LVDS signals (1 used in these tests+1 just bought, 16+16 LVDS signals)• NIM modules to convert different logic signals (NIM, ECL,TTL) produced by the various parts (PG, LTU) • At least 1 PCs to be used both as a server and to store and analyze data (in our setup we use 2 different PCs for the two tasks)

…and obviously a TELL1 with at least 1 TDCB!

• 8 channels pulsed with 20ns long pulses (min 10 ns)• PATTERN: a) single channels pulsed, 12.8µs pause between pulses b) all channels pulsed at the same time c) single channels pulsed, 10 ns between pulses (same TDCB

TS)• use of input/output PG channels to reset the TDCB TS at

the beginning of each pattern

Part of the pattern used (shifted signals)

Optical trigger to TELL1

Trigin/out from/to PG to LTU module

Signal conversions

Data to PC through GBE

LTU-PG-TELL1-PC COMMUNICATION

• The PG sends an output signal and waits for an input• The output triggers the LTUvi module, which sends a reset signal to the TELL1 (causing TDC TS to reset) and a signal back to the PG input• After the input the PG sends 2 more signals to the LTU through the output, which are sent as 2 triggers to the TELL1. the 2 triggers are delayed to collect the whole pattern. •The pattern is then cyclically repeated till the acquisition is stopped. ~ 0.2M pattern/min collected• Data are accumulated in the PP FIFOs and sent to the acquisition PC through a GBE connection when the TELL1 receives the LTUvi trigger (old TELL1 firmware)

LTU-PG-TELL1-PC COMMUNICATION

DATA ANALYSIS

The output from the TELL1 was sent through a GBE connection to the acquisition PC. Here data are turned into ROOT format in order to be easily analyzed.

single signals (8 channels)

12,8 µs

All channels (shifted)All channels

Pulsed channels: 4-7,

12-15

TS time

CHANNELS 4,5,6,7,12,13,14,15

Leadings and trailings in part b (channels pulsed at the same time) and c (10 ns between pulses) of the

pattern

TRAILING-LEADING TIME CHANNELS 4,5,6,7,12,13,14,15

Pulses from all channels (fired at the same time at PG level)

Offsets will be used to eliminate channel-to-channel shifts

PROBLEMS DETECTED

HOLES: one TDC shows “holes” in the time distribution

TDC word time bins

absolute time (referred to first pulse)

GUESS: bit 0 and 1 paths are in contact, so that the output of bits 0 and 1 is an OR of their real signals

If so the truth table should be:

Bit 0 Bit 1 Bit 0&1

0 0 00

0 1 11

1 0 11

1 1 11

2 empty bins every 4, 1/3 ratio between the

other 2 and that’s it!

TDC word time bins (detail)

NOISY CHANNELSA long time problem on noisy channels (see Marco’s last meeting presentation) was understood, the cause being that the channels not pulsed were not properly terminated. This caused a noise almost in time with the signal, which looked like cross talk.A new patch panel (input PG, output TDCB cable), already available, will solve this problem.

Pulsed channels: 4-7, 12-15

16 unterminated

channels 16 pulsed channels

Conclusions• A (very) preliminary procedure to test TDC boards has been set up• No data loss detected at the level of the collected statistics (~107 events)• Resolution compatible with 100ps (~1 TDC bit), PG effect still to be understood (probably sizeable)• Some problems have been detected, some of them were solved, many more will come…

Todo list• Produce a TDCB test program analyzing data and comparing them with the PG pattern • High rate tests• Offset adjustment of TDC channels• Try to change trigger windows• Firmware development