Technology Inflection Points: Planar to FinFET to Nanowire · Victor Moroz April 4, 2016 ISPD Invited talk Technology Inflection Points: Planar to FinFET to Nanowire

Victor Moroz

April 4, 2016

ISPD Invited talk

Technology Inflection Points:

Planar to FinFET to Nanowire

© 2016 Synopsys, Inc. 2

Outline

ISPD 2016, Santa Rosa, California


Outline



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Why Scaling?

When What scales? When does it end?

1965 Moore’s Law (Fairchild):

Double transistor density every couple of years

• By 2043, there will be 1 atom per transistor

• But you can go up (3D IC)

• Great for planning and aligning the industry

1999

Claasen’s Law (Philips CEO):

Usefulness = log(Technology), or:

Technology = exp(Usefulness)

Forever?

2010

Koomey’s Law (Stanford Professor):

"at a fixed computing load, the amount of battery you need will fall by a factor of two every year and a half.“

• By the second law of thermodynamics and Landauer's principle, irreversible computing cannot continue to be made more energy efficient forever. As of 2011, computers have a computing efficiency of about 0.00001%. The Landauer bound will be reached in 2048. Thus, after 2048, the law could no longer hold.

• With reversible computing, however, Landauer's principle is not applicable. With reversible computing, though, computational efficiency is still bounded by the Margolus–Levitin theorem. By the theorem, Koomey's law has the potential to be valid for about 125 years.


https://en.wikipedia.org/wiki/Logarithm

https://en.wikipedia.org/wiki/Exponential_function

https://en.wikipedia.org/wiki/Second_law_of_thermodynamics

https://en.wikipedia.org/wiki/Landauer's_principle



https://en.wikipedia.org/wiki/Reversible_computing

https://en.wikipedia.org/wiki/Margolus%E2%80%93Levitin_theorem






Terminology of Scaling

• Logic chip is based on standard cell library (lego-like)

• Standard cells are defined by:

–Gate pitch (GP), a.k.a. CPP (Contacted Poly Pitch)

–Metal pitch (MP)

–Cell height, say 12 MP’s or 9 MP’s or 6 MP’s

–Fin pitch (FP)


PMOS

NMOS

GND

PWR FP

GP

MP

Cell width

Cel

l heig

ht

• GP*FP = Transistor area

• GP*MP determine cell area

• 12-track high cells are easy to route

• 6-track high cells are difficult to route

fin gate


Scaling: Fuzzy “technology node”, Crisp “gate pitch”

• Technology node definition varies from one company to another

• However, gate pitch definition is precise and meaningful for standard library cell area scaling

• Here, 2*HK comes from HK-last/gate-last process and will have to be altered


14nm 10nm 7nm 5nm 3nm 2nm 1nm

Technology node

0

10

20

30

40

50

60

70

70 60 50 40 30 20 10

Com

pone

nts

of g

ate

pitch

, nm

Gate pitch, nm

S/D contact

2*HK

2*Spacers

L


Scaling: Fuzzy “technology node”, Crisp “gate pitch”


0

10

20

30

40

50

60

70

70 60 50 40 30 20 10

Com

pone

nts

of g

ate

pitch

, nm

Gate pitch, nm

S/D contact

2*HK

2*Spacers

L

14nm 10nm 7nm 5nm 3nm 2nm 1nm

Technology node

0

1

2

3

4

5

6

14 10 7 5 3 2 1

1/s

pace

r, n

ormalize

d

Technology node, nm

Middle-Of-Line

Capacitance


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Outline



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Planar vs FinFET vs Nano-Wire Transistors


• It is possible to scale any of these transistors, and even the planar MOSFET

• However, the performance of FDSOI scaled beyond 14nm degrades quickly

• FinFET scales gracefully down to 7nm node

• Gate-All-Around nanowire can take over at 5nm node

• This is driven by gate control (i.e. electrostatics) considerations

Source: J.-P. Colinge (TSMC), SISPAD 2014

FDSOI

FinFET

NW

Gate HK Si Oxide


FinFETs Will Last as Long as They Can

• L and W are scaled in sync to prevent short-channel effects (i.e. off-state leakage)

• Simultaneously, fins are getting taller to get more current per layout area


S D

S D

G

G

L/W ratio ~2.5

Source

Drain

STI

Si


Fin Shape Evolution

22nm 14/16nm 10nm 7nm

Channel length 25 22 19 16

Fin width 10 9 8 7

Fin height 34 42 ~50 50+

Aspect ratio 3 : 1 5 : 1 6 : 1 7 : 1


STI

Planar

L/W ratio ~2.5


Fin Shape Evolution

22nm 14/16nm 10nm 7nm

Channel length 25 22 19 16

Fin width 10 9 8 7

Fin height 34 42 ~50 50+

Aspect ratio 3 : 1 5 : 1 6 : 1 7 : 1


STI

Planar

L/W ratio ~2.5


Fin Bending and Eventual Collapse

• Increasing aspect ratio (fin height to fin width) will eventually make the fins too fragile to be manufacturable



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Transistor Load: Middle Of Line Crisis


0

1

2

3

4

5

6

14 10 7 5 3 2 1

1/s

pace

r, n

ormalize

d

Technology node, nm

Middle-Of-Line Capacitance

• At every switching event, transistor has to charge load capacitance

• Load capacitance: Cload = CMOL + CBEOL

• Switching delay: t ~ C

• Power consumption: P ~ C


Middle Of Line Crisis


0

1

2

3

4

5

6

14 10 7 5 3 2 1

1/s

pace

r, n

ormalize

d

Technology node, nm


C ~ 1/x

C

x






Middle Of Line Life Crisis


0

1

2

3

4

5

6

14 10 7 5 3 2 1

1/s

pace

r, n

ormalize

d

Technology node, nm






• Switching from FinFETs to NWs can delay the crisis


Outline



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To III-V or not to III-V?

• There’s a big effort in the industry on alternative channel materials with high bulk mobility, like InGaAs and InSb

• High bulk mobility is due to low effective mass

• We perform analysis of a wide range of material properties for 5nm design rules and beyond

• Analysis is based on Quantum Transport NEGF (Non-Equilibrium Green’s Functions), accounting for electron tunneling through the barriers


32 22 16 11 8 6 4

Op

po

rtu

nit

y

Technology node, nm

III-V process

is not ready

III-V becomes

worse than Si

SiGe,

Ge

III-V

Opportunity Window for Non-Si Channel

Source: V. Moroz at ECS 2010


Band Structure of Fins and Nano-Wires


Atomistic structure of a nano-wire cross-section


Band Structure of Fins and Nano-Wires


0.1

1

0 1 2 3 4 5 6

Elect

ron

eff

ect

ive m

ass

NW diameter, nm

ml

mt

Atomistic structure of a nano-wire cross-section

Band-structure properties of NW


Exploring Wide Range of Effective Masses


• Stress engineering is currently used to reduce effective mass

Ioff = 1nA/μm

200

300

400

500

600

700

800

0 0.1 0.2 0.3 0.4 0.5 0.6

Ion

(μ

A/μ

m)

Effective mass

5nm node




Ioff = 1nA/μm

200

300

400

500

600

700

800

0 0.1 0.2 0.3 0.4 0.5 0.6

Ion

(μ

A/μ

m)

Effective mass

5nm node

Direct S/D

tunneling • Stress engineering is currently used to reduce effective mass

• When pushed too far, it leads to direct S/D tunneling

• And that’s a very steep cliff




Ioff = 1nA/μm

200

300

400

500

600

700

800

0 0.1 0.2 0.3 0.4 0.5 0.6

Ion

(μ

A/μ

m)

Effective mass

5nm node

4nm node

3nm node

2nm node




• Optimal effective mass increases when scaling NW

• The peak width broadens, favoring heavier mass







• Optimal effective mass increases when scaling NW

• The peak width broadens, favoring heavier mass

• III-V falls off the cliff, but Si is in the sweet spot Ioff = 1nA/μm

200

300

400

500

600

700

800

0 0.1 0.2 0.3 0.4 0.5 0.6

Ion

(μ

A/μ

m)

Effective mass

5nm node

4nm node

3nm node

2nm node

InGaAs Silicon

Stress to

speed up

Stress to

slow down


Photons are Too Big!

• The blu-ray photon diameter is ~400 nm, which limits the density of data on DVD

• Shorter wavelength would be X-Ray…



Photons are Too Big! What about Electrons?


Particle wave-function is inversely proportional to it’s effective mass: l ~ h/meff

Electron in Si Electron in InGaAs

Stress-free

With stress engineering

Electrons are moving around

l


Electrons Spilling Out of Transistor


Source extension

Source barrier

Channel

Drain extension

HK

Si electrons easily fit into NW with design rules down to 2nm

But III-V electrons spill out of source through the HK

and also through the source barrier beyond 7nm node




Source extension

Source barrier

Channel

Drain extension

HK





Source extension

Source barrier

Channel

Drain extension

HK






32 22 16 11 8 6 4

Op

po

rtu

nit

y

Technology node, nm

III-V process

is not ready

III-V becomes

worse than Si

SiGe,

Ge

III-V

Opportunity Window for Non-Si Channel

Source: V. Moroz at ECS 2010


Outline



Sca

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nsisto

r st

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Existing Early Design Rule Evaluation


GDS: Maxwell

or Laker

DR DR

1

DR

2

Fin

pitch

24

nm

22

nm

MG

ext.

15

nm

15

nm

Spac

er

7

nm

6

nm

Litho:

Sentaurus

Design rule

bad

bad

good


Existing Early Design Rule Evaluation


GDS: Maxwell

or Laker

DR DR

1

DR

2

Fin

pitch

24

nm

22

nm

MG

ext.

15

nm

15

nm

Spac

er

7

nm

6

nm

Litho:

Sentaurus

Design rule

bad

bad

good

• Missing process proximity effects outside of litho

• Missing process interaction with design

• Gives design window, but no guidance within the window


Proposed DTCO: Pre-Si PowerPerformanceArea Evaluation


GDS: Maxwell

or Laker

Process T Time Etch

Process1 480 C 25 min 12 nm


DR DR

1

DR

2

Fin

pitch

24

nm

22

nm

MG

ext.

15

nm

15

nm

Spac

er

7

nm

6

nm

Litho:

Sentaurus

3D structure:

Process

Explorer

Switching

behavior:

TCAD

Design rule

bad

bad

good

Design rule P

rocess c

onditio

n

Design rule

Pro

cess c

onditio

n




GDS: Maxwell

or Laker

Process T Time Etch



DR DR

1

DR

2

Fin

pitch

24

nm

22

nm

MG

ext.

15

nm

15

nm

Spac

er

7

nm

6

nm

Litho:

Sentaurus

3D structure:

Process

Explorer

Switching

behavior:

TCAD

Design rule

bad

bad

good

Design rule P

rocess c

onditio

n

Design rule

Pro

cess c

onditio

n




GDS: Maxwell

or Laker

Process T Time Etch



DR DR

1

DR

2

Fin

pitch

24

nm

22

nm

MG

ext.

15

nm

15

nm

Spac

er

7

nm

6

nm

Litho:

Sentaurus

3D structure:

Process

Explorer

Switching

behavior:

TCAD

Design rule

bad

bad

good

Design rule P

rocess c

onditio

n

Design rule

Pro

cess c

onditio

n

• Provides quick PPA estimate

• Includes process effects

• Enables process-design feedback

• Reasonable TAT


2-Input NAND Standard Library Cell

• 2-input NAND library cell with a load of:

– Fan-out of 2

– Metal wire that is 70 metal pitches long

• Cload = 2*Cpin + Cwire

• Cwire = 0.34 fF

• Typical Cload is 1 fF to 2 fF

A

B Q

Cload


Layout: 5nm 2-NAND Cell, 9 Tracks Tall


fins

Dummy

gate

PMOS

NMOS

gates

Gate

contact

S/D

contact

M1

Via1

M2 (PWR)

Via2

3 Gate Pitches wide

9 M

eta

l P

itch

es t

all

M2 (GND)

GP = 32nm MP = 24nm FP = 18nm


3D Library Cell in Process Explorer


M2

M1

M0

Transistors


Power-Performance-Area Evaluation in TCAD

• Transient analysis of the switching behavior in Sentaurus-Device

• Time delay is the averaged pull-up and pull-down delays

• Rigorous current flow analysis in the 3D structure


-0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0 2E-11 4E-11 6E-11 8E-11 1E-10

Po

ten

tia

l, V

Time, s

Input

Low_ROutput

3D current crowding


0

0.5

1

1.5

2

0 5 10 15 20 25

En

erg

y p

er

sw

itc

h, f

J

Switching delay, ps

FF 2x

FF 2x, low MG R

FF 1x

NW 2x2

NW 2x1

NW 1x2

5nm Technology Evaluation: PowerPerformanceArea @TCAD


Load: Fan-out of 2 plus 70 pitches long BEOL wire

3D current flow in TCAD

2-NAND logic cell

Reference 2-fin FF cell


0

0.5

1

1.5

2

0 5 10 15 20 25

En

erg

y p

er

sw

itc

h, f

J

Switching delay, ps

FF 2x

FF 2x, low MG R

FF 1x

NW 2x2

NW 2x1

NW 1x2





2-NAND logic cell

10%

Low MG resistance: 10% power reduction


Insight Into Metal Gate Resistance Effect

• Due to metal resistance, the input signal takes time to get to the fins

• Different parts of the gate experience different biases at any given time

• This is a new effect, due to the lack of space inside MG for tungsten fill, so MG resistivity increases from ~20 mW.cm to ~200 mW.cm

• It gets worse for 3 and 4 fins


2D cut across the gate

PMOS Gate

NMOS Gate

NMOS fins

PMOS fins

2-NAND cell

Electrostatic potential map

Input signal arrives here first

delay

eve

n mor

e d

elay


0

0.5

1

1.5

2

0 5 10 15 20 25

En

erg

y p

er

sw

itc

h, f

J

Switching delay, ps

FF 2x

FF 2x, low MG R

FF 1x

NW 2x2

NW 2x1

NW 1x2





2-NAND logic cell

10%

30%

Fin depopulation from 2 to 1: 30% power reduction


0

0.5

1

1.5

2

0 5 10 15 20 25

En

erg

y p

er

sw

itc

h, f

J

Switching delay, ps

FF 2x

FF 2x, low MG R

FF 1x

NW 2x2

NW 2x1

NW 1x2





2-NAND logic cell

10%

30%

44%

Nano-wires: 44% better


0

0.5

1

1.5

2

0 5 10 15 20 25

En

erg

y p

er

sw

itc

h, f

J

Switching delay, ps

FF 2x

FF 2x, low MG R

FF 1x

NW 2x2

NW 2x1

NW 1x2





2-NAND logic cell

10%

30%

44%

50%

Nano-wire depopulation: 50% power reduction


0

0.5

1

1.5

2

0 5 10 15 20 25

En

erg

y p

er

sw

itc

h, f

J

Switching delay, ps

FF 2x

FF 2x, low MG R

FF 1x

NW 2x2

NW 2x1

NW 1x2





2-NAND logic cell

10%

30%

44%

50%

FinFET

NW

2 fins

1 fin


0

0.5

1

1.5

2

0 5 10 15 20 25

En

erg

y p

er

sw

itc

h, f

J

Switching delay, ps

FF 2x

FF 2x, low MG R

FF 1x

NW 2x2

NW 2x1

NW 1x2





2-NAND logic cell

10%

30%

44%

50%

FinFET

NW

2 fins

1 fin

0.000

0.200

0.400

0.600

0.800

1.000

1.200

FF 2xFF 1x

NW 2x2NW 2x1

NW 1x2

0.7

96

0.4

95

0.5

41

0.3

68

0.3

64

1

0.5

1.09

0.54 0.54

Cpin, fF

Ion, normalized


0

0.5

1

1.5

2

0 5 10 15 20 25

En

erg

y p

er

sw

itc

h, f

J

Switching delay, ps

FF 2x

FF 2x, low MG R

FF 1x

NW 2x2

NW 2x1

NW 1x2





2-NAND logic cell

10%

30%

44%

50%

FinFET

NW

2 fins

1 fin

0.000

0.200

0.400

0.600

0.800

1.000

1.200

FF 2xFF 1x

NW 2x2NW 2x1

NW 1x2

0.7

96

0.4

95

0.5

41

0.3

68

0.3

64

1

0.5

1.09

0.54 0.54

Cpin, fF

Ion, normalized50%

40%


0

0.5

1

1.5

2

0 5 10 15 20 25

En

erg

y p

er

sw

itc

h, f

J

Switching delay, ps

FF 2x

FF 2x, low MG R

FF 1x

NW 2x2

NW 2x1

NW 1x2





2-NAND logic cell

10%

30%

44%

50%

FinFET

NW

2 fins

1 fin

0.000

0.200

0.400

0.600

0.800

1.000

1.200

FF 2xFF 1x

NW 2x2NW 2x1

NW 1x2

0.7

96

0.4

95

0.5

41

0.3

68

0.3

64

1

0.5

1.09

0.54 0.54

Cpin, fF

Ion, normalized

~CV/I

~CV

2

50%

40%


0

0.5

1

1.5

2

0 5 10 15 20 25

En

erg

y p

er

sw

itc

h, f

J

Switching delay, ps

FF 2x

FF 2x, low MG R

FF 1x

NW 2x2

NW 2x1

NW 1x2





2-NAND logic cell

10%

30%

44%

50%

FinFET

NW

2 fins

1 fin

0.000

0.200

0.400

0.600

0.800

1.000

1.200

FF 2xFF 1x

NW 2x2NW 2x1

NW 1x2

0.7

96

0.4

95

0.5

41

0.3

68

0.3

64

1

0.5

1.09

0.54 0.54

Cpin, fF

Ion, normalized

~CV/I

~CV

2

•MOL capacitance engineering rules!


5nm 2-NAND Cell: What if We Rotate the Fins?

• Conventional

• 9 tracks tall

• Rotated fins

• 6 tracks tall


GP = 2 * MP FP = 2 * MP MP = 24nm

Relaxed GP & FP

reduce MOL C

This is possible due to fin depopulation


5nm 2-NAND Cell: What if We Rotate the Fins?

• Conventional

• 9 tracks tall

• Rotated fins

• 6 tracks tall


GP = 2 * MP FP = 2 * MP MP = 24nm

Relaxed GP & FP

reduce MOL C

This is possible due to fin depopulation


Better Routability and Better Power-Performance!


• Conventional

• 9 tracks tall

• 6 routing tracks

• Rotated fins

• 6 tracks tall

• 5 routing tracks

A

Z

B

A B Z

• 8% lower dynamic power

• Big M1 pins improve routability

• M2 is available for routing (not used within the cell)

GP = 2 * MP FP = 2 * MP MP = 24nm

Relaxed GP & FP

reduce MOL C


Summary

• Fins are getting slimmer and taller. Electrostatics requires narrow fins, which makes the fins fragile, forcing a switch to nano-wires.

• High mobility materials like III-V do not scale beyond 7nm, whereas Si scales gracefully down to 2nm design rules

• 5nm technology has multiple trade-offs in transistor architecture and MOL RC that require holistic engineering

• The rising “wave” of MOL RC is coming, but can be delayed by careful engineering of MOL architecture and MOL material properties


Documents

Technology Inflection Points: Planar to FinFET to Nanowire · Victor Moroz April 4, 2016 ISPD Invited talk Technology Inflection Points: Planar to FinFET to Nanowire