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MMS8010/8011 User Manual Copyright © 2017 Abaco Systems, Inc.

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Abaco Systems Product Manual

Vita 48.1 and 48.2 VPX plug in module

P/N 8010 zero ohm connected

P/N 8011 SSR connected

Six ECM Carrier card

Board shown with VITA48.2 top and bottom covers

www.abaco.com

http://www.abaco.com/

4-Port RS232/RS485 XMC Manual Copyright © 2017 Abaco Systems

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Life support statement

This Abaco Systems product is not designed, intended, specified or tested for life support use, any life support usage of this product is the responsibility of the purchaser of this product.

Static and handling precautions

Static precautions are mandatory in handling this equipment. Use a conductive wrist strap and handle the board in a static-free environment. Avoid touching components or connectors on the PCB, it is best to hold the PCB by the edges.

Warranty

Warranty information is found on the Abaco Systems website at www.abaco.com for product warranty or repairs please call or email Abaco Systems for an RMA number

Technical Support.

Please contact your sales representative for support with drivers and operating systems.

[email protected]

Liability Limitation.

IN NO EVENT SHALL ABACO SYSTEMS, INC. BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING BUT NOT LIMITED TO LOSS OF PROFIT OR OPPORTUNITY. FOR ANY PRODUCT NOT MANUFACTURED BY ABACO SYSTEMS, INC., THE CUSTOMER'S SOLE AND EXCLUSIVE REMEDY IS STATED IN THE MANUFACTURER'S OR PUBLISHER'S END USER WARRANTY ACCOMPANYING THE PRODUCT. IN NO EVENT SHALL ABACO SYSTEMS, INC.'S LIABILITY EXCEED THE REPAIR, REPLACEMENT OR COST OF THE SPECIFIC PRODUCT PURCHASED FROM ABACO SYSTEMS, INC. SOME STATES MAY NOT RECOGNIZE A DISCLAIMER OR LIMITATION OF WARRANTIES AND/OR LIMITATION OF LIABILITY SO THE ABOVE DISCLAIMERS MAY NOT APPLY. CUSTOMER MAY ALSO HAVE DIFFERENT AND/OR ADDITIONAL RIGHTS AND REMEDIES THAT VARY FROM STATE TO STATE.

Manual Revision

Rev 1 – 09/22/2017 – Abaco re-branding

Rev 0 – 10/03/2016 – Initial release

Part Numbers

P/N 8010 ECM carrier with 50K logic elements FPGA, SSR I/O. P/N 8011 ECM carrier with 50K logic elements FPGA, zero ohm I/O. P/N 8284 Hardware Kit for conduction cooled 5HP version, top & bottom covers. P/N 8228 Hardware Kit for conduction cooled 4HP version, top cover. P/N 8227 Hardware Kit for air cooled version Vita 48.1. A customer specific P/N is issued based, see ordering section in this manual.

All product names and trademarks are the property of their respective owners.

http://www.abaco.com/

mailto:[email protected]

VPX form factor Six Site ECM Carrier Copyright © 2017, Abaco Systems

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CAUTION (1) When developing designs for the ALTERA Cyclone FPGA, care must be exercised to insure that the FPGA logic design does not cause unsafe conditions in the system being controlled external to this board. (2)The design should be simulated for marginalities and proper functioning.


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TABLE OF CONTENTS INTRODUCTION ............................................................................................................................................... 6 FEATURES ........................................................................................................................................................ 8 SPECIFICATIONS............................................................................................................................................. 9 REFERENCES ................................................................................................................................................. 10 SOFTWARE REQUIREMENTS .................................................................................................................... 11 PCI device and vendor ID .................................................................................................................................................. 11Software considerations FPGA example design ............................................................................................................ 11Host Software Drivers ......................................................................................................................................................... 12FPGA ................................................................................................................................................................. 13 FPGA – Introduction ........................................................................................................................................................... 13FPGA Design ....................................................................................................................................................................... 13FPGA – IP modules ............................................................................................................................................................ 13FPGA – external circuits .................................................................................................................................................... 14FPGA ECM validation ......................................................................................................................................................... 15FPGA Programming............................................................................................................................................................ 16FPGA - Initialization - Load From Serial Flash Chip ...................................................................................................... 16FPGA - JTAG Programming header................................................................................................................................. 17JTAG connector, HDR1, pinout details ............................................................................................................................ 17FPGA Test Points ............................................................................................................................................................... 20FPGA Software register map ............................................................................................................................................. 20FPGA – LEDs ...................................................................................................................................................................... 21FPGA – BGA Ball locations ............................................................................................................................................... 22PIC MICROCONTROLLER DEVICE ........................................................................................................... 23 PIC microcontroller – Introduction .................................................................................................................................... 23PIC uC – external circuitry ................................................................................................................................................. 23PIC uC Programming.......................................................................................................................................................... 24JP7 RS232 Monitor Terminal / PIC uC programming .................................................................................................... 24ECM I/O SSR SWITCHING AND REDUNDANCY .................................................................................... 27 ECM I/O Card cage level redundancy .............................................................................................................................. 28ECM I/O circuit details ........................................................................................................................................................ 29ECMS AND ECM SITES ................................................................................................................................ 31 ECM site connectors JP1, JP2, JP3, JP4, JP5 and JP6 ............................................................................................... 31ECMs Original vs Enhanced .............................................................................................................................................. 32ECMs, electrical conversion modules, characteristics ................................................................................................... 35Installation ECMs orientation and hardware .................................................................................................................... 36THERMAL DESIGN ........................................................................................................................................ 38 Thermal paths on the 8010/8011 ...................................................................................................................................... 38Thermal coupling of ECMs to the heat frame .................................................................................................................. 38VPX CONNECTORS....................................................................................................................................... 39 VPXP0 Connector ............................................................................................................................................................... 40VPXP1 Connector ............................................................................................................................................................... 41VPXP2 Connector ............................................................................................................................................................... 42VPXP0, Connector to Backplane RP0 pin mapping ....................................................................................................... 43VPX Connector Keying ....................................................................................................................................................... 45Misc. VPX signals ............................................................................................................................................................... 45BACKPLANE AND RTM ............................................................................................................................... 47 Backplane considerations .................................................................................................................................................. 47Rear Transition module considerations ........................................................................................................................... 48POWER OVERVIEW ...................................................................................................................................... 50 INSTALLATION ............................................................................................................................................... 51 VITA48.1 air cooled Installation ........................................................................................................................................ 51VITA48.2 4HP or 5HP conduction cooled Installation .................................................................................................... 51Installation and Handling Warnings .................................................................................................................................. 51APPENDIX A TYPICAL APPLICATIONS ................................................................................................... 52 APPENDIX B ORDERING INFORMATION ................................................................................................ 53 APPENDIX C PRINTED CIRCUIT PLACEMENT ...................................................................................... 54 APPENDIX D RELEVANT SCHEMATICS .................................................................................................. 55


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APPENDIX E MECHANICAL ........................................................................................................................ 69 VITA 48.1 configuration ...................................................................................................................................................... 69VITA 48.2, 4HP and 5HP configuration ........................................................................................................................... 69

Table of Figures Figure 1 Block Diagram 6 site ECM 3U VPX carrier ........................................................................................................ 6Figure 2 FPGA internal set of IP modules (ECM IP created by Abaco Systems) ...................................................... 13Figure 3 FPGA with external circuitry ............................................................................................................................... 14Figure 4 Original ECMs used on an Enhanced SITE ..................................................................................................... 15Figure 5 JTAG header location shown in red .................................................................................................................. 18Figure 6 programming adapter, showing the orientation to the red stripe on the cable. ........................................... 18Figure 7 TP1 offers eight FPGA test points shown in red. ............................................................................................ 20Figure 8 FPGA LED locations ........................................................................................................................................... 21Figure 9 location of LEDs connected to PIC uC ............................................................................................................. 24Figure 10 JP7 RS232 port ................................................................................................................................................. 25Figure 11 RS232 cable diagrams, P/N 6351 ................................................................................................................... 26Figure 12 redundant VPX card cages with redundant I/O connection on external cabling. ..................................... 28Figure 13 I/O circuit details. .............................................................................................................................................. 29Figure 14 The two I/O options. .......................................................................................................................................... 29Figure 15 ECM block diagram. .......................................................................................................................................... 35Figure 16 example selection of ECMs. ............................................................................................................................ 36Figure 17 Signal names of J1 connector on an ECM module ...................................................................................... 37Figure 18 VPX connectors, P0 Red, P1 Blue, P2 Green, the 10 black holes are non-electrical ............................. 39Figure 19 Mapping pins VPXP2, on the left, to the backplane, VPXJ2 on the right. ................................................. 43Figure 20 frontal view of the VPX connectors, note the empty wafer location shown in RED ................................. 44Figure 21 Mapping between the 7 press fit pins on wafer 1 and the 9 edge finger connections on wafer 1. ........ 44Figure 22 overview of Wafer locations for the 8010/8011. ............................................................................................ 45Figure 23 block diagram of RTM signals ......................................................................................................................... 48Figure 24 overview of the wafers and pins on a RTM, rear transition module. .......................................................... 49Figure 25 Corresponding view of Wafer locations and identification scheme for a VPX plug in card..................... 49Figure 26 Power supply architecture ................................................................................................................................ 50Figure 27 Printed Circuit Placement – side 1 .................................................................................................................. 54Figure 28 Printed Circuit Placement – side 2 .................................................................................................................. 54Figure 29 Two metal rails and front panel for VITA 48 configuration. ......................................................................... 69Figure 30 Top Cover and two spacers for 4HP configuration. ...................................................................................... 69Figure 31 Top Cover and bottom cover for VITA 48 5HP configuration. ..................................................................... 70

Table of Tables Table 1 - Device/Vendor ID ............................................................................................................................................... 11Table 2 Altera programmer header pinouts ..................................................................................................................... 17Table - 3 FPGA LED function ............................................................................................................................................ 21Table 4 JP1,2,3,4,5,6 to VPX connectors same for Original and Enhanced .............................................................. 32Table 5 New signal functions Original vs Enhanced ECMs. ......................................................................................... 33Table 6 Misc. signal functions and voltages. ................................................................................................................... 34Table 7 ECM P/N and types the example selection of ECMs....................................................................................... 36Table 8 Table showing signal names for the above drawing. ....................................................................................... 44


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Introduction

VPX P1/P0PCI express

Altera Cyclone V FPGA

Electrical Conversion

Module Site A


Module Site B


Module Site C


Module Site D

Digital Control /Data

Analog / Digital I/O

VPX P2 Rear I/O (64 sig)


Module Site E


Module Site F


4 Lane

Optional SSRs

Optional SSRs

Optional SSRs

6 Isolation Enables

323232323232

16

16

16

16

16

16

VPX P0

IPMI-A, IPMI-B

Power

+12V,+3.3V,+5VRS232 Serial

Misc. eeprom,

LEDs

PIC uC

Optional SSRs

Optional SSRs

Optional SSRs

Figure 1 Block Diagram 6 site ECM 3U VPX carrier

The Abaco Systems 6 site ECM 3U VPX carrier supports up to six Abaco Systems Electrical Conversion Modules (ECMs) in a VITA 46 VPX form-factor. Each ECM site connects 32 single-ended 3.3V signals to the FPGA. The specific ECM board installed on a site converts the FPGA signals to 16 I/O signals, for a total of 96 I/O signals across the six ECM sites. For this product, the 96 ECM I/Os are available on differential wafers P1-8 thru P1-16, and P2-1 thru P2-16. In VITA 65 OpenVPX terminology, this product conforms to SLT3-PER-1F-14.3.2, where a single data-plane Fat pipe (the 4x lane PCIe port) provides connectivity to a PCIe fabric; the remaining differential wafers are for User I/O.

The VPX carrier is built and stocked in two fundamental “C4” density configurations: One with opto-isolated Solid State Relays (SSRs) between the ECM I/O and the VPX wafers, and a second replacing the SSRs with zero ohm resistors. The intent of the SSR version is to allow “failover” to a redundant hardware set for high-reliability applications. For each ECM, the associated SSRs are controlled by an FPGA signal, with the power-up default being “off.” Additionally, the +12V backplane power must be supplied to power the SSR LEDs, and this provides an additional method of disabling the entire bank of SSRs for an installed VPX board.

Mechanical packaging of the fundamental boards is accomplished by adding either a 5HP VPX front panel to support air-cooled VITA 48.1 systems, or VITA 48.2 conduction cooled packaging with wedge locks. The VITA 48.2 packaging can be either a top cover only for 0.8” pitch (4HP) frames, or both a top and bottom cover for 1.0” or 1.2” pitch (5HP/6HP) frames. Additionally, customers may specify various


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keying angles (0, 45, 90, 270, 315, or none) for the two alignment guides adjacent to the backplane connector; the default and stocked angle is “none”.

Four GEN 1 PCIe lanes, presented to the board via the P1-1 thru P1-4 differential wafers, are wired to an Altera Cyclone V GX FPGA. The FPGA provides a hard core PCIe interface, which bridges to internal FPGA IP via the Altera Avalon bus. The stocked board is populated with 5CGXFC4C6F23I7N, C4 density, providing an equivalent 50K Logic Element (LE) capacity. A second custom build option is available for C7 density at 149.5K LE. Generous SRAM, multipliers, logic, and PLLs are supplied by the Cyclone V FPGA, alleviating need for external memory and devices.

The FPGA is effectively the engine for the carrier, executing a resident IP core design and orchestrating various processing and I/O functions for the installed ECMs. The ECMs themselves have unique characteristics and capabilities that are supported by the FPGA and for which separate drivers and code are installed as needed. Each ECM site can be populated by a different module to allow considerable design flexibility.

On power up, an FPGA design image is loaded from a Quad serial flash memory (QSPI). This allows the PCIe interface and PCI configuration space to be initialized by the host processor. In this case, the user’s application is operational on power up. Alternatively, by using Altera’s Configuration via Protocol (CvP) technique, a host-initiated initialization and update of the FPGA core logic over PCIe may be accomplished later in the system bring up, which is useful for in-system FPGA code revision updates. The design also allows the QSPI device to be programmed from the host over the PCIe so that a subsequent power cycle will initialize the FPGA with new code.

External devices connected to the FPGA include Status LEDs, a temperature sensor, and a 93LC66 EEPROM. A PIC microcontroller, programmed by Abaco Systems, is used for IPMI support (VITA 46.11) and has a user accessible RS232 port for viewing power supply rail voltages and geographical address.

JTAG programming with an Altera USB blaster, or equivalent, is supported and accessed by the standard 10 pin JTAG header. Thus, in-circuit QSPI device programming, direct programming of the FPGA, and support for Altera’s Signal Tap Logic Analyzer are realized.

The design environment for this product is Altera’s Quartus Prime, with Qsys providing the interconnection between the Avalon bus IP components within the FPGA. Abaco Systems provides a sample design, including Altera Quartus FPGA design files, and “C” source code, for the customer’s specific complement of ECMs and XMC carrier card. A unique orderable Abaco Systems Part Number is assigned to this complement of mechanical enclosure (VITA 48.1 air-cooled, 48.2 conduction cooled, etc.), guidepost keying, carrier card, ECMs, and FPGA code programmed into the QSPI device. Often, the supplied sample code is tailored to a customer’s requirement by Abaco Systems, and no additional FPGA design effort on the customer’s part is needed.

In order to facilitate rapid availability of finished product, Abaco Systems maintains an inventory of the commonly used fundamental parts: keying guides, air-cooled front panels, assembled/tested boards, conduction cooled heat frames, and ECMs. To minimize additional development work, Abaco Systems has created an existing collection of FPGA IP modules and associated “C” driver code, in addition to the standard Qsys modules from the Altera library. This allows customers to procure a product that exactly meets requirements without having to spend considerable NRE and calendar time to get a prototype. Furthermore, the Abaco Systems FPGA-based Micro Mezzanine System (MMS)/ECM approach provides a flexible platform for changes discovered during development.


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Features • Altera Cyclone V GX (standard 50KLE, optional 149.5KLE)

• Up to six ECMs

• 32 FPGA signals per ECM

• 16 I/O per ECM

• 96 I/Os total out VPX differential wafers P1-[8:16] and P2-[1:16]

• VITA 65 OpenVPX SLT3-PER-1F-14.3.2 profile

• PCIe hard core built into FPGA

• 4x PCIe lanes w/Gen 1 (2.5 Gb/s) performance

• VITA 46.4 PCIe on wafers P1-[1:4]

• VITA 46.0 P0 power for +3.3, +5, +12, -12, and system control

• On board PIC microcontroller

• PIC microcontroller RS232 dumb-terminal port

• VITA 46.11 IPMI support type 1

• Easily configured using Quartus/Qsys

• Supports NIOS processor

• Configure FPGA by QSPI flash, PCIe (CvP), or JTAG

• Sample FPGA and “C” code provided

• FPGA controlled status LEDs

• Temperature sensor

• 93LC66 EEPROM

• Altera USB blaster JTAG header (allows debug Altera with signal tap)

• Industrial temperature

• RoHS compliant

• Power required: +3.3V, +12V (SSR); +5, +12, -12 as need by ECMs

• Patented

Copyright © 2017 Abaco Systems, Inc.

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-40 to +85 degrees C-55 to +105 degrees CNot Specified or Characterized. Typical similar equipment is at 15,000ft.5% to 90% non-condensing.Not specified or Characterized.Not specified or Characterized.Available on request.123 grams board without covers and with six representative ECMsApplication dependent.4 lanes.100MHz or local clock as per FPGA design.+3.3V, +3.3V Aux, +12V Tol: +/-5%+12V,-12V,+5V,+3.3V as per ECMs in use.

MMS8010/8011 User Manual

Specifications

Temperature (Operating): Temperature (Storage): Altitude:

Humidity(Operating/Storage): Vibration: Shock: MTBF: Weight: Power: PCI Express: PCI Express Clock: Voltages Required Carrier: Voltages Required ECM: Size: 100 mm x 170 mm PCB size, without covers.


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References

These references should help the user to understand this product. This manual generally excludes information that is better presented in these references:

1. PCI Express Card Electromechanical Specification, Revision 1.1 standard for PCI Express bus –maintained by PCI Special Interest Group. www.pcisig.com

2. ANSI/Vita 46.0-2007 VPX Base electrical and Mechanical specification. Maintained by Vitawww.vita.com

3. ANSI/Vita 46.4-2007 PCI express on VPX. Maintained by Vita www.vita.com

4. ANSI/Vita 46.11-2015 System Management on VPX. Maintained by Vita www.vita.com

5. ANSI/Vita 48.0-2010 VPX REDI Cooling specification. Maintained by Vita www.vita.com

6. ANSI/Vita 48.1-2010 Mechanical Specifications for Microcomputers REDI Air Cooling Applied toVITA 46. Maintained by Vita www.vita.com

7. ANSI/Vita 48.1-2010 Air Mechanical Specifications for Microcomputers REDI Conduction CoolingApplied to VITA 46. Maintained by Vita www.vita.com

8. ANSI/Vita 65.0-2010 OPEN VPX Organizes the versatile VPX system into a series of industrialcompatible backplane, module and chassis profiles. Maintained by Vita www.vita.com

9. IEEE 1101.1-1998 Standard for Mechanical Core Specifications for Microcomputers. Maintained bywww.ieee.org

10. IEEE 1101.2-1992 Standard for Mechanical Core Specifications for Conduction-Cooled Eurocards.Maintained by www.ieee.org

11. IEEE 1101.10-1996 Standard for Additional Mechanical Specifications for Microcomputers.Maintained by www.ieee.org

12. Altera Cyclone V FPGA Documentation can be found at www.altera.com.

13. ECM Support Documents email [email protected] to request MMS documents

http://www.pcisig.com/

http://www.vita.com/







http://www.ieee.org/



mailto:[email protected]


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Software Requirements

Writing to and reading from the PCI express BARs and offsets to access the ECM control registers allows the user to write their own host program.

PCI device and vendor ID When performing a PCI bus scan look for the Vendor, Device ID and Sub Device ID to each VPXECM configuration will have a unique Sub Device ID.

Register Value Name Description

0x00-0x01 0x1D61 Vendor ID Identifies Abaco Systems.

0x02-0x03 0x1000 Device ID Identifies Cyclone V designs

0x2C-0x2D 0x1D61 Sub Vendor ID Identifies Abaco Systems.

0x2E-0x2F 0x1004 Sub Device ID Identifies specific orderable P/N, will vary.

Table 1 - Device/Vendor ID

Software considerations FPGA example design The FPGA example design, which comes programmed in the ECM carrier, provides enough functionality to access all the features of the populated ECMs.


12

Host Software Drivers The Abaco Systems driver works for Linux or Windows, if your operating system has a PCI express driver then it should be possible to use it along with the BARs and offsets, but will require some programming effort.


13


FPGA

FPGA – Introduction This section discusses the details of the FPGA design, an Altera Cyclone V GX (standard 50KLE, optional 149.5KLE) with a PCIe hard core built into the FPGA.

The Cyclone V FPGA on the Abaco Systems 8010/8011 board interfaces to external circuitry using Abaco Systems supplied IP modules.

FPGA Design Abaco Systems supplies an example design in a compressed format with a QAR extension which can be extracted by the Altera software. The nature of the example design will not be examined in this document as it is better understood by exploring the design with the Altera software.

FPGA – IP modules Internal to the FPGA are a mix of IP modules developed by Abaco Systems, Altera, third parties and users. Shown below is an example of a simple set of IP modules which could be used for an application. The IP modules are usually Verilog or AHDL code. The root of the design is a Verilog file. The NIOS processor provides local DMA control.

Figure 2 FPGA internal set of IP modules (ECM IP created by Abaco Systems)


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FPGA – external circuits

CYCLONE V FPGA

CLK 100 MHz, U90

TestPoints

TP1

JTAG Program HeaderHDR1

EEPROMU89

TempSensor

U88

LED D5

3 4 4 8

1

LED D6

LED D7

LED D8

CLKIN DATA / CONTROL

4 LANE

VPX P2 Connector

100MHzCLKIN

Serial FLASH

Program Memory

U91

4 data2 ctrlCLK

PERST

32

FPGAModeJMP1

5

LED D9

USERLEDs

LED D10

ECMSite A

DATA / CONTROL

32

ECMSite B

DATA / CONTROL

32

ECMSite C

32

ECMSite D

DATA / CONTROL

16 16 16 16

1 1 1

100MHzDifferential

CLKIN

32

ECMSite E

DATA / CONTROL

16

ECMSite F

DATA / CONTROL

16

VPX P1 Connector

32

VPX P1 Connector

PIC Micro Controller

U83

6

CONFIG DONE

LANEACTIVE

LED0

LED1

LED2

LED3

LED D2

LED D3

Figure 3 FPGA with external circuitry

External circuits list

Six ECMs, with 32 data lines each.

Connects to the host processor via a 4 lane PCI express bus.

U90 generates clock inputs and is normally the primary clock input.

The PCI express clock can be used as the primary clock but must not be 25MHz

Six LEDs,

A temperature sensor U88.

A 93LC66 eeprom, 4Kbit/512 bytes, U89


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FPGA ECM validation The module detection IP in the FPGA confirms that the ECM matches the ECM IP in the FPGA. If it matches it enables the outputs, if not it leaves them in a high impedance state.

CYCLONE V FPGA

DA0..31

Enhanced ECM inSite A

SERASerial

ID Chip

MODULE Interface IP detects

I/O configuration

MODULE IP for each ECM

A special case is the use of an Original ECM used in an Enhanced ECM SITE.

CYCLONE V FPGADA0..25

Original ECM inSite A

SERASerial

ID Chip

MODULE Interface IP detects ECM is

Original type

MODULE IP for each ECM

DA28..31Upper 4 bits set to High Z

On FPGA

GNDon ECM

DA26..27

Figure 4 Original ECMs used on an Enhanced SITE

Note that on Original ECMs bits 26 & 27 are outputs from the ECM only.


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FPGA Programming The FPGA is Configured by QSPI flash, PCIe (CvP), or the JTAG header.

The FPGA and serial flash can be programmed from the JTAG header. Alternately once the correct IP is loaded in the serial flash the FPGA and the serial flash can be reprogrammed over the PCI express bus.

Refer to the Altera documentation for detail on CvP including how to use and its limitations.

Refer to the Abaco Systems SW EPCS programming document for details on IP required to program the serial flash and functions to update the serial flash.

JTAG HeaderHDR1

4

4 LANE

Serial FLASHProgram Memory

2 ctrl

CLK

ProgramModeJMP1

5

LED D9

LED D10

VPX P0/P1 Connector

CONFIG DONE

LANEACTIVE

4

PERST

ConfigurationSRAM IP for

CVP

CYCLONEV FPGA

IP for CVP

Fixed for AS fast mode

Initially written using JTAG

JTAG can write to SRAM or Serial Flash

CvP over PCIecan write to configuration

SRAM. Application SW over PCIe can write to Serial Flash,

but IP to do so needs to be included

IP for SFlash

IP written via CvP

FPGA - Initialization - Load From Serial Flash Chip Upon power up, the FPGA will be loaded with an image from the serial flash chip. This is the only way to load the FPGA from the flash chip it cannot be reloaded from flash after power up.

If a valid image is written from the serial flash chip, the FPGA will be initialized to that image.

If no valid image is found the FPGA will be un-initialized and all lines will be tri-stated, this condition is also indicated by LED D10 not illuminating.


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FPGA - JTAG Programming header The header for programming the Altera FPGA is connected to from the top side of the board as pictured below.

The board connector or the carrier card connector allows use of Altera Signal Tap for debugging FPGA designs. Altera Signal Tap feature is not available when programming over the PCI express bus. When using SignalTap Applications, set the Mode to JTAG.

Since the JTAG pins are not connected on the VPX connectors, the FPGA cannot be programmed from the backplane JTAG.

JTAG connector, HDR1, pinout details

Function Header Pin Number

Header Pin Number

Function

GND 10 9 TDI

NC 8 7 NC

NC 6 5 TMS

+3.3V 4 3 TDO

GND 2 1 TCK

Table 2 Altera programmer header pinouts

TDO output from the VPX card, TDI input to the VPX card. NC no connection.


18

Figure 5 JTAG header location shown in red

Figure 6 programming adapter, showing the orientation to the red stripe on the cable.


19

Figure Cover for HDR1, remove 2 screws to access.


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FPGA Test Points There are eight test points on the back of the PCB for probing or soldering wires which can be driven or read from the FPGA.

Figure 7 TP1 offers eight FPGA test points shown in red.

FPGA Software register map The Altera design software generates a C language header file ending in “_top.h” which provides the addresses for the ECM control registers, data registers and BAR locations. This is useful for customer application programs.


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FPGA – LEDs

Figure 8 FPGA LED locations

The six LEDs connected to the FPGA provide an indication of certain conditions.

Signal Function Ref. Des. FPGA

LED0 low turns on User LED D5 Output




Lane Active

LED full on 4 lanes PCI express connected

LED blinks less than 4 lanes connected LED off no PCI express connection

This is as implemented in Abaco Systems example design.

D9 Output

Config Done

LED full on FPGA has configured

LED full on FPGA has not configured

D10 Output

Table - 3 FPGA LED function


22

Note that depending on the FPGA design any of the LEDs can serve as a PCI express status LED. The config done LED is hardwired to a dedicated FPGA output and is not programmable.

FPGA – BGA Ball locations The ball locations of the FPGA signals are documented in the example FPGA design supplied by Abaco Systems. They are contained in a QSF file.- From this design the EEPROM U89, ball locations are as in the four bolded lines.

set_location_assignment PIN_AC9 -to eecs

set_location_assignment PIN_AC8 -to eeclk

set_location_assignment PIN_AB10 -to eedi

set_location_assignment PIN_AC10 -to eedo


23

PIC Microcontroller device

PIC microcontroller – Introduction This section discusses the details of the PIC uC functions, such as IPMI, voltage monitoring and RS232 communications via. a monitor program. The monitor program reports temperature, IPMI status and other information.

CYCLONE V FPGA

SYSRESET

JP7 ConnectorPIC

Programming/ RS232 port

Prog. 3

VPX P0 Connector

PIC uCIPMC

Voltage Monitor

6

LED D2

LED D3

Voltages

IPMI-BIPMI-A IPMI-RTM

VPX P2 Connector

MVMROGA0..4,GAP

RS232TX

RS232RX

Heart BeatIPMI ActivityBoot loader

I2CI2C

PIC uC – external circuitry

Uses on chip A/D converters to monitor voltages.

The on chip UART providing a RS232 dumb terminal.

Acts as an IPMI controller also called an IPMC, as per VITA 46.11

Indicates normal operation with a blinking heartbeat LED.

Indicates IPMI activity with a blinking LED.

Both LEDs blinking indicate the bootloader is active.


24

Figure 9 location of LEDs connected to PIC uC

PIC uC Programming Not programmable by the customer

JP7 RS232 Monitor Terminal / PIC uC programming


25

Figure 10 JP7 RS232 port

To use the RS232 port for system monitoring and control, Abaco Systems offers a P/N 6351 adapter cable. The P1 end connects to JP7. To orient the cable correctly check that the blue wire is to the left and connects to pin 1 of JP7. Customers wanting to make their own cables can use the cable diagram shown below.

PINS 1,2 and 3 of JP7 are a RS232 debug/monitor port, pin 4 shown as an X is cut. Pins 4 thru. 9 are for Abaco Systems use only.


26

Color P2 DB9 Female

P1 Female 3x1

Signal

YELLOW 3 2 RXD BLUE 2 1 TXD RED 5 3 GND

Figure 11 RS232 cable diagrams, P/N 6351


27

ECM I/O SSR switching and redundancy

The intent of the SSR version is to allow “failover” to a redundant hardware set for high-reliability applications. For each ECM, the associated SSRs are controlled by an FPGA signal, with the power-up default being “off.” Additionally, the +12V backplane power must be supplied to power the SSR LEDs, and this provides an additional method of disabling the entire bank of SSRs for an installed VPX board.

In the illustration of card cage level redundancy each 8010/8011 card is identical with the same selection of ECMs. One card cage would be powered down under normal operation. When an error condition is detected on a module the entire card cage can be switched off and the other card cage turned on.

Backplane level redundancy, not illustrated, is where two identical 8010/8011 boards are populated on the same backplane.

In the illustration of board level redundancy the pair of ECMs in sites A and B are identical, as are the pairs C & D and E & F. One of each pair is switched off under normal operation. When an error condition is detected on a module it can be switched off and the other module switched on. The illustration also shows the I/O shorted together on the RTM which is an approach not possible with rack and backplane level redundancy.


28

ECM I/O Card cage level redundancy

VPX Backplane Card Cage1


Module Sites A...E

SSRSwitches

ON6 Isolation EnablesControlled by FPGA

96

VPX Conn.

RTM Conn.

I/OConn.

On RTM

Analog / Digital 96 I/O

Turing off +12V to the card cage

forces the SSRs off.

96

VPXECM6 Board 1

VPX Backplane Card Cage2


Module Sites A...E

SSRSwitches

OFF6 Isolation EnablesControlled by FPGA

96

VPX Conn.

RTM Conn.

I/OConn.

On RTM


Turing off +12V to the card cage

forces the SSRs off.

96

VPXECM6 Board 2 Rear transition module 2

Rear transition module 1ExternalCabling

Figure 12 redundant VPX card cages with redundant I/O connection on external cabling.


29

ECM I/O circuit details

VPX Backplane

¼ ECM Site VPX Conn.

RTM Conn.

SSR Switches for 1/4 ECM site

Bit 3

Each SSR Enable turns on 4 identical LED strings per ECM

Bit 3

+12V acts like a global disable for all 96 SSRs

Current source

Bit 2 Bit 2

Bit 1 Bit 1

Bit 0 Bit 0

Figure 13 I/O circuit details.

0 ohm optionStandard build

SSR optionStandard Build

Figure 14 The two I/O options.

Characteristics SSR

• Back to back MOSFET opto-isolated type SSR

• Max 0.8 ohms, Load = 100mA

• Up to 60V across SSR

• 600mA max load current @25 deg. C.

• 480mA max load current @80 deg. C.

• See also datasheet for IXYS P/N CPC1018N

• Order base P/N 8010

Characteristics zero ohm


30

• Lower cost

• Order base P/N 8011


31

ECMs and ECM sites

ECM site connectors JP1, JP2, JP3, JP4, JP5 and JP6 The six 80 pin ECM connectors are electrically and mechanically identical allowing interchangeability of modules.

The data signal flow, is from the PCI express bus on the VPX connectors, to the FPGA, then to the ECM module. After conversion to I/O signals by the ECM the signal flow is then from the ECM back to the VPX connectors as user I/O.


32

ECMs Original vs Enhanced All six ECM sites on the 8010/8011 are Enhanced, so all sites are compatible with both Original and Enhanced ECMs. The connections are identical for all six sites.

The I/O signals are the same for Original and Enhanced. ECMs.

I/O signals from FPGA to ECM site and module.

ECM carrier pin IO

SITE x JPX pin 16 IO0 JPX pin 18 IO1 JPX pin 28 IO2 JPX pin 30 IO3 JPX pin 52 IO4 JPX pin 54 IO5 JPX pin 64 IO6 JPX pin 66 IO7 JPX pin 65 IO8 JPX pin 63 IO9 JPX pin 53 IO10 JPX pin 51 IO11 JPX pin 29 IO12 JPX pin 27 IO13 JPX pin 17 IO14 JPX pin 15 IO15

Table 4 JP1,2,3,4,5,6 to VPX connectors same for Original and Enhanced

The voltage level and other details of the I/O signals are determined by the ECM type plugged into the ECM site.


33

Data signals from FPGA to ECM site and module.

Most signals are bi-directional, but DA26 and DA27 are dedicated inputs into the FPGA.

The data signals from the ECM to the FPGA are +3.3V logic levels.

Four pins which were grounds on Original ECMs are now FPGA signals. These new FPGA signals will be tri-stated when using Original ECMS in an Enhanced ECM site, but driven for Enhanced ECMs in an Enhanced ECM site.

ECM carrier pin

Name

Original

Type

Original

Name

Enhanced

Type

Enhanced

SITE x JPX pin 10 DA0 BIDIR DA0 BIDIR JPX pin 12 DA1 BIDIR DA1 BIDIR JPX pin 22 DA2 BIDIR DA2 BIDIR JPX pin 24 DA3 BIDIR DA3 BIDIR JPX pin 34 DA4 BIDIR DA4 BIDIR JPX pin 36 DA5 BIDIR DA5 BIDIR JPX pin 46 DA6 BIDIR DA6 BIDIR JPX pin 48 DA7 BIDIR DA7 BIDIR JPX pin 58 DA8 BIDIR DA8 BIDIR JPX pin 60 DA9 BIDIR DA9 BIDIR JPX pin 70 DA10 BIDIR DA10 BIDIR JPX pin 72 DA11 BIDIR DA11 BIDIR JPX pin 71 DA12 BIDIR DA12 BIDIR JPX pin 69 DA13 BIDIR DA13 BIDIR JPX pin 59 DA14 BIDIR DA14 BIDIR JPX pin 57 DA15 BIDIR DA15 BIDIR JPX pin 47 DA16 BIDIR DA16 BIDIR JPX pin 45 DA17 BIDIR DA17 BIDIR JPX pin 35 DA18 BIDIR DA18 BIDIR JPX pin 33 DA19 BIDIR DA19 BIDIR JPX pin 23 DA20 BIDIR DA20 BIDIR JPX pin 21 DA21 BIDIR DA21 BIDIR JPX pin 11 DA22 BIDIR DA22 BIDIR JPX pin 9 DA23 BIDIR DA23 BIDIR JPX pin 40 DA24 BIDIR DA24 BIDIR JPX pin 41 DA25 BIDIR DA25 BIDIR JPX pin 42 DA26 INPUT DA26 BIDIR JPX pin 39 DA27 INPUT DA27 BIDIR JPX pin 44 GND Power DA28 BIDIR JPX pin 37 GND Power DA29 BIDIR JPX pin 38 GND Power DA30 BIDIR JPX pin 43 GND Power DA31 BIDIR

Table 5 New signal functions Original vs Enhanced ECMs.

Note Original differences in GREEN, Enhanced differences in RED.


34

Misc. signals from FPGA to ECM site and power.

The serial number is output by the ECM continuously and is read by the FPGA there is also a dedicated 3.3V power to the serial number chip. These signals are the same for Original and Enhanced ECMs.

ECM carrier pin

Name Type

SITE x JPX pin 1 +12V Power JPX pin 2 -12V Power JPX pin 4 +3.3V Power JPX pin 6 +3.3V Power JPX pin 3 +5V Power JPX pin 5 +5V Power

JPX pin 78 +3.3V Serial Number power

JPX pin 78 Serial number

data

Output to FPGA

Table 6 Misc. signal functions and voltages.


35

ECMs, electrical conversion modules, characteristics

+3.3V

SERA Serial ID Chip

I/O 0..15

+12V+5V

GND

DA 0..31

+3.3V

-12V

I/OConversion

Circuits

EnhancedECM

Figure 15 ECM block diagram.

An ECM or electrical conversion module takes data signals and converts them to some kind of I/O signal. Generally they will always use ground and provide serial identification but the mix of other signals used will vary according to the design requirements of the specific ECM.

The Enhanced type provides 32 bits of connection to the FPGA, while the original ECMs provided 28 bits.


36

Installation ECMs orientation and hardware When changing out an ECM or adding an ECM take careful note of which ECM corresponds to which ECM SITE. The IP in the FPGA for each site must match the ECM populated in that SITE.

Step 1. Observe that the mounting holes line up with the standoffs on the carrier card. The connector is not symmetric and the mounting holes will not line up if the module is rotated 180 degrees. Also Observe that the white dot on the carrier card and the ECM are aligned. See red arrows.

Figure 16 example selection of ECMs.

Step 3. Apply Loctite 222MS thread-locker or similar to the threads of the M2.5 screws, for VITA48 conduction cooled boards use the M2.5 standoffs circled in black instead of the screws.

Step 4. Screw down each ECM with two fasteners.

Table 7 ECM P/N and types the example selection of ECMs.

ECM SITE B A E

ECM P/N 3556 5308 5041

TYPE Micro SD RS232 RS485

TYPE Comparator I2C D/A converter

ECM P/N 3564 5360 5081

ECM SITE D C F

4-Port RS232/RS485 XMC Manual Copyright © 2017 Abaco Systems, Inc.

Figure 17 Signal names of J1 connector on an ECM module

The signal names in black call out 4 additional FPGA signals on Enhanced ECMs, the new FPGA signals replaced 4 grounds on Original ECMs.


38


Thermal Design

Thermal paths on the 8010/8011 There are three major paths for conductive heat flow on the VPX ECM carrier.

1) The first shown in red is safety ground, the board guides and the perimeter planes carry it to thebackplane.

2) The covers and clamp assembly which carry the heat to the card cage.

3) The voltage and ground planes which connect to components connect to the backplane. Theground plane is also flooded on the top and bottom of the PCB to aid is heat dissipation.

Thermal coupling of ECMs to the heat frame An ECM, shown in yellow, thermally couples to the top signal ground plane through the optional thermally conductive pads, the pads are shown in blue.

The ECM standoffs are electrically isolated, except when connected to safety ground when the top cover is used. The attachment to the top cover is through an additional standoff shown in orange.

The thermal pads, shown as blue, are 0.875” x 0.375 inch strips of Bergquist GPVOUS-0.080-AC-0816 which are 0.080” thick. Other materials could be used as well.


39

VPX connectors

The three VPX connectors provide PCI express, User I/O and power from the backplane. This arrangement conforms to a VITA 65 OpenVPX SLT3-PER-1F-14.3.2 profile

PCI express is implemented on wafers P1-[1:4].

User I/O is implemented with 96 I/Os total on VPX differential wafers P1-[8:16] and P2-[1:16]

Figure 18 VPX connectors, P0 Red, P1 Blue, P2 Green, the 10 black holes are non-electrical


40

VPXP0 Connector The VPXP0 connector supplies power, reset, geographical addressing, and the PCI express clock from the backplane.

Row G Row F Row E Row D Row C Row B Row A

1

2

3

4

5

6

7

8

12v(VS1) 12v 12v NO PAD 3.3v (VS2) 3.3v 3.3v

2 12v 12v 12v NO PAD 3.3v 3.3v 3.3v

3 5v(VS3) 5v 5v NO PAD 5v 5v 5v

4 SM2 SM3 GND -12v_AUX GND SYSREST NMMRO

5 GAP GA4 GND 3.3v_AUX GND SM0 SM1

6 GA3 GA2 GND +12v_AUX(NC)

GND GA1 GA0

7 TCK GND TD0 TDI GND TMS TRST

8 GND REF_CLK- REF_CLK+ GND RES_BUS- (NC)

RES_BUS+ (NC)

GND

PCI express


41

VPXP1 Connector The VPXP1 connector supplies four lanes of PCI express data and user I/O from ECMs from/to the backplane.

Connector VPXP1 is connected to two ECM sites, E0...E15 and F0.F15, for a total of 32 user I/Os.


1 VPX0_DEF GND RXD1 RXD0 GND TXD1 TXD0

2 GND RXD3 RXD2 GND TXD3 TXD2 GND

3 VPX0_DEF GND RXD5 RXD4 GND TXD5 TXD4

4 GND RXD7 RXD6 GND TXD7 TXD6 GND

5 VPX0_DEF GND (NC) (NC) GND (NC) (NC)

6 GND (NC) (NC) GND (NC) (NC) GND

7 VPX0_DEF GND (NC) (NC) GND (NC) (NC)

8 GND (NC) (NC) GND (NC) (NC) GND

9 SE4 GND E3 E2 GND E1 E0

10 GND E7 E6 GND E5 E4 GND

11 SE5 GND E11 E10 GND E9 E8

12 GND E15 E14 GND E13 E12 GND

13 SE6 GND F3 F2 GND F1 F0

14 GND F7 F6 GND F5 F4 GND

15 SE7 GND F11 F10 GND F9 F8

16 GND F15 F14 GND F13 F12 GND

(NC) no connect, PCI express (as refereced in schematics), ECM I/O


42

VPXP2 Connector The VPXP2 connector supplies four lanes of PCI express data and user I/O from ECMs from/to the backplane.

Connector VPXP2 is connected to four ECM sites, A0...A15, B0...B15, C0...C15 and D0...D15, for a total of 64 user I/Os.


1 SE0 GND A3 A2 GND A1 A0

2 GND A7 A6 GND A5 A4 GND

3 SE1 GND A11 A10 GND A9 A8

4 GND A15 A14 GND A13 A12 GND

5 SE2 GND B3 B2 GND B1 B0

6 GND B7 B6 GND B5 B4 GND

7 SE3 GND B11 B10 GND B9 B8

8 GND B15 B14 GND B13 B12 GND

9 SE4 GND C3 C2 GND C1 C0

10 GND C7 C6 GND C5 C4 GND

11 SE5 GND C11 C10 GND C9 C8

12 GND C15 C14 GND C13 C12 GND

13 SE6 SDA GND D3 D2 GND D1 D0

14 GND D7 D6 GND D5 D4 GND

15 SE6 SCK GND D11 D10 GND D9 D8

16 GND D15 D14 GND D13 D12 GND

ECM I/O


43

VPXP0, Connector to Backplane RP0 pin mapping VPXP0 example mapping for a power wafer.

The mapping of pins and signals between the 8010/8011 and the backplane can cause confusion, the SEVEN rows on the VPXECM six somehow become NINE rows on the backplane.

The key to understanding the mapping is that the wafers on the connector are just small PCBs which can be routed however desired.

For the example wafer shown in cross-section, there are 2 voltages and a no-connect.

One advantage of this scheme is that it creates more voltage and ground connections on the backplane side.

Figure 19 Mapping pins VPXP2, on the left, to the backplane, VPXJ2 on the right.

Plug in card Row A Row B Row C Row D Row E Row F Row G

Pin GND Pair Pair GND Pair Pair GND

Backplane Row A Row B Row C Row D Row E Row F Row G Row H Row I

Wafer 1

Pin 1

GND GND Pair Pair GND GND Pair Pair GND


44

Table 8 Table showing signal names for the above drawing.

Figure 20 frontal view of the VPX connectors, note the empty wafer location shown in RED

Figure 21 Mapping between the 7 press fit pins on wafer 1 and the 9 edge finger connections on wafer 1.


45

Figure 22 overview of Wafer locations for the 8010/8011.

VPX Connector Keying

The keying guides on the 8010/8011 are of the unkeyed or universal type allowing it to plug into any backplane slot.

In the drawing a 90 degree keyed guide is shown for comparison, calling out the keying feature with a red arrow.

Misc. VPX signals VPX I2C / IPMI support

This VPX provides 2 I2C / IPMI buses on VPXP0 The FRU records and sensor records are readable by the host processor via IPMI commands. The IPMI commands are defined in VITA 46.11

For hardware definition storage the PIC uC stores the FRU information and the sensor data records.

The VPX signals used for this EEPROM include the following.


46

MVMRO is an active high memory protection signal set by the host processor which prevents writing the FRU or sensor data records.

Ga0…GA4 are signals set by the backplane which determine which range of addresses on the I2C bus the IPMC should respond to.

VPX JTAG support

TRSTTMSTCKTDITDO

VPXPOConnector

There are no on board JTAG devices on this VPX accessible with the VPXP0 JTAG signals, the JTAG data in and data out are connected together however.


47


Backplane and RTM

Backplane considerations The backplane should be compatible with a VITA 65 OpenVPX SLT3-PER-1F-14.3.2 profile.

Warning: Because of voltage incompatibilities this module can only be used in 3U backplanes, it is not electrically compatible with 6U backplanes.

One reason for this is that for 3U backplanes VS1 is +12V while for 6U backplanes it is +12V/48V.

An additional reason is that for 3U backplanes VS2 is +3.3V while for 6U backplanes it is +12VD/48V_RTN.

PLUGGING THE 8010/8011 into a 6U VPX backplane will destroy the board.


48

Rear Transition module considerations Using 8010/8011 may require a custom RTM with connectors as required by the system wiring.

ECM Site A

ECM Site B

ECM Site C

ECM Site D

VPX Backplane


ECM Site E

ECM Site F


SSRSwitches

SSRSwitches

SSRSwitches

SSRSwitches

SSRSwitches

SSRSwitches

6 Isolation EnablesControlled by FPGA

16

VPX P0

RTM RP0

RTM RP1

RTM RP2


I/OConnector

OrConnectors

On RTM


IPMI-A PIC uC

VPXECM6 Rear transition module

IPMI-B

16

16

16

16

16

IPMI-RTM

IPMI-RTM FRU EEPROM

16

16

16

16

16

16

0 ohm

Figure 23 block diagram of RTM signals

The IPMI-RTM signals are connected with zero ohm resistors, in case these signals are incompatible with some RTMs.

Note that Rear Transition modules are not the only way to access ECM I/O, cabling which attached directly to the backplane, custom backplanes with cable connectors and single slot backplanes can also aid in accessing ECM I/O.


49

Figure 24 overview of the wafers and pins on a RTM, rear transition module.

When matching up the VPX plug in card with the corresponding RTM, note that P0 and RP0 are colored light blue in these two drawing, but they are different sized connector so they do not correspond in a one to one fashion. This is also true for (P1 and RP1) orange and (P2 and RP2) light purple.

Figure 25 Corresponding view of Wafer locations and identification scheme for a VPX plug in card.


50

Power Overview

Figure 26 Power supply architecture

Abaco Systems P/N 8004 requires +3.3V, +3.3V Aux, +5V, +12V, -12VAux and Ground from the VPX backplane.

Some combination of +3.3V, +5V, +12V and -12V Aux is also required by the ECMs. These voltages are supplied by the VPX J0 connector. Since -12V Aux is optional as per the VPX standard it may need to be added if any of the ECMs need it. The ECMs do not use +3.3V Aux.

+12Vaux is not used.

Ground supplied all three of the VPX connectors and is common throughout the board.

The FPGA and core voltages are generated by DC/DC converters which are powered off the +3.3V power rail.

There is no power sequencing circuitry.

Safety ground is implemented as a border around the active components on the top and bottom of the PCB it connects to the front panel as well as the backplane. Note that Safety ground is isolated from board voltages and signal ground.

For the conduction cooled version of the board safety ground connects to the heat frame and also the 12 ECM standoffs.

The Safety ground also connects to the twelve ECM standoffs when a thermal frame is applied to the 8010/8011 board. For the air cooled board it does not connect to Safety ground.


51


Installation

VITA48.1 air cooled Installation Seat the VPX into the backplane connectors, and then tighten the front panel screws.

VITA48.2 4HP or 5HP conduction cooled Installation Seat the VPX into the backplane connectors, and then tighten the wedge lock screws. Turn the allen screw clockwise to tighten and counter clockwise to loosen. Use a 3/32” hex key.

Installation and Handling Warnings Static precautions are mandatory in handling this assembly. Use a conductive wrist strap and handle the

card in a static-free environment. Avoid touching components on the VPX module. When transporting the

board use the ESD protective bag it was shipped in or other protective wrapping.

Adequate filtered cooling is needed to prevent the temperature of the VPX from exceeding the specification

and dust accumulation.


52

Appendix A Typical applications

A Abaco Systems VPX six ECM carrier is mounted on a Abaco Systems P/N 8065 VPX to PCI express adapter allowing testing and debug of the VPX board in a PC chassis with access headers for the rear I/O signals. Note the blue push on jumpers are intended for loop back testing.


53

Appendix B Ordering information

1) Choose SSR or zero ohm I/O base board.

ECM carrier with 50K logic elements FPGA, SSR I/O. P/N 8010 ECM carrier with 50K logic elements FPGA, zero ohm I/O. P/N 8011

2) Choose cooling style.

Hardware Kit for VITA48.2 conduction cooled 5HP version, top & bottom covers. P/N 8284 Hardware Kit for VITA48.2 conduction cooled 4HP version, top cover. P/N 8228 Hardware Kit for VITA48.1 air cooled version. P/N 8227

3) Choose from zero to six ECMs. A few of the P/Ns are listed below, there are many others.

RS232 ECM. P/N 3508 8 channel digital I/O ECM. P/N 3512 RS422/RS485 ECM. P/N 5041

4) Choose FPGA design, this is the example design.

5) Select the guides to match the backplane if this is not specified the unkeyed will be supplied.

6) Choose custom options, see below.

7) Get a custom orderable P/N from Abaco Systems, based on choices 1 thru. 6.

Custom part numbers derived from the base design.

Custom part numbers derived from the baseline design are possible, however order minimums, longer lead times and higher prices may apply. Call Abaco Systems for help in choosing and ordering your specific options and to get an orderable part number. Options include.

• Conformal coating, many customers order Acrylic conformal coating.

• Higher density FPGAs can be substituted.

• For other customer requirements please contact Abaco Systems.


54

APPENDIX C Printed circuit placement

Figure 27 Printed Circuit Placement – side 1

Figure 28 Printed Circuit Placement – side 2


55

APPENDIX D relevant schematics

The first schematic page, “ROOT”, contains the connections between the individual detailed schematic sheets.

The second schematic page “FPGA”, Contains the main body of the FPGA along with support chips and the PCI express interface on the FPGA.

The next six schematic pages contain the FPGA data connections to the ECM sites and the I/O circuitry and I/O connector for ECM Sites A, B, C and D.

The next three schematic pages contain the FPGA data connections to the ECM sites and the I/O circuitry and I/O connector for ECM Sites E and F.

Note that because of the large number of balls and distributed nature of the FPGA control it has been broken up into multiple schematic symbols.


56

ROOT SCHEMATIC


57

FPGA, PCIe interface, misc. external circuits associated with the FPGA.


58

FPGA, center part, connections to two ECM sites A and B, the connections to I/O are via the next two schematics.

.


59

SITE A SSR or zero ohms I/O control, this page connects the ECM I/O to the backplane connector.


60

SITE B SSR or zero ohms I/O control, this page connects the ECM I/O to the backplane connector.


61

FPGA, center part, connections to two ECM sites C and D, the connections to I/O are via the next two schematics.


62

SITE C SSR or zero ohms I/O control, this page connects the ECM I/O to the backplane connector.


63

SITE D SSR or zero ohms I/O control, this page connects the ECM I/O to the backplane connector.


64

VPXP2, ECM I/O for SITES A, B, C and D, also IPMI for RTM.


65

FPGA, center part, connections to two ECM sites E and F, the connections to I/O are via the next two schematics.


66

SITE E SSR or zero ohms I/O control, this page connects the ECM I/O to the backplane connector.


67

SITE F SSR or zero ohms I/O control, this page connects the ECM I/O to the backplane connector.


68

VPXP1, ECM I/O for SITES E and F, also four lanes of PCI express.


69


Appendix E Mechanical

VITA 48.1 configuration The VITA 48.1 configuration allows the use of the 8010/8011 in an air-cooled chassis, it uses two aluminum rails to help guide the module and provide a conductive path from safety ground on the board to the chassis.

Figure 29 Two metal rails and front panel for VITA 48 configuration.

VITA 48.2, 4HP and 5HP configuration

Figure 30 Top Cover and two spacers for 4HP configuration.

Note the eight mounting screws for spacers.


70

Figure 31 Top Cover and bottom cover for VITA 48 5HP configuration.

Note the back cover replaces the spacers reusing the eight mounting screws.