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High-level Synthesis
Motivation for high-level synthesisDomains of the HW designLevels of abstractionsOverview on synthesis methodsHigh-level synthesis tasks and modelsASAP and ALAPList schedulingAdvanced Issues
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Integrated HW/SW-Systems 2Andreas Mitschele-Thiel 3-Dec-09
Motivation for High-level Synthesis
Complexity problem: millions of transistors on a single chip=> handcrafting of each single transistor is not possible=> handcrafting of single gates is not possible=> cost and time of the process require to do it right the first time=> need design automation on more abstract levels
=> high-level synthesis
algorithm synthesis
HW/SW (system)synthesis
Design automation ensures:speed-up the design processdo it right the first time
=> time-to-market
Integrated HW/SW-Systems 3Andreas Mitschele-Thiel 3-Dec-09
Domains of HW Design
Y chart: design domains and abstraction levels
structural domain behavioral domain
physical domain (layout)
=1A
BY
t = 5 ns
layo
ut P
ower
PC 7
50
EXOR: process (A, B)begin
Y <= transport A xor B after 5 ns;end process;
abstractionlevels
Integrated HW/SW-Systems 4Andreas Mitschele-Thiel 3-Dec-09
Abstraction Levels
structural domain behavioral domain
physical domain (layout)
transistor layout
cells
chips
boards
CFG, algorithmsregister transfers
Boolean expressionstransistor functions
gates, flip-flopstransistors
registers, ALUs, MUXs
processors, memories, buses
Integrated HW/SW-Systems 5Andreas Mitschele-Thiel 3-Dec-09
Structural Synthesis
Structural synthesis is the translation from a behavioral description into a structural description
structural domain behavioral domain
physical domain (layout)
transistor layout
cells
chips
boards
CFG, algorithmsregister transfers
Boolean expressionstransistor functions
gates, flip-flopstransistors
registers, ALUs, MUXs
processors, memories, buses
high-level synthesis
register-transfer synthesis
logic synthesis
circuit synthesis
Integrated HW/SW-Systems 6Andreas Mitschele-Thiel 3-Dec-09
Circuit Synthesis
generates a transistor schematic from a set of input-output current, voltage and frequency characteristics or equationstransistor schematic contains transistor types, parameters and sizes
structural domainbehavioral domain
physical domain (layout)
transistor layout
cells
chips
boards
CFG, algorithmsregister transfers
Boolean expressionstransistor functionstransistors
registers, ALUs, MUXs
processors, memories, buses
high-level synthesis
register-transfer synthesis
logic synthesis
circuit synthesis
gates, flip-flops
Integrated HW/SW-Systems 7Andreas Mitschele-Thiel 3-Dec-09
Logic Synthesis
structural domainbehavioral domain
physical domain (layout)
transistor layout
cells
chips
boards
CFG, algorithmsregister transfers
Boolean expressionstransistor functionstransistors
registers, ALUs, MUXs
processors, memories, buses
high-level synthesis
register-transfer synthesis
logic synthesis
circuit synthesis
gates, flip-flops
translation of Boolean expressions into a netlist of components from a given library of logic gates such as NAND, NOR, EXOR, etc.
-> see logic synthesis section for details
Integrated HW/SW-Systems 8Andreas Mitschele-Thiel 3-Dec-09
Register-transfer Synthesis
structural domainbehavioral domain
physical domain (layout)
transistor layout
cells
chips
boards
CFG, algorithmsregister transfers
Boolean expressionstransistor functionstransistors
high-level synthesis
register-transfer synthesis
logic synthesis
circuit synthesis
gates, flip-flops
start with a set of states and a set of register-transfers in each stateone state typically corresponds to a clock cycle (clock-accurate description)register-transfer synthesis generates the corresponding structures in two parts
registers, ALUs, MUXs
processors, memories, buses
(a) a data path which is a structure of storage elements and functional units that perform the given register transfers, and
(b) a control unit that controls the sequencing of the states in the register-transfer description
Integrated HW/SW-Systems 9Andreas Mitschele-Thiel 3-Dec-09
High-level Synthesis
structural domainbehavioral domain
physical domain (layout)
transistor layout
cells
chips
boards
CFG, algorithmsregister transfers
Boolean expressionstransistor functionstransistors
registers, ALUs, MUXs
processors, memories, buses
high-level synthesis
register-transfer synthesis
logic synthesis
circuit synthesis
gates, flip-flops
High-level synthesis (also called system synthesis or algorithmic synthesis) may cover HW as well as SW parts of the systemstarts with a set of processes communicating through either shared variables or message passing (an un-clocked description)generates a structure of processors, memories, controllers and interface adapters from a set of system componentseach component can be described by a register-transfer description
Integrated HW/SW-Systems 10Andreas Mitschele-Thiel 3-Dec-09
Levels of Synthesis
Integrated HW/SW-Systems 11Andreas Mitschele-Thiel 3-Dec-09
High-level Synthesis – Central Tasks
High-level synthesis deals with the algorithmic level (behavioral viewpoint)the system level (structural viewpoint)
Tasks of high-level synthesis(system) partitioning
partitioning of a behavioral description or design structure into subdescriptions or substructuresreduce the problem sizesatisfy external constraints as chip size, pins per package, power dissipation or wire length
allocationselection of the number and types of structural entities
mapping (Gajski: allocation, Teich: Bindung)assignment of data to storage units (registers)assignment of operations to functional units (ALUs, etc.)assignment of communications to busses or links
scheduling (Teich: Ablaufplanung)temporal assignment of data and operationsderivation of controller (microprogram)
mappin
g an
d sc
hedu
ling
are
highly
interd
epen
dent
Integrated HW/SW-Systems 12Andreas Mitschele-Thiel 3-Dec-09
High-level Synthesis: Theory
Behavioral model:
GS = (VS, ES) is a directed acyclic graph where
each node vS ∈ Vs represents a task and
each arc eT = (vi, vj) ∈ ES defines a data dependency (execute vi before vj)
Resource model:
GR = (VR, ER) is a bipartite graph with
VR = (VS ∪ VT) where
VS specifies the nodes of the behavioral model
VT specifies the nodes representing resource types
(vS, vT) ∈ ER with vS ∈ Vs and vT ∈ VT specifies that vS may be implemented
by a resource node of type vT
the cost function c denoting the cost of each instance of node type vT and
the node execution time t denoting the latency of the execution of task vS on
a resource of type vT
Integrated HW/SW-Systems 13Andreas Mitschele-Thiel 3-Dec-09
Summary of Basic Concepts of Models and Languages
State transitionsevents triggering a state transition (simple input, complex conditions)computation associated with transition
Concurrencydecomposition of behavior in concurrent entities different levels of concurrency (job, task-, statement-, operation-level)data-driven (data dependencies) vs control-driven concurrency (control dependencies)reduction of states
Hierarchystructural hierarchy (system, block, process, procedure)behavioral hierarchy (hierarchical transitions, fork-join)
Programming constructsspecify sequential algorithm
Communicationshared variables (broadcast)message passingsynchronous vs. asynchronous
Synchronizationcontrol-dependent (fork-join)data-dependent (data, event, message)
Exception handlingimmediate termination of current behaviror
Non-determinismchoice between multiple transitionsnon-deterministic ordering
Timingtimeoutstime constraints (e.g. exec. time)
Integrated HW/SW-Systems 14Andreas Mitschele-Thiel 3-Dec-09
Control vs. Data Flow Applications
Rough classification:control:
don’t know when data arrive (quick reaction)time of arrival often matters more than value
data:data arrive in regular streams (samples)values matter most
Distinction is important for:specification (language, model, ...)synthesis (scheduling, optimization, ...)validation (simulation, formal verification, ...)
Specification, synthesis and validation methods emphasize:
for control:event/reaction relationresponse time (real-time scheduling for deadline satisfaction)priority among events and processes
for data:functional dependency between input and outputmemory/time efficiency (data-flow scheduling for efficient pipelining)all events and processes are equal
Integrated HW/SW-Systems 15Andreas Mitschele-Thiel 3-Dec-09
Control/Data Flow Graph (CDFG)
also called sequence graphmixture of control and data flow graphhierarchy of sequential elements
units model data flowhierarchy models control flow
special nodes (for control operations)start/end node: NOP (no operation) – all inputs needed (AND), all outputs needed (AND)branch node (BR) – one out of many outputs selected (OR)iteration (LOOP) – one out of two outputs selected (OR)procedure call (CALL) – lower hierarchy is executed exactly once
attributesnodes: execution time, cost, ...arcs: conditions for branches and loops
Integrated HW/SW-Systems 16Andreas Mitschele-Thiel 3-Dec-09
StateCharts – AND Decomposition
V,W
V.YV,Z
V
W
X
X,Y
X,W
X.Z
R
Q
Z
Y
U
RQ
S Tk
e
e
e
kTo be in state U the system must be both in states S and T
Integrated HW/SW-Systems 17Andreas Mitschele-Thiel 3-Dec-09
StateCharts – OR Decomposition
S
V
T
S
V
T
f
f
f
e
h
e
h
g g
To be in state U the system mustbe either in state S or in state T
U
State U is an abstraction of states S and T
Integrated HW/SW-Systems 18Andreas Mitschele-Thiel 3-Dec-09
Asynchronous Communication – Buffering
Buffers used to adapt when sender and receiver have different ratesize of buffer?
Lossless vs. lossyevents/tokens may be lostbounded memory: overflow or overwritingneed to block the sender
Single vs. multiple readresult of each write can be read at most once or several times
Pure FIFOprioritized eventsout of order access to FIFO
A B
Integrated HW/SW-Systems 19Andreas Mitschele-Thiel 3-Dec-09
DFG – Example
Integrated HW/SW-Systems 20Andreas Mitschele-Thiel 3-Dec-09
CDFG – Loop
Integrated HW/SW-Systems 21Andreas Mitschele-Thiel 3-Dec-09
Review of Models, Concepts and Languages
Behavioral ModelsFinite State Machine (FSM)NDFSMcomposed FSMPetri Net (PN)Data Flow Graph (DFG)Control Flow Graph (CFG)Control/Data Flow Graph (CDFG)
Behavioral ModelsFinite State Machine (FSM)NDFSMcomposed FSMPetri Net (PN)Data Flow Graph (DFG)Control Flow Graph (CFG)Control/Data Flow Graph (CDFG) Specification Languages
StateChartsSDLVHDLSystemC...
Specification LanguagesStateChartsSDLVHDLSystemC...
Basic Conceptsconcurrencyhierarchycommunicationsynchronisationexception handlingnon-determinism timing
Basic Conceptsconcurrencyhierarchycommunicationsynchronisationexception handlingnon-determinism timing
Integrated HW/SW-Systems 22Andreas Mitschele-Thiel 3-Dec-09
Data Flow Graph (DFG)
Powerful formalism for data-dominated applications
DFG support the specification of transformational systems:output is a function of the inputset of actors (nodes) connected by a set of arcs representing the data flowno states, no external events to trigger state changesunbounded FIFO queues (main data store)no control nodes, e.g. branch, loop
DFG represent a partial ordered model of the computation=> specification of problem-inherent dependencies only=> suitable for scheduling and code generation=> there is a relation between buffer dimensioning and scheduling
(static scheduling minimizes the number of buffers required)
Languages:graphical: Ptolemy (UCB), GRAPE (U. Leuven), SPW (Cadence), COSSAP (Synopsys)textual: Silage (UCB, Mentor), Haskell, Lucid
Integrated HW/SW-Systems 23Andreas Mitschele-Thiel 3-Dec-09
High-level Synthesis: Example
Behavioral model:
* *
*
*
+ <*
-
-
* +1 2 6 8 10
4
3 7 9 11
5
data dependency
Resource model:
*
*
*
*
*
*
--
++
<
1
3
7
2
6
8
4
9
11
5
10
multiplier
ALU
may be implemented
on
Note: behavior model does not define clocking (different from RT synthesis)
Integrated HW/SW-Systems 24Andreas Mitschele-Thiel 3-Dec-09
High-level Synthesis: Example
Scheduling with unlimited resources:
=> latency 4 T
* *
*
*
+ <*
-
-
* +1 2 6 8 10
4
3 7 9 11
5
t0
t1
t2
t3
t4
Integrated HW/SW-Systems 25Andreas Mitschele-Thiel 3-Dec-09
High-level Synthesis: Example
Mapping and scheduling with limited resources:
4 multipliers
2 ALUs
=> latency 4 T
* *
*
*
+ <*
-
-
* +1 2 6 8 10
4
3 7 9 11
5
t0
t1
t2
t3
t4
Integrated HW/SW-Systems 26Andreas Mitschele-Thiel 3-Dec-09
High-level Synthesis: Example
Mapping and scheduling with limited resources:
1 multiplier
1 ALU
=> latency 7 T
* 1
* 2
* 6
* 8
+10
-4
* 3
* 7
+9
<11
-5
t0
t1
t2
t3
t4
t5
t6
t7
Integrated HW/SW-Systems 27Andreas Mitschele-Thiel 3-Dec-09
ASAP Scheduling without Resource ConstraintsASAP (as soon as possible) scheduling without resource constraints:
algorithm: for each time slot select node which has all predecessors assigned
problem is solvable in polynomial time
* * * * +1 2 6 8 10
-4
* + <*3 7 9 11
-5
t0
t1
t2
t3
t4
assign all nodes without predecessors
assign nodes with scheduled predecessors
dito
dito
Integrated HW/SW-Systems 28Andreas Mitschele-Thiel 3-Dec-09
ALAP Scheduling without Resource Constraints
ALAP (as late as possible) scheduling without resource constraints:
algorithm: complementary to ASAP; start with nodes without successors
problem is solvable in polynomial time
* *1 2
* 6* 3
- * +8 104 * 7
+ <- 9 115
t0
t1
t2
t3
t4
dito
dito
assign nodes with scheduled successor
assign all nodes without sucessor
Integrated HW/SW-Systems 29Andreas Mitschele-Thiel 3-Dec-09
Scheduling with Resource Constraints: ASAP Extension
Extensions to ASAP and ALAP, respectivelycompute schedule using ASAP (or ALAP)if a resource constraint is violated, move respective nodes
Example: extended ASAP (2 multiplier, 2 ALUs)
* * +1 2 10
-4
* <3 11
-5
t0
t1
t2
t3
t4
* 8
+9
*
6*
7
* 8
+9
*
6*
7
Integrated HW/SW-Systems 30Andreas Mitschele-Thiel 3-Dec-09
Scheduling with Resource Constraints: List Scheduling
Apply global criteria to optimize the schedulederive priority for each node based on
length of path to sink/source orlaxity of node (i.e. the difference between start according to ASAP and ALAP) ornumber of successor nodes (fanout)
Example: 1 multiplier, 1 ALU
Priority assignment (according to length to sink):
* 1+
10
* 6-
4
* 7
+9
* 2<
11
* 8-
5
t0
t1
t2
t3
t4
t5
t6
t7
* 3
* *
*
*
+ <*
-
-
* +1 2 6 8 10
4
3 7 9 11
51
2
1 1
22
23
344
Integrated HW/SW-Systems 31Andreas Mitschele-Thiel 3-Dec-09
Scheduling with Resource Constraints: List Scheduling
Example: 2 combined multiplier/ALU units
2 time units for multiplication1 time unit for ALU operation
Priority assignment (length to sink):
* *
*
*
+ <*
-
-
* +1 2 6 8 10
4
3 7 9 11
51
2
1 1
23
34
566
* 1 * 2
* 6
* 8
+10
-4
* 7
t0
t1
t2
t3
t4
t5
t6
t7
* 3
t8
t9
+9
<11
-5
Integrated HW/SW-Systems 32Andreas Mitschele-Thiel 3-Dec-09
Advanced Topics of High-level Synthesis
Considered so far:mapping and scheduling without resources constraintsmapping and scheduling with given number (and type) of resources
Advanced topics:mapping and scheduling with time constraints and open number of resourcesmapping and scheduling of periodic tasksmapping and scheduling in the presence of multiple resources with identical functionality but different area-latency relations...
The general mapping and scheduling problem is NP hard (optimal solution is not computable in polynomial time)
Numerous heuristic optimization algorithms have been applied to the problem
Integrated HW/SW-Systems 33Andreas Mitschele-Thiel 3-Dec-09
References
D. Gajski, N. Dutt, A. Wu, S. Lin: High-level Synthesis – Introduction to Chip and System Design. Kluwer Academic Publishers, 1992.Bleck, Goedecke, Huss, Waldschmidt: Praktikum des modernen VLSI-Entwurfs. B.G. Teubner, 1996J. Teich: Digitale Hardware/Software Systeme. Springer, 1997.