Embed Size (px)
Citation preview
TDI-CCD image sensors
Hybrid structure combining TDI-CCD and CMOS readout circuit
S14810 S14813
1www.hamamatsu.com
These image sensors combine a TDI-CCD, which can ensure adequate brightness for images even during high speed imaging, with a CMOS readout circuit for digital output. The S14813 (back-thinned type) has higher sensitivity than the S14810 (front-illuminated type) in the ultraviolet to visible region, ensuring clear images even at low illuminance.
StructureParameter Specification
Pixel size (H × V) 12 × 12 μmTotal number of pixels (H × V) 1024 × 132Number of effective pixels (H × V) 1024 × 128Image size (H × V) 12.288 × 1.536 mmFill factor 100%Number of TDI stages 128Anti-blooming FW × 100 min.Vertical clock 2-phase (bidirectional)Output circuit 10-bit A/D converterPackage 320-pin ceramic (see dimensional outlines)
Window material S14810 Borosilicate glass*1S14813 Quartz glass*1
Cooling Non-cooled*1: Resin sealingNote: This product is not hermetically sealed, and therefore moisture may penetrate into the package. Storing or using the product
in a place with sudden temperature or humidity changes may cause condensation to form inside the package, so avoid such environments.
Features
Sensors combining TDI-CCD and CMOS readout circuit 10-bit digital output High-speed line rate: 100 kHz max. High UV resistance (S14813) Low noise: 12 e- rms typ. (S14813)
8 e- rms typ. (S14810) Bidirectional transfer
Applications
Continuous imaging of high-speed moving objects Machine vision
TDI-CCD image sensors S14810, S14813
2
Absolute maximum ratings (Ta=25 °C unless otherwise noted)Parameter Symbol Min. Typ. Max. Unit
Operating temperature*2 Topr 0 - 60 °CStorage temperature Tstr -40 - 70 °COutput transistor drain voltage VOD -10 - 9.5 VReset drain voltage VRD -10 - 7.5 VOverflow drain voltage VOFD -10 - 7.5 VOverflow gate voltage VOFG -20.5 - 7.5 VSumming gate voltage VSG -20.5 - 4.5 VReset gate voltage VRG -20.5 - 4.5 VOutput gate voltage VOG -20.5 - 4.5 VVertical clock voltage VPXV -20.5 - 4.5 VCCD ground voltage VAGND -11.5 - -9.5 V
ROIC supply voltageAnalog terminal Vdd(A) -0.3 - 3.9
VDigital terminal Vdd(D) -0.3 - 3.9Counter terminal Vdd(C) -0.3 - 3.9
ROIC digital input terminal voltage*3 Vi -0.3 - 3.9 VSoldering conditions*4 Tsol 260 °C, within 5 s, at least 2 mm away from lead roots -*2: Package temperature*3: SPI_CS, SPI_SCLK, SPI_MOSI, SPI_RSTB, CLK, TG_reset, PLL_reset*4: Use a soldering iron.Note: Exceeding the absolute maximum ratings even momentarily may cause a drop in product quality. Always be sure to use the product
within the absolute maximum ratings.
Operating condition (TDI mode, Ta=25 °C)Parameter Symbol Min. Typ. Max. Unit
Output transistor drain voltage VOD 2.5 4.5 6.5 V
Reset drain voltage S14810 VRD-0.5 1.5 3.5 VS14813 -1.5 0.5 2.5
Overflow drain voltage VOFD -0.5 1.5 3.5 VOverflow gate voltage VOFG -7.5 -5.5 -3.5 VOutput gate voltage VOG -7.5 -5.5 -3.5 V
Summing gate voltage VSGH -5.5 -3.5 -1.5 VVSGL -15.5 -13.5 -11.5
Reset gate voltage VRGH -3.5 -1.5 0.5 VVRGL -13.5 -11.5 -9.5
Vertical clock voltage VPXVH -5.5 -3.5 -1.5 VVPXVL -15.5 -13.5 -11.5CCD ground voltage VAGND - -10.5 - V
ROIC supply voltageAnalog terminal Vdd(A) 3.2 3.3 3.45
VDigital terminal Vdd(D) 3.2 Vdd(A) 3.45Counter terminal Vdd(C) 2.6 2.7 2.9
ROIC digital input terminal voltage*5 ViH Vdd(D) - 0.25 Vdd(D) Vdd(D) + 0.25 VViL 0 - 0.25*5: SPI_CS, SPI_SCLK, SPI_MOSI, SPI_RSTB, CLK, TG_reset, PLL_reset
TDI-CCD image sensors S14810, S14813
3
Digital input
Electrical characteristics
[Ta=25 °C, Typ. values in operating conditions table (P.2), unless otherwise noted]Parameter Symbol Min. Typ. Max. Unit
Master clock pulse frequency f(CLK) 25 30 35 MHzMaster clock pulse duty ratio D(CLK) 45 50 55 %
Digital input signal Rise time*6 *7 tr(sigi) - 5 7 nsFall time*6 *7 tf(sigi) - 5 7*6: SPI_CS, SPI_SCLK, SPI_MOSI, SPI_RSTB, CLK, TG_reset, PLL_reset*7: Time for the input voltage to rise or fall between 10% and 90%
Digital output[Ta=25 °C, Typ. values in operating conditions table (P.2), unless otherwise noted]
Parameter Symbol Min. Typ. Max. UnitData rate DR f(CLK) × 8 MHzPixel sync signal (PCLK) frequency f(PCLK) f(CLK) × 4 MHz
Digital output voltage (LVDS output)
Offset Vofs 1.13 1.25 1.38 VDifferential Vdiff 0.25 0.35 0.45 VRise time*8 *9 tr(out) - 2 3 nsFall time*8 *9 tf(out) - 2 3 ns
*8: Out_A to H, Vsync, Hsync, PCLK, CTR*9: Time for the output voltage to rise or fall between 10% and 90% when there is a 2 pF load capacitor attached to the output terminal
CCD[Ta=25 °C, Typ. values in operating conditions table (P.2), unless otherwise noted]
Parameter Symbol Min. Typ. Max. UnitLine rate LR - 100 100 kHzVertical shift register capacitance CPXV - 1200 - pFSumming gate capacitance CSG - 40 - pFReset gate capacitance CRG - 40 - pFCharge transfer efficiency CTE 0.99995 0.99999 - -
Current consumption
Parameter Symbol S14810 S14813 UnitMin. Typ. Max. Min. Typ. Max.Current consumption
Analog and digital terminal*10 I1 - 430 600 - 430 600 mACounter terminal*11 I2 - 250 350 - 230 350*10: Total value of 2 ROICs*11: Saturated
A/D converter
Parameter Symbol Specification UnitResolution RESO 10 bit
A/D resolution High*12 - 0.17 mV/DNLow*13 - 1.67*12: Gain=10x*13: Gain=1x
TDI-CCD image sensors S14810, S14813
4
Electrical and optical characteristics[Ta=25 °C, Typ. values in operating conditions table (P.2), unless otherwise noted]
Parameter Symbol S14810 S14813 UnitMin. Typ. Max. Min. Typ. Max.Spectral response range λ 400 to 1100 200 to 1100 nm
Conversion efficiency
Low*14
-
- 25 - - 15 - μV/e-Low*14 - 0.015 - - 0.009 - DN/e-High*15 - 250 - - 150 - μV/e-High*15 - 0.15 - - 0.09 - DN/e-
Full well capacity FW 40 45 - 65 75 - ke-
Saturation output Low*14Vsat 600 675 - 585 675 - DNHigh*15 600 675 - 480 550 -
Saturation output voltage Vsat - FW × Sv - - FW × Sv - VPhotoresponse nonuniformity*16 PRNU - ±3 ±10 - ±3 ±10 %Dark current*17 DS - 10 15 - 10 15 ke-/pixel/s
Dark output Low*14DSD - 150 - - 150 - DN/sHigh*15 - 1500 - - 1500 -
Readout noise Low*14Nread - 30 50 - 40 80 e- rmsHigh*15 - 8 15 - 12 20
Random noise Low*14RN - 0.45 0.75 - 0.36 0.72 DN rmsHigh*15 - 1.2 2.25 - 1.08 1.80
Dynamic rangeLow*14
Drange800 1500 - 812 1875 -
-High*15 267 563 - 325 625 -*18 3333 5630 - 3250 6250 -
Offset output Low*14Vo 0 200 300 0 210 300 DNHigh*15 0 200 300 0 320 400
Offset variation Low*14DSNU - 3 10 - 3 10 DN rmsHigh*15 - 3 15 - 7 15
*14: Gain=1x*15: Gain=10x*16: PRNU=∆X/X × 100 [%]
∆X: standard deviation of all effective pixel output, X: average output of all eff ective pixels*17: Dark current nearly doubles for every 5 to 7 °C increase in temperature.*18: Total where gain is 1x and 10x
TDI-CCD image sensors S14810, S14813
5
Spectral transmittance of window material
KMPDB0582EA
Wavelength (nm)
Tran
smitt
ance
(%)
200 400 600 800 1000 1200
100
90
80
70
60
50
40
30
20
10
0
S14810S14813
(Typ. Ta=25 °C)
Dark current vs. chip temperature
KMPDB0583EA
Chip temperature (°C)
Dark
cur
rent
(ke-
/pixe
l/s)
0 10 20 30 40 50 60
1000
100
10
1
0
(Typ.)
Spectral response (with window)
KMPDB0580EA
Wavelength (nm)Qu
antu
m e
fficie
ncy
(%)
200 400 600 800 1000 1200
100
90
80
70
60
50
40
30
20
10
0
S14810
S14813
(Typ. Ta=25 °C)
KMPDB0581EA
Wavelength (nm)
Phot
osen
sitiv
ity (A
/W)
200 400 600 800 1000 1200
0.6
0.5
0.4
0.3
0.2
0.1
0
(Typ. Ta=25 °C)
S14810
S14813
TDI-CCD image sensors S14810, S14813
6
B port
OS_b1 toOS_b128(L, H)
Out_H[2:0]_b
OS_b129 toOS_b256(L, H)
Out_G[2:0]_b
OS_b257 toOS_b384(L, H)
Out_F[2:0]_b
OS_b385 toOS_b512(L, H)
Out_E[2:0]_b
OS_b513 toOS_b640(L, H)
Out_D[2:0]_b
OS_b641 toOS_b768(L, H)
Out_C[2:0]_b
OS_b769 toOS_b896(L, H)
Out_B[2:0]_b
OS_b897 toOS_b1024(L, H)
Out_A[2:0]_b
OFDOFG
A.GND
SG_bP1VP2VP3VP4VSG_a
B portreadout1024 × 128 pixels
. . .
. . .
. . .OS_b
128
OS_b
2
OS_b
1
OS_b
1024
OS_b
1023
OS_b
897
OS_b
128(
L)OS
_b12
8(H)
OS_b
2(L)
OS_b
2(H)
OS_b
1(L)
OS_b
1(H)
OS_b
1024
(L)
OS_b
1024
(H)
OS_b
1023
(L)
OS_b
1023
(H)
OS_b
897(
L)OS
_b89
7(H)
. . .
. . .. . .
1st c
olum
n
1024
th c
olum
n
KMPDC0791EA
A port
OS_a1 toOS_a128(L, H)
Out_H[2:0]_a
Os_a129 toOS_a256(L, H)
Out_G[2:0]_a
Os_a257 toOS_a384(L, H)
Out_F[2:0]_a
OS_a385 toOS_a512(L, H)
Out_E[2:0]_a
Os_a513 toOS_a640(L, H)
Out_D[2:0]_a
Os_a641 toOS_a768(L, H)
Out_C[2:0]_a
Os_a769 toOS_a896(L, H)
Out_B[2:0]_a
Os_a897 toOS_a1024(L, H)
Out_A[2:0]_a
. . .
. . .
OS_a
1
OS_a
2
OS_a
128. . .
OS_a
1(H)
OS_a
1(L)
OS_a
2(H)
OS_a
2(L)
OS_a
128(
H)OS
_a12
8(L)
OS_a
897
OS_a
1023
OS_a
1024
OS_a
897(
H)OS
_a89
7(L)
OS_a
1023
(H)
OS_a
1023
(L)
OS_a
1024
(H)
OS_a
1024
(L)
. . .
. . . . . .
OFDOFG
A.GND
SG_bP1VP2VP3VP4VSG_a
A portreadout1024 × 128 pixels
1st c
olum
n
1024
th c
olum
n
KMPDC0790EA
Sensor structure
TDI-CCD image sensors S14810, S14813
7
CLK, TG_resetPLL_reset
SPI_SCLK_a, SPI_RSTB_aSPI_CS_a, SPI_MOSI_a
Vsync_aHsync_aCTR_aPCLK_a
OutA[2:0]_a to OutH[2:0]_a
24
Column parallel A/D converter
Column amplifier
Pixels
Horizontal shift register LVDS
out
put
Seria
lizer
SPI
Bias circuit
Timing generator
CLK, TG_resetPLL_reset
24
Column parallel A/D converter
Column amplifier
Horizontal shift register
LVDS
out
put
Seria
lizer
SPI
Timing generator
Bias circuit
SPI_SCLK_b, SPI_RSTB_bSPI_CS_b, SPI_MOSI_b
Vsync_bHsync_bCTR_bPCLK_b
OutA[2:0]_b to OutH[2:0]_b
ROIC
ROIC
KMPDC0792EA
Block diagram
TDI-CCD image sensors S14810, S14813
8
Timing chart
PCLK
Vsync
Hsync
CTR
Out_A[0]
Out_A[1]
Out_A[2]
Out_B[0]
Out_B[1]
Vsync
Hsync
Out_A[0]
Out_A[1]
Out_H[1]
Out_H[2]
Invalid data 1st pixel data 2nd pixel data 3rd pixel data
D1 D2 D3 D0 D1 D2D3 D0 D1 D2 D3 D0 D3 D0 D1 D2D3 D0 D1 D2 D3 D0 D3 D0 D1 D2 D3D1 D2 D3 D0 D1 D2D3 D0 D1 D2 D3 D0D1 D2
D7 D4 D5 D6 D7 D6 D7 D4 D5 D6 D7D4 D5 D6 D7 D4 D5 D6 D7 D4 D5 D6 D7D4 D5 D6 D7 D4 D5 D6 D7 D4 D5 D6 D7D4 D5 D6 D7 D4 D5
D9 D10 D11 D8 D9 D10D11 D8 D9 D10 D11 D8 D11 D8 D9 D10D11 D8 D9 D10 D11 D8 D11 D8 D9 D10 D11D9 D10 D11 D8 D9 D10D11 D8 D9 D10 D11 D8D9 D10
D3 D0 D1 D2 D3 D1 D2 D3D0 D1 D2 D3 D0 D1 D1 D2 D3D0 D1 D2 D3 D0 D1 D2 D3 D0D2 D3 D0 D1 D2 D3D0 D1 D2 D3 D0 D1D2 D3 D0
D7 D4 D5 D6 D7 D4 D7 D4 D5 D6 D7 D4D5 D6 D7 D4 D5 D6 D7 D4 D5 D6 D7 D4D5 D6 D7 D4 D5 D6 D7 D4 D5 D6 D7D5 D6 D7 D4 D5 D6
Valid data Invalid dataInvalid data Valid data Invalid data Valid data Invalid data
Valid data Invalid dataInvalid data Valid data Invalid data Valid data Invalid data
Valid data Invalid dataInvalid data Valid data Invalid data Valid data Invalid data
Valid data Invalid dataInvalid data Valid data Invalid data Valid data Invalid data
1st column data (256 pixels) 2nd column data (256 pixels)
......
KMPDC0793EA
TDI-CCD image sensors S14810, S14813
9
TDI mode
Output
Input. . . . . .
. . . . . .
. . . . . .
. . . . . .
. . . . . .
. . . . . .
. . . . . .
. . . . . .
tpwvs
tpwhs
tts
tpwr
tpwvPXV
PYV
RG_x
RG_y
SG_x
SG_y
Vref_x (open)
Vref_y
Vsync
Hsync
KMPDC0794EA
Readout port PXV PYVA P1V, P2V P3V, P4VB P2V, P3V P1V, P4V
Vertical clock phase
Readout port RG_x RG_y SG_x SG_y Vref_x Vref_yA RG_a RG_b SG_a SG_b Vref1_a, Vref3_a Vref1_b, Vref3_bB RG_b RG_a SG_b SG_a Vref1_b, Vref3_b Vref1_a, Vref3_a
RG, SG, Vref
Readout port A port SPI B port SPIA 0 199B 199 0
ADC_N [7:0], DO_N [7:0]
TDI-CCD image sensors S14810, S14813
10
Area scanning mode
Output
Input. . . . . .
. . . . . .
. . . . . .
. . . . . .
. . . . . .
. . . . . .
. . . . . .
. . . . . .
tpwvs
tpwhs
tts
tpwr
tpwvPXV
PYV
RG_x
RG_y
SG_x
SG_y
Vref_x (open)
Vref_y
Vsync
Hsync
Integration period(shutter open)
Transfer period(shutter closed)
KMPDC0795EA
Readout port PXV PYVA P1V, P2V P3V, P4VB P2V, P3V P1V, P4V
Vertical clock phase
Readout port RG_x RG_y SG_x SG_y Vref_x Vref_yA RG_a RG_b SG_a SG_b Vref1_a, Vref3_a Vref1_b, Vref3_bB RG_b RG_a SG_b SG_a Vref1_b, Vref3_b Vref1_a, Vref3_a
RG, SG, Vref
Readout port A port SPI B port SPIA 0 199B 199 0
ADC_N [7:0], DO_N [7:0]
Parameter Symbol Min. Typ. Max. Unit
PXV, PYV*19
SG*19
Pulse width tpwv - 5 - μsRise and fall times tprv, tpfv 150 200 250 nsDuty ratio - - 50 - %
RG Pulse width tpwr 500 600 nsRise and fall times tprr, tpfr 8 12 15 ns
Vsync-CCD clock timing shift tts -100 0 100 ns*19: Symmetrical clock pulses should be overlapped at 50% of maximum pulse amplitude.
TDI-CCD image sensors S14810, S14813
11
Digital output timing
Reset input at power-on
tr(psv)
tPW(RSTB)tPW(Reset)
tPW(RtoR)
Vdd(A)Vdd(D)
MCLK
TG_reset
SPI_RSTB
KMPDC0796EA
Raise all the supply voltage to meet the operating conditions, then input “Tg_reset” and “SPI_RSTB” as shown below to initialize the timing generator and the SPI circuit.
[Ta=25 °C, Typ. values in operating conditions in table (P.2), unless otherwise noted]Parameter Symbol Min. Typ. Max. Unit
SPI_RSTB signal low period at power-on tPW(RSTB) 100 - - nsInterval between SPI_RSTB signal and TG_Reset signal at power-on tPW(RtoR) 100 - - ns
TG_Reset signal high period at power-on*20 *21 tPW(Reset) 3 - - cyclesSupply voltage rise time*22 tr(psv) - 20 - ms*20: Incorrect data is output in the fi rst frame after the reset signal is input. Use the data in the second frame or later.*21: One cycle is the period of a single master clock cycle.*22: The time period where the supply voltage is increased from 10% to 90% with 1 μF external load capacitor, during the power-on
time or readout direction switch time
Parameter Symbol Min. Typ. Max. Unit
Vsync Pulse width tpwvs - 10 - nsRise and fall times tr(out), tf(off) - 2 3 ns
Hsync Pulse width tpwhs - 100 - μsRise and fall times tr(out), tf(off) - 2 3 ns
TDI-CCD image sensors S14810, S14813
12
Parameter Symbol Min. Typ. Max. UnitData rate (per port) VR f(CLK) HzDigital output voltage (LVDS output)
Offset Vofs 1.13 1.25 1.38 VDifferential Vdiff 0.25 0.35 0.45 V
Digital output signal Rise time*23 *24 tr(out) - 2 3 nsFall time*23 *24 tf(out) - 2 3PCLK - Dout delay time tPDD - - 3 ns
PCLK - Hsync delay time Rise time tPDHR - - 3 nsFall time tPDHF - - 3
PCLK - Vsync delay time Rise time tPDVR - - 3 nsFall time tPDVF - - 3
PCLK - CTR delay time Rise time tPDCR - - 3 nsFall time tPDCF - - 3*23: Dout, Vsync, Hsync, PCLK, CTR*24: Time for the output voltage to rise or fall between 10% and 90% when there is a 10 pF load capacitor attached to the output
terminal
Digital output (LVDS)
tPDVF tPDVR
tPDHF tPDHR
tPDCR
tPDD
tPDCF
PCLK
Vsync
Hsync
CTR
GND
Out_X[2:0]tr(out)tf(out)Vofs
Vdiff
KMPDC0797EA
TDI-CCD image sensors S14810, S14813
13
SPI input
SPI_SCLK
SPI_CS
SPI_MOSI A6 A5 A4 A0 W D7 D6 D0
SPI_RSTB
tHOLD(CS)
tr(sigi), tf(sigi)
tSET(CS)
tHOLD(MO)tSET(MO)
KMPDC0799EA
SPI address setting
A6 A5 A4 A3 A2 A1 A0 W D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 1 0 1 1 0 0 0 0 0 1 1 0
SPI_SCLK
SPI_CS
SPI_MOSI
KMPDC0800EA
SPIFollowing parameters can be selected in SPI (serial peripheral interface).
⸱ Off set adjustment of analog amplifi er output⸱ Operation mode setting of A/D converter
Set the SPI using SPI_SCLK, SPI_CS, SPI_MOSI, and SPI_RSTB.SPI_SCLK : SPI clock signalSPI_CS : SPI selection signalSPI_MOSI : SPI input signalSPI_RSTB : SPI reset signal
Parameter Symbol Min. Typ. Max. UnitSPI clock pulse frequency f(SCLK) - - 10 MHzSPI setup time (SPI_CS) tSET(CS) 7 - - nsSPI hold time (SPI_CS) tHOLD(CS) 7 - - nsSPI setup time (SPI_MOSI) tSET(MO) 7 - - nsSPI hold time (SPI_MOSI) tHOLD(MO) 7 - - ns
Digital input signal Rise time*25 tr(sigi) - 5 7 nsFall time*25 tf(sigi) - 5 7*25: Time for the output voltage to rise or fall between 10% and 90% when there is a 10 pF load capacitor attached to the output terminal
TDI-CCD image sensors S14810, S14813
14
Address Name Initial value DescriptionBinary system Decimal system0 - -100 0001 65 Fixed value1 - ---- ---- -
Not used (Do not change the settings) 2 - ---- ---- -3 - ---- ---- -4 - ---- ---- -5 CntEnd[7:0] 0110 0010 98 See the line rate settings (P.15).6 - ---- ---- -
Not used (Do not change the settings)
7 - ---- ---- -8 - ---- ---- -9 - ---- ---- -10 - ---- ---- -11 - ---- ---- - 12 - ---- ---- -13 WinWV[15:8] 0000 0001 300 The number of readout rows are set in WinWV[15:0].14 WinWV[7:0] 0010 110015 - ---- ---- -
Not used (Do not change the settings)16 - ---- ---- -17 - ---- ---- -18 - ---- ---- -19 - ---- ---- -20 - ---- 1100 12 Fixed value21 - ---- ---- - Not used (Do not change the settings)22 - ---- ---- -23 - 0000 0111 7 Fixed value24 ADC_N[7:0] 0000 0000 0 *26
25 - 0000 0011 3 Fixed value26 DO_N[7:0] 0000 0000 0 *26
27 - 0000 0000 0 Fixed value28 - 0000 0000 029 - ---- ---- - Not used (Do not change the settings)30 TG_N[7:0] 0000 0010 2 See the line rate settings (P.15).31 - 0000 1101 13
Fixed value32 - 0001 0100 2033 - 0001 0100 2034 - 0010 0100 3635 - ---- ---- -
Not used (Do not change the settings)36 - ---- ---- -37 - ---- ---- -38 - ---- ---- -39 - 0001 0100 20
Fixed value
40 - 0001 1100 2841 - 0001 1011 2742 - 0000 1110 1443 - 0000 0000 044 - 0001 0100 2045 - ---- ---- - Not used (Do not change the settings)46 - ---- ---- -47 Off set[11:8] ---- 0000 200 Set the off set level in Off set[11:0] (Initial value: about 200 DN in the dark state).48 Off set[7:0] 1100 100049 - 1100 1000 200 Fixed value
*26: Change the readout/halt state of ROIC in ADC_N [7:0] and DO_N [7:0] (readout setting value: 0, halt state setting value: 199).
TDI-CCD image sensors S14810, S14813
15
Line rate settings
TG_N CntEndLine rate
LR(kL/s)
tpwv(μs)
2 98 100.0 5.05 77 50.0 10.08 70 33.3 15.011 67 25.0 20.014 65 20.0 25.0
Note: Line rate settings other than specified above are not recommended.
LR = [Hz]f(CLK)
100 (TG_N + 1)
TDI-CCD image sensors S14810, S14813
16
S14813
UTSRQPONMLKJIHGFEDCBA
123456789101112131415161718192021
□55 ± 0.55
Input window 29Photosensitive area
12.288
Inpu
t win
dow
30.
5
4
3
2.18 ± 0.18*32.05 ± 0.37*2
4.23 ± 0.5
0.33 ± 0.16Gold-platedFe-Ni-Co alloy
UTSRQPONMLKJIHGFEDCBA
1 2 3 4 5 6 7 8 9 101112131415161718192021
50.8 ± 0.35
2.5450
.8 ±
0.3
5
2.54
25.4
25.4
Index mark
Window thickness : 0.6 ± 0.1Window refractive index: 1.46Weight : 40 gAR coating : none
Photosensitivesurface
Index mark
*1: Distance from photosensitive area center to package edge*2: Distance from input window top to photosensitive area*3: Distance from package bottom to photosensitive surface
27.5 ± 0.48*1
27.5
± 0
.48*
1
1st column
Phot
osen
sitive
are
a1.
536
Standoff
KMPDA0626EB
Dimensional outlines (unit: mm)
UTSRQPONMLKJIHGFEDCBA
123456789101112131415161718192021
*1: Distance from photosensitive area center to package edge*2: Distance from input window top to photosensitive area*3: Distance from package bottom to photosensitive surface
Window thickness : 0.6 ± 0.1Window refractive index: 1.52Weight : 40 gAR coating : none
□55 ± 0.55
Input window 29Photosensitive area
12.288
Inpu
t win
dow
30.
5
4
3
2.16 ± 0.19*32.07 ± 0.38*2
4.23 ± 0.5
0.33 ± 0.16Gold-platedFe-Ni-Co alloy
UTSRQPONMLKJIHGFEDCBA
1 2 3 4 5 6 7 8 9 101112131415161718192021
50.8 ± 0.35
2.54
50.8
± 0
.35
2.54
25.4
25.4
Index markIndex mark
Photosensitivesurface
1st column
27.5 ± 0.48*1
Phot
osen
sitive
are
a1.
536
27.5
± 0
.48*
1
Standoff
KMPDA0625EB
S14810
TDI-CCD image sensors S14810, S14813
17
A1 GND Ground (CMOS) IA2 GND Ground (CMOS) IA3 GND Ground (CMOS) IA4 Vdd(D) Digital supply voltage IA5 Vdd(D) Digital supply voltage IA6 GND Ground (CMOS) IA7 Vdd(C) Counter supply voltage IA8 Vdd(C) Counter supply voltage IA9 GND Ground (CMOS) IA10 GND A/D converter ground IA11 GND A/D converter ground IA12 GND Ground (CMOS) IA13 GND Ground (CMOS) IA14 GND Ground (CMOS) IA15 Vdd(D) Digital supply voltage IA16 Vdd(D) Digital supply voltage IA17 GND Ground (CMOS) IA18 Vdd(D) Digital supply voltage IA19 Vdd(D) Digital supply voltage IA20 GND Ground (CMOS) IA21 NC -B1 SPI_RSTB_a SPI reset signal IB2 Vref1_a Bias voltage for LVDS output IB3 GND Ground (CMOS) IB4 Vsyncp_a Frame (vertical) sync signal OB5 PCLKn_a Pixel output sync signal OB6 Out_An[1]_a Pixel output, LVDS (4, 5, 6, 7-bit) signal OB7 Out_Bn[0]_a Pixel output, LVDS (0, 1, 2, 3-bit) signal OB8 Out_Bn[2]_a Pixel output, LVDS (8, 9, 10, 11-bit) signal OB9 Out_Cn[1]_a Pixel output, LVDS (4, 5, 6, 7-bit) signal OB10 Out_Dn[0]_a Pixel output, LVDS (0, 1, 2, 3-bit) signal OB11 Out_Dn[2]_a Pixel output, LVDS (8, 9, 10, 11-bit) signal OB12 GND Ground (CMOS) IB13 GND Ground (CMOS) IB14 GND Ground (CMOS) IB15 Out_En[1]_a Pixel output, LVDS (4, 5, 6, 7-bit) signal OB16 Out_Fn[0]_a Pixel output, LVDS (0, 1, 2, 3-bit) signal OB17 Out_Fn[2]_a Pixel output, LVDS (8, 9, 10, 11-bit) signal OB18 Out_Gn[1]_a Pixel output, LVDS (4, 5, 6, 7-bit) signal OB19 Out_Hn[0]_a Pixel output, LVDS (0, 1, 2, 3-bit) signal OB20 Out_Hn[2]_a Pixel output, LVDS (8, 9, 10, 11-bit) signal OB21 NC -C1 SPI_SCLK_a SPI input signal (clock signal) IC2 Vref2_a Bias voltage for LVDS output OC3 CLK Master clock signal (30 MHz recommended) IC4 Vsyncn_a Frame (vertical) sync signal OC5 PCLKp_a Pixel output sync signal OC6 Out_Ap[1]_a Pixel output, LVDS (4, 5, 6, 7-bit) signal OC7 Out_Bp[0]_a Pixel output, LVDS (0, 1, 2, 3-bit) signal OC8 Out_Bp[2]_a Pixel output, LVDS (8, 9, 10, 11-bit) signal OC9 Out_Cp[1]_a Pixel output, LVDS (4, 5, 6, 7-bit) signal OC10 Out_Dp[0]_a Pixel output, LVDS (0, 1, 2, 3-bit) signal OC11 Out_Dp[2]_a Pixel output, LVDS (8, 9, 10, 11-bit) signal OC12 GND Ground (CMOS) IC13 GND Ground (CMOS) IC14 GND Ground (CMOS) I
C15 Out_Ep[1]_a Pixel output, LVDS (4, 5, 6, 7-bit) signal OC16 Out_Fp[0]_a Pixel output, LVDS (0, 1, 2, 3-bit) signal OC17 Out_Fp[2]_a Pixel output, LVDS (8, 9, 10, 11-bit) signal OC18 Out_Gp[1]_a Pixel output, LVDS (4, 5, 6, 7-bit) signal OC19 Out_Hp[0]_a Pixel output, LVDS (0, 1, 2, 3-bit) signal OC20 Out_Hp[2]_a Pixel output, LVDS (8, 9, 10, 11-bit) signal OC21 GND Ground (CMOS) ID1 GND Ground (CMOS) ID2 Vref3_a Bias voltage for A/D converter ID3 GND Ground (CMOS) ID4 CTRp_a 4-bit serializer sync signal OD5 Hsyncp_a Line (horizontal) sync signal OD6 Out_An[0]_a Pixel output, LVDS (0, 1, 2, 3-bit) signal OD7 Out_An[2]_a Pixel output, LVDS (8, 9, 10, 11-bit) signal OD8 Out_Bn[1]_a Pixel output, LVDS (4, 5, 6, 7-bit) signal OD9 Out_Cn[0]_a Pixel output, LVDS (0, 1, 2, 3-bit) signal OD10 Out_Cn[2]_a Pixel output, LVDS (8, 9, 10, 11-bit) signal OD11 Out_Dn[1]_a Pixel output, LVDS (4, 5, 6, 7-bit) signal OD12 GND Ground (CMOS) ID13 GND Ground (CMOS) ID14 GND Ground (CMOS) ID15 Out_En[0]_a Pixel output, LVDS (0, 1, 2, 3-bit) signal OD16 Out_En[2]_a Pixel output, LVDS (8, 9, 10, 11-bit) signal OD17 Out_Fn[1]_a Pixel output, LVDS (4, 5, 6, 7-bit) signal OD18 Out_Gn[0]_a Pixel output, LVDS (0, 1, 2, 3-bit) signal OD19 Out_Gn[2]_a Pixel output, LVDS (8, 9, 10, 11-bit) signal OD20 Out_Hn[1]_a Pixel output, LVDS (4, 5, 6, 7-bit) signal OD21 Vref4_a Bias voltage for A/D converter OE1 SPI_CS_a SPI input signal (enable signal) IE2 Vref5_a Bias voltage for A/D converter OE3 Vref6_a Bias voltage for A/D converter OE4 CTRn_a 4-bit serializer sync signal OE5 Hsyncn_a Line (horizontal) sync signal OE6 Out_Ap[0]_a Pixel output, LVDS (0, 1, 2, 3-bit) signal OE7 Out_Ap[2]_a Pixel output, LVDS (8, 9, 10, 11-bit) signal OE8 Out_Bp[1]_a Pixel output, LVDS (4, 5, 6, 7-bit) signal OE9 Out_Cp[0]_a Pixel output, LVDS (0, 1, 2, 3-bit) signal OE10 Out_Cp[2]_a Pixel output, LVDS (8, 9, 10, 11-bit) signal OE11 Out_Dp[1]_a Pixel output, LVDS (4, 5, 6, 7-bit) signal OE12 GND Ground (CMOS) IE13 GND Ground (CMOS) IE14 GND Ground (CMOS) IE15 Out_Ep[0]_a Pixel output, LVDS (0, 1, 2, 3-bit) signal OE16 Out_Ep[2]_a Pixel output, LVDS (8, 9, 10, 11-bit) signal OE17 Out_Fp[1]_a Pixel output, LVDS (4, 5, 6, 7-bit) signal OE18 Out_Gp[0]_a Pixel output, LVDS (0, 1, 2, 3-bit) signal OE19 Out_Gp[2]_a Pixel output, LVDS (8, 9, 10, 11-bit) signal OE20 Out_Hp[1]_a Pixel output, LVDS (4, 5, 6, 7-bit) signal OE21 Vref7_a Bias voltage for A/D converter OF1 SPI_MOSI_a SPI input signal (setting input signal) IF2 Vref8_a Bias voltage for A/D converter OF3 Vref9_a Bias voltage for A/D converter OF4 TG_reset Timing circuit reset IF5 PLL_reset Internal PLL reset signal IF17 GND Ground (CMOS) IF18 GND Ground (CMOS) I
Pin connectionsPin no. Symbol Function I/O Pin no. Symbol Function I/O
TDI-CCD image sensors S14810, S14813
18
Pin no. Symbol Function I/O Pin no. Symbol Function I/OF19 GND Ground (CMOS) IF20 NC - F21 NC - G1 GND Ground (CMOS) IG2 GND Ground (CMOS) IG3 GND Ground (CMOS) IG4 GND Ground (CMOS) IG5 GND Ground (CMOS) IG17 GND Ground (CMOS) IG18 GND Ground (CMOS) IG19 GND Ground (CMOS) IG20 GND Ground (CMOS) IG21 GND Ground (CMOS) IH1 A.GND CCD ground voltage IH2 OD CCD output drain voltage IH3 A.GND CCD ground voltage IH4 A.GND CCD ground voltage IH5 A.GND CCD ground voltage IH17 A.GND CCD ground voltage IH18 A.GND CCD ground voltage IH19 A.GND CCD ground voltage IH20 RD CCD reset drain voltage IH21 A.GND CCD ground voltage II1 A.GND CCD ground voltage II2 OD CCD output drain voltage II3 A.GND CCD ground voltage II4 RG_a CCD reset gate_a II5 P1V CCD vertical register clock-1 II17 P4V CCD vertical register clock-4 II18 RG_a CCD reset gate_a II19 A.GND CCD ground voltage II20 RD CCD reset drain voltage II21 A.GND CCD ground voltage IJ1 A.GND CCD ground voltage IJ2 OFD CCD overfl ow drain voltage IJ3 A.GND CCD ground voltage IJ4 SG_a CCD summing gate_a IJ5 P2V CCD vertical register clock-2 IJ17 P3V CCD vertical register clock-3 IJ18 SG_a CCD summing gate_a IJ19 A.GND CCD ground voltage IJ20 OFG CCD overfl ow gate voltage IJ21 A.GND CCD ground voltage IK1 A.GND CCD ground voltage IK2 OG CCD output gate voltage IK3 OS(test)_4*24 CCD output transistor source (test)_4 OK4 OS(test)_3*24 CCD output transistor source (test)_3 OK5 A.GND CCD ground voltage IK17 A.GND CCD ground voltage IK18 OS(test)_1*24 CCD output transistor source (test)_1 OK19 OS(test)_2*24 CCD output transistor source (test)_2 OK20 OG CCD output gate voltage IK21 A.GND CCD ground voltage IL1 A.GND CCD ground voltage IL2 OFG CCD overfl ow gate voltage IL3 A.GND CCD ground voltage I
L4 SG_b CCD summing gate_b IL5 P3V CCD vertical register clock-3 IL17 P2V CCD vertical register clock-2 IL18 SG_b CCD summing gate_b IL19 A.GND CCD ground voltage IL20 OFD CCD overfl ow drain voltage IL21 A.GND CCD ground voltage IM1 A.GND CCD ground voltage IM2 RD CCD reset drain voltage IM3 A.GND CCD ground voltage IM4 RG_b CCD reset gate_b IM5 P4V CCD vertical register clock-4 IM17 P1V CCD vertical register clock-1 IM18 RG_b CCD reset gate_b IM19 A.GND CCD ground voltage IM20 OD CCD output drain voltage IM21 A.GND CCD ground voltage IN1 A.GND CCD ground voltage IN2 RD CCD reset drain voltage IN3 A.GND CCD ground voltage IN4 A.GND CCD ground voltage IN5 A.GND CCD ground voltage IN17 A.GND CCD ground voltage IN18 A.GND CCD ground voltage IN19 A.GND CCD ground voltage IN20 OD CCD output drain voltage IN21 A.GND CCD ground voltage IO1 GND Ground (CMOS) IO2 GND Ground (CMOS) IO3 GND Ground (CMOS) IO4 GND Ground (CMOS) IO5 GND Ground (CMOS) IO17 GND Ground (CMOS) IO18 GND Ground (CMOS) IO19 GND Ground (CMOS) IO20 GND Ground (CMOS) IO21 GND Ground (CMOS) IP1 NC -P2 NC -P3 GND Ground (CMOS) IP4 GND Ground (CMOS) IP5 GND Ground (CMOS) IP17 PLL_reset Internal PLL reset signal IP18 TG_reset Timing circuit reset IP19 Vref9_b Bias voltage for A/D converter OP20 Vref8_b Bias voltage for A/D converter OP21 SPI_MOSI_b SPI input signal (setting input signal) IQ1 Vref7_b Bias voltage for A/D converter OQ2 Out_Hp[1]_b Pixel output, LVDS (4, 5, 6, 7-bit) signal OQ3 Out_Gp[2]_b Pixel output, LVDS (8, 9, 10, 11-bit) signal OQ4 Out_Gp[0]_b Pixel output, LVDS (0, 1, 2, 3-bit) signal OQ5 Out_Fp[1]_b Pixel output, LVDS (4, 5, 6, 7-bit) signal OQ6 Out_Ep[2]_b Pixel output, LVDS (8, 9, 10, 11-bit) signal OQ7 Out_Ep[0]_b Pixel output, LVDS (0, 1, 2, 3-bit) signal OQ8 GND Ground (CMOS) IQ9 GND Ground (CMOS) I
*24: Leave OS terminals open.
TDI-CCD image sensors S14810, S14813
19
Q10 GND Ground (CMOS) IQ11 Out_Dp[1]_b Pixel output, LVDS (4, 5, 6, 7-bit) signal OQ12 Out_Cp[2]_b Pixel output, LVDS (8, 9, 10, 11-bit) signal OQ13 Out_Cp[0]_b Pixel output, LVDS (0, 1, 2, 3-bit) signal OQ14 Out_Bp[1]_b Pixel output, LVDS (4, 5, 6, 7-bit) signal OQ15 Out_Ap[2]_b Pixel output, LVDS (8, 9, 10, 11-bit) signal OQ16 Out_Ap[0]_b Pixel output, LVDS (0, 1, 2, 3-bit) signal OQ17 Hsyncn_b Line (horizontal) sync signal OQ18 CTRn_b 4-bit serializer sync signal OQ19 Vref6_b Bias voltage for A/D converter OQ20 Vref5_b Bias voltage for A/D converter OQ21 SPI_CS_b SPI input signal (enable signal) IR1 Vref4_b Bias voltage for A/D converter OR2 Out_Hn[1]_b Pixel output, LVDS (4, 5, 6, 7-bit) signal OR3 Out_Gn[2]_b Pixel output, LVDS (8, 9, 10, 11-bit) signal OR4 Out_Gn[0]_b Pixel output, LVDS (0, 1, 2, 3-bit) signal OR5 Out_Fn[1]_b Pixel output, LVDS (4, 5, 6, 7-bit) signal OR6 Out_En[2]_b Pixel output, LVDS (8, 9, 10, 11-bit) signal OR7 Out_En[0]_b Pixel output, LVDS (0, 1, 2, 3-bit) signal OR8 GND Ground (CMOS) IR9 GND Ground (CMOS) IR10 GND Ground (CMOS) IR11 Out_Dn[1]_b Pixel output, LVDS (4, 5, 6, 7-bit) signal OR12 Out_Cn[2]_b Pixel output, LVDS (8, 9, 10, 11-bit) signal OR13 Out_Cn[0]_b Pixel output, LVDS (0, 1, 2, 3-bit) signal OR14 Out_Bn[1]_b Pixel output, LVDS (4, 5, 6, 7-bit) signal OR15 Out_An[2]_b Pixel output, LVDS (8, 9, 10, 11-bit) signal OR16 Out_An[0]_b Pixel output, LVDS (0, 1, 2, 3-bit) signal OR17 Hsyncp_b Line (horizontal) sync signal OR18 CTRp_b 4-bit serializer sync signal OR19 GND Ground (CMOS) IR20 Vref3_b Bias voltage for A/D converter IR21 GND Ground (CMOS) IS1 GND Ground (CMOS) IS2 Out_Hp[2]_b Pixel output, LVDS (8, 9, 10, 11-bit) signal OS3 Out_Hp[0]_b Pixel output, LVDS (0, 1, 2, 3-bit) signal OS4 Out_Gp[1]_b Pixel output, LVDS (4, 5, 6, 7-bit) signal OS5 Out_Fp[2]_b Pixel output, LVDS (8, 9, 10, 11-bit) signal OS6 Out_Fp[0]_b Pixel output, LVDS (0, 1, 2, 3-bit) signal OS7 Out_Ep[1]_b Pixel output, LVDS (4, 5, 6, 7-bit) signal OS8 GND Ground (CMOS) IS9 GND Ground (CMOS) IS10 GND Ground (CMOS) IS11 Out_Dp[2]_b Pixel output, LVDS (8, 9, 10, 11-bit) signal OS12 Out_Dp[0]_b Pixel output, LVDS (0, 1, 2, 3-bit) signal OS13 Out_Cp[1]_b Pixel output, LVDS (4, 5, 6, 7-bit) signal OS14 Out_Bp[2]_b Pixel output, LVDS (8, 9, 10, 11-bit) signal OS15 Out_Bp[0]_b Pixel output, LVDS (0, 1, 2, 3-bit) signal O
S16 Out_Ap[1]_b Pixel output, LVDS (4, 5, 6, 7-bit) signal OS17 PCLKp_b Pixel output sync signal OS18 Vsyncn_b Frame (vertical) sync signal OS19 CLK Master clock signal (30 MHz recommended) IS20 Vref2_b Bias voltage for LVDS output OS21 SPI_SCLK_b SPI input signal (clock signal) IT1 NC -T2 Out_Hn[2]_b Pixel output, LVDS (8, 9, 10, 11-bit) signal OT3 Out_Hn[0]_b Pixel output, LVDS (0, 1, 2, 3-bit) signal OT4 Out_Gn[1]_b Pixel output, LVDS (4, 5, 6, 7-bit) signal OT5 Out_Fn[2]_b Pixel output, LVDS (8, 9, 10, 11-bit) signal OT6 Out_Fn[0]_b Pixel output, LVDS (0, 1, 2, 3-bit) signal OT7 Out_En[1]_b Pixel output, LVDS (4, 5, 6, 7-bit) signal OT8 GND Ground (CMOS) IT9 GND Ground (CMOS) IT10 GND Ground (CMOS) IT11 Out_Dn[2]_b Pixel output, LVDS (8, 9, 10, 11-bit) signal OT12 Out_Dn[0]_b Pixel output, LVDS (0, 1, 2, 3-bit) signal OT13 Out_Cn[1]_b Pixel output, LVDS (4, 5, 6, 7-bit) signal OT14 Out_Bn[2]_b Pixel output, LVDS (8, 9, 10, 11-bit) signal OT15 Out_Bn[0]_b Pixel output, LVDS (0, 1, 2, 3-bit) signal OT16 Out_An[1]_b Pixel output, LVDS (4, 5, 6, 7-bit) signal OT17 PCLKn_b Pixel output sync signal OT18 Vsyncp_b Frame (vertical) sync signal OT19 GND Ground (CMOS) IT20 Vref1_b Bias voltage for LVDS output IT21 SPI_RSTB_b SPI reset signal IU1 NC -U2 GND Ground (CMOS) IU3 Vdd(D) Digital supply voltage IU4 Vdd(D) Digital supply voltage IU5 GND Ground (CMOS) IU6 Vdd(D) Digital supply voltage IU7 Vdd(D) Digital supply voltage IU8 GND Ground (CMOS) IU9 GND Ground (CMOS) IU10 GND Ground (CMOS) IU11 GND A/D converter ground IU12 GND A/D converter ground IU13 GND Ground (CMOS) IU14 Vdd(C) Counter supply voltage IU15 Vdd(C) Counter supply voltage IU16 GND Ground (CMOS) IU17 Vdd(D) Digital supply voltage IU18 Vdd(D) Digital supply voltage IU19 GND Ground (CMOS) IU20 GND Ground (CMOS) IU21 GND Ground (CMOS) I
Note: The video output symbol is defi ned as follows. Out_An[0]
[0]: 0, 1, 2, 3-bits, [1]: 4, 5, 6, 7-bits, [2]: 8, 9, 10, 11-bitsp: positive input of diff erential pair, n: negative input of diff erential pairA to H: output ports
Pin no. Symbol Function I/O Pin no. Symbol Function I/O
TDI-CCD image sensors S14810, S14813
20
Precautions (electrostatic countermeasures)⸱ Handle these sensors with bare hands or wearing cotton gloves. In addition, wear anti-static clothing or use a wrist band with an earth ring, in order to prevent electrostatic damage due to electrical charges from friction.⸱ Do not place the sensor directly on workbenches or the like that may become charged with static electricity.⸱ Connect a ground wire to workbenches or fl oors in order to discharge static electricity.⸱ Ground tools, such as tweezers and soldering irons, that are used to handle the sensor.
It is not always necessary to provide all the anti-electrostatic measures stated above. Implement these countermeasures according to the extent of deterioration or damage that may occur.
*1: 10 Ω*2: 100 Ω*3: Connect 0.1 μF and 10 μF.*4: Connect 100 kΩ.*5: Connect 0.1 μF and 100 μF.*6: Connect 0.1 μF.
Note: Set switch to (a) side during A port readout. Set switch to (b) side during B port readout.
GNDVdd(C)*5Vdd(D)*5
Vref9_b*6Vre8_b*6Vref7_b*6Vref6_b*6Vref5_b*6Vref4_b*6Vref3_b*6Vref2_b*6Vref1_b*6Vref9_a*6Vre8_a*6Vref7_a*6Vref6_a*6Vref5_a*6Vref4_a*6Vref3_a*6Vref2_a*6Vref1_a*6
SPI_RSTB_bSPI_MOSI_b
SPI_CS_bSPI_SCLK_bSPI_RSTB_aSPI_MOSI_a
SPI_CS_aSPI_SCLK_a
TG_resetPLL_reset
CLKPCLKn_bPCLKp_bCTRn_bCTRp_b
Vsyncn_bVsyncp_bHsyncn_bHsyncp_bPCLKn_aPCLKp_aCTRn_aCTRp_a
Vdd(D)+3.3 VVdd(C)+2.7 VOut_Ap[0]_a
Out_An[0]_aOut_Ap[1]_aOut_An[1]_aOut_Ap[2]_aOut_An[2]_aOut_Bp[0]_aOut_Bn[0]_aOut_Bp[1]_aOut_Bn[1]_aOut_Bp[2]_aOut_Bn[2]_aOut_Cp[0]_aOut_Cn[0]_aOut_Cp[1]_aOut_Cn[1]_aOut_Cp[2]_aOut_Cn[2]_aOut_Dp[0]_aOut_Dn[0]_aOut_Dp[1]_aOut_Dn[1]_aOut_Dp[2]_aOut_Dn[2]_aOut_Ep[0]_aOut_En[0]_aOut_Ep[1]_aOut_En[1]_aOut_Ep[2]_aOut_En[2]_aOut_Fp[0]_aOut_Fn[0]_aOut_Fp[1]_aOut_Fn[1]_aOut_Fp[2]_aOut_Fn[2]_aOut_Gp[0]_aOut_Gn[0]_aOut_Gp[1]_aOut_Gn[1]_aOut_Gp[2]_aOut_Gn[2]_aOut_Hp[0]_aOut_Hn[0]_aOut_Hp[1]_a Ou
t_Hn
[1]_
aOu
t_Hp
[2]_
aOu
t_Hn
[2]_
aOu
t_Ap
[0]_
bOu
t_An
[0]_
bOu
t_Ap
[1]_
bOu
t_An
[1]_
bOu
t_Ap
[2]_
bOu
t_An
[2]_
bOu
t_Bp
[0]_
bOu
t_Bn
[0]_
bOu
t_Bp
[1]_
bOu
t_Bn
[1]_
bOu
t_Bp
[2]_
bOu
t_Bn
[2]_
bOu
t_Cp
[0]_
bOu
t_Cn
[0]_
bOu
t_Cp
[1]_
bOu
t_Cn
[1]_
bOu
t_Cp
[2]_
bOu
t_Cn
[2]_
bOu
t_Dp
[0]_
bOu
t_Dn
[0]_
bOu
t_Dp
[1]_
bOu
t_Dn
[1]_
bOu
t_Dp
[2]_
bOu
t_Dn
[2]_
bOu
t_Ep
[0]_
bOu
t_En
[0]_
bOu
t_Ep
[1]_
bOu
t_En
[1]_
bOu
t_Ep
[2]_
bOu
t_En
[2]_
bOu
t_Fp
[0]_
bOu
t_Fn
[0]_
bOu
t_Fp
[1]_
bOu
t_Fn
[1]_
bOu
t_Fp
[2]_
bOu
t_Fn
[2]_
bOu
t_Gp
[0]_
bOu
t_Gn
[0]_
bOu
t_Gp
[1]_
bOu
t_Gn
[1]_
bOu
t_Gp
[2]_
bOu
t_Gn
[2]_
bOu
t_Hp
[0]_
bOu
t_Hn
[0]_
bOu
t_Hp
[1]_
bOu
t_Hn
[1]_
bOu
t_Hp
[2]_
bOu
t_Hn
[2]_
bHs
yncp
_aHs
yncn
_aVs
yncp
_aVs
yncn
_a
A.GN
D*3
OD*3
RD*3
OFD*
3
OG*3
OFG*
3
P1V*
3
P2V*
3
P3V*
3
P4V*
3
SG_a*3
SG_b*3
RG_a*3
RG_b*3
OS(te
st)_
1*4
OS(te
st)_
2*4
OS(te
st)_
3*4
OS(te
st)_
4*4
Digital buffer
To LVDS driver
To LVDS driver
To LVDSdriver S14810, S14813
A.GND-10.5 V
OD4.5 V
RD1.5 V
OFD1.5 V
OG-5.5 V
OFG-5.5 V
PXV*1
-3.5 V/-13.5 V
PYV*1
-3.5 V/-13.5 V SG_x*1
-3.5 V/-13.5 V
SG_y*1
-13.5 VRG_x*2
-1.5 V/-11.5 V
RG_y*2
-11.5 V
(a) (b)(a) (b) (a) (b)
(a) (b)(a) (b)
(a) (b)
TP1TP2
TP3TP4
KMPDC0811EA
Application circuit example
TDI-CCD image sensors S14810, S14813
21Cat. No. KMPD1216E02 Aug. 2020 DN
Information described in this material is current as of August 2020.
www.hamamatsu.comHAMAMATSU PHOTONICS K.K., Solid State Division1126-1 Ichino-cho, Higashi-ku, Hamamatsu City, 435-8558 Japan, Telephone: (81)53-434-3311, Fax: (81)53-434-5184U.S.A.: Hamamatsu Corporation: 360 Foothill Road, Bridgewater, N.J. 08807, U.S.A., Telephone: (1)908-231-0960, Fax: (1)908-231-1218, E-mail: [email protected]: Hamamatsu Photonics Deutschland GmbH: Arzbergerstr. 10, D-82211 Herrsching am Ammersee, Germany, Telephone: (49)8152-375-0, Fax: (49)8152-265-8, E-mail: [email protected]: Hamamatsu Photonics France S.A.R.L.: 19, Rue du Saule Trapu, Parc du Moulin de Massy, 91882 Massy Cedex, France, Telephone: (33)1 69 53 71 00, Fax: (33)1 69 53 71 10, E-mail: [email protected] Kingdom: Hamamatsu Photonics UK Limited: 2 Howard Court, 10 Tewin Road, Welwyn Garden City, Hertfordshire AL7 1BW, UK, Telephone: (44)1707-294888, Fax: (44)1707-325777, E-mail: [email protected] Europe: Hamamatsu Photonics Norden AB: Torshamnsgatan 35 16440 Kista, Sweden, Telephone: (46)8-509 031 00, Fax: (46)8-509 031 01, E-mail: [email protected]: Hamamatsu Photonics Italia S.r.l.: Strada della Moia, 1 int. 6, 20020 Arese (Milano), Italy, Telephone: (39)02-93 58 17 33, Fax: (39)02-93 58 17 41, E-mail: [email protected]: Hamamatsu Photonics (China) Co., Ltd.: 1201 Tower B, Jiaming Center, 27 Dongsanhuan Beilu, Chaoyang District, 100020 Beijing, P.R.China, Telephone: (86)10-6586-6006, Fax: (86)10-6586-2866, E-mail: [email protected]: Hamamatsu Photonics Taiwan Co., Ltd.: 8F-3, No. 158, Section2, Gongdao 5th Road, East District, Hsinchu, 300, Taiwan R.O.C. Telephone: (886)3-659-0080, Fax: (886)3-659-0081, E-mail: [email protected]
Product specifications are subject to change without prior notice due to improvements or other reasons. This document has been carefully prepared and the information contained is believed to be accurate. In rare cases, however, there may be inaccuracies such as text errors. Before using these products, always contact us for the delivery specification sheet to check the latest specifications.The product warranty is valid for one year after delivery and is limited to product repair or replacement for defects discovered and reported to us within that one year period. However, even if within the warranty period we accept absolutely no liability for any loss caused by natural disasters or improper product use.Copying or reprinting the contents described in this material in whole or in part is prohibited without our prior permission.
Related informationwww.hamamatsu.com/sp/ssd/doc_en.html
Precautions⸱ Disclaimer⸱ Image sensors
