TC1270A/70AN/71A Voltage Supervisor with Manual Reset Inputww1.microchip.com/downloads/en/DeviceDoc/22035D.pdfTC1270A/70AN/71A DS22035D-page 4 2007-2011 Microchip Technology Inc. Reset

TC1270A/70AN/71AVoltage Supervisor with Manual Reset Input

Features:• Precision Voltage Monitor

- 2.63V, 2.93V, 3.08V, 4.38V and 4.63V Trip Points (Typical)

• Manual Reset Input • Reset Time-Out Delay:

- Standard: 280 ms (Typical)- Optional: 2.19 ms, and 35 ms (Typical)

• Power Consumption 15 µA max• No glitches on outputs during power-up • Active Low Output Options:

- Push-Pull Output and Open-Drain Output• Active High Output Option:

- Push-Pull Output• Replacement for (Specification compatible with):

- TC1270, TC1271 - TCM811, TCM812

• Fully Static Design• Low-Voltage Operation (1.0V)• ESD Protection:

- 4 kV Human Body Model (HBM)- 400V Machine Model (MM)

• Extended (E) Temperature Range:-40°C to +125°C

• Package Options:- 4-Lead SOT-143 - 5-Lead SOT-23- Pb-free Device

Package Types

Functional Block Diagram

Device Features

1

2

4

3

TC1271A

SOT-143

VSS VDD

RST MR

1

2

4

3

TC1270A

TC1270A

N

SOT-143

VSS VDD

RST MR

1

2

3

5

4

TC1271A

SOT-23-5

1

2

3

5

4

SOT-23-5

NC NC

VDDMR RST

VSS VSS

VDDMR RST

TC1270A

TC1270A

N

18.5 k

VDD

MR

RST

RST

Glitch Filter

VoltageDetector

PP

PP

Out

put

Driv

er

Circuitry(TC1271A)

(TC1270A)

ResetGeneratorand Delay

Timer(2.19 ms,

35 ms,280 ms) OD

RST (TC1270AN)

Device

Output

Res

et D

elay

(m

s) (T

yp)(3

)

Res

et T

rip

Poin

t (V)

(3)

Volta

ge

Ran

ge (V

)

Tem

pera

ture

R

ange

Packages CommentType Active Level

TC1270A Push-Pull Low

2.19, 35,280(1)

4.63, 4.38,3.08, 2.93,2.63(4)

1.0V to 5.5V

-40°C to +125°C

SOT-143(2), SOT-23-5

Replaces TC1270 and TCM811

TC1270AN Open-Drain Low SOT-143(2),

SOT-23-5New Option

TC1271A Push-Pull High SOT-143(2),

SOT-23-5Replaces TC1271 and TCM812

Note 1: The 280 ms Reset delay time-out is compatible with the TC1270, TC1271, TCM811 and TCM812 devices.2: The SOT-143 package is compatible with the TC1270, TC1271, TCM811 and TCM812 devices.3: Custom Reset trip points and Reset delays available, contact your local Microchip sales office.4: The TC1270/1 and TCM811/12 1.75V trip point option is not supported.

2007-2011 Microchip Technology Inc. DS22035D-page 1

TC1270A/70AN/71A

NOTES:

DS22035D-page 2 2007-2011 Microchip Technology Inc.

TC1270A/70AN/71A

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings †Supply Voltage (VDD to VSS) ...............................+7.0VInput Current, VDD.............................................. 10 mAOutput Current, RESET, Reset .......................... 10 mAVoltage on all inputs and outputs

w.r.t. VSS ............................ -0.6V to (VDD + 1.0V)Storage Temperature Range.............. -65°C to +150°COperating Temperature Range .......... -40°C to +125°CMaximum Junction Temperature, TS .................. 150°CESD protection on all pins

Human Body Model 4 kVMachine Model 400V

† Notice: Stresses above those listed under “AbsoluteMaximum Ratings” may cause permanent damage to adevice. The absolute maximum values are merelystress ratings – functional operation of a device atthose, or any other conditions above those indicated inthe operational listing of these specifications, is notimplied. Exposure to absolute maximum ratingconditions for extended periods may affect devicereliability.

ELECTRICAL CHARACTERISTICSElectrical Characteristics: Unless otherwise noted, VDD = 5V for L/M versions, VDD = 3.3V for T/S versions,VDD = 3V for R version, TA = -40°C to +125°C. Typical values are at TA = +25°C.

Parameter Sym Min Typ(1) Max Units Test Conditions

Operating Voltage Range VDD 1.0 — 5.5 VSupply Current IDD — 7 15 µA VDD > VTRIP, for L/M/R/S/T,

VDD = 5.5V— 4.75 10 µA VDD > VTRIP, for R/S/T, VDD = 3.6V— 10 15 µA VDD < VTRIP, for L/M/R/S/T

Reset Trip Point Threshold (3)

VTRIP 4.54 4.63 4.72 V TC127xAL: TA = +25°C4.50 — 4.75 V TA = –40°C to +125°C4.30 4.38 4.46 V TC127xAM: TA = +25°C4.25 — 4.50 V TA = –40°C to +125°C3.03 3.08 3.14 V TC127xAT: TA = +25°C3.00 — 3.15 V TA = –40°C to +125°C2.88 2.93 2.98 V TC127xAS: TA = +25°C 2.85 — 3.00 V TA = –40°C to +125°C2.72 2.77 2.82 V TC127xA:(5) TA = +25°C 2.70 — 2.85 V TA = –40°C to +125°C2.58 2.63 2.68 V TC127xAR: TA = +25°C 2.55 — 2.70 V TA = –40°C to +125°C

Note 1: Data in the Typical (“Typ”) column is at 5V, +25C, unless otherwise stated.2: RST output for TC1270A and TC1270AN, RST output for TC1271A.3: TC127XA refers to the TC1270A, TC1270AN or TC1271A device.4: Hysteresis is within the VTRIP(MIN) to VTRIP(MAX) window.5: Custom-ordered voltage trip point. Minimum order volume requirement.6: This specification allows this device to be used in PIC® microcontroller applications that require the

In-Circuit Serial Programming™ (ICSP™) feature (see device-specific programming specifications for voltage requirements). The total time that the RST pin can be above the maximum device operational voltage (5.5V) is 100s. Current into the RST pin should be limited to 2 mA. It is recommended that the device operational temperature be maintained between 0°C to +70°C (+25°C preferred). For additional information, refer to Figure 2-41.


TC1270A/70AN/71A

Reset Threshold Tempco — ±30 — ppm/°CReset Trip Point Hysteresis (1)

VHYS — 0.3 — % Percentage of VTRIP Voltage

MR Input High Threshold VIH 2.3 — — V VDD > VTRIP(MAX), L/M only0.7 VDD — — V VDD > VTRIP(MAX), R/S/T only

MR Input Low Threshold VIL — — 0.8 V VDD > VTRIP(MAX), L/M only— — 0.25 VDD V VDD > VTRIP(MAX), R/S/T only

MR Pull-up Resistance 10 18.5 40 kOpen-Drain High Voltage on Output

VODH — — 13.5 V Open-Drain Output pin only. VDD = 3.0V, Time voltage > 5.5 applied 100s. Current into pin limited to 2 mA +25°C operation recommended (6)

Reset Output Voltage Low (2)

TC1270A/TC1270AN

VOL — — 0.3 V R/S/T only,ISINK = 1.2 mA, VDD = VTRIP(MIN)

TC1271A — — 0.3 V R/S/T only,ISINK = 1.2 mA, VDD = VTRIP(MAX)

TC1270A/TC1270AN

— — 0.4 V L/M only,ISINK = 3.2 mA, VDD = VTRIP(MIN)

TC1271A — — 0.3 V L/M only,ISINK = 3.2 mA, VDD = VTRIP(MAX)

TC1270A/TC1270AN

— — 0.3 V L/M only,ISINK = 50 µA, VDD > 1.0V

Reset Output Voltage High (2)

TC1270A VOH 0.8 VDD — — V R/S/T only,ISOURCE = 500 µA, VDD = VTRIP(MAX)

TC1270A VDD - 1.5 — — V L/M only,ISOURCE = 800 µA, VDD = VTRIP(MAX)

TC1271A 0.8 VDD — — V ISOURCE = 500 µA, VDD VTRIP(MIN)Input Leakage Current IIL — — ±1 µA VPIN = VDDOpen-Drain RST Output Leakage

IOLOD — — 1 µA Open-Drain configuration only.

Capacitive Loading Specification on Output Pins

CIO — — 50 pF

ELECTRICAL CHARACTERISTICS (CONTINUED)Electrical Characteristics: Unless otherwise noted, VDD = 5V for L/M versions, VDD = 3.3V for T/S versions,VDD = 3V for R version, TA = -40°C to +125°C. Typical values are at TA = +25°C.


Note 1: Data in the Typical (“Typ”) column is at 5V, +25C, unless otherwise stated.2: RST output for TC1270A and TC1270AN, RST output for TC1271A.3: TC127XA refers to the TC1270A, TC1270AN or TC1271A device.4: Hysteresis is within the VTRIP(MIN) to VTRIP(MAX) window.5: Custom-ordered voltage trip point. Minimum order volume requirement.6: This specification allows this device to be used in PIC® microcontroller applications that require the

In-Circuit Serial Programming™ (ICSP™) feature (see device-specific programming specifications for voltage requirements). The total time that the RST pin can be above the maximum device operational voltage (5.5V) is 100s. Current into the RST pin should be limited to 2 mA. It is recommended that the device operational temperature be maintained between 0°C to +70°C (+25°C preferred). For additional information, refer to Figure 2-41.


TC1270A/70AN/71A

1.1 AC CHARACTERISTICS

1.1.1 TIMING PARAMETER SYMBOLOGYThe timing parameter symbols have been createdfollowing one of the following formats:

FIGURE 1-1: Test Load Conditions.

1. TppS2ppS 2. TppST

F Frequency T TimeE ErrorLowercase letters (pp) and their meanings:

ppio Input or Output pin osc Oscillatorrx Receive tx Transmitbitclk RX/TX BITCLK RST Resetdrt Device Reset TimerUppercase letters and their meanings:

SF Fall P PeriodH High R RiseI Invalid (High-impedance) V ValidL Low Z High-impedance

Pin

VSS

CL = 50 pF


TC1270A/70AN/71A

TIMING DIAGRAMS AND SPECIFICATIONS

MR Pin and Reset Pin Waveform

Device Voltage and Reset Pin (Active Low) Waveform

Reset and Device Reset Timer Requirements

Electrical Characteristics: Unless otherwise noted, VDD = 5V for L/M versions, VDD = 3.3V for T/S versions,VDD = 3V for R version, TA = -40°C to +125°C. Typical values are at TA = +25°C.


VDD to Reset Delay tRD — 50 — µs VDD = VTRIP(MAX) toVTRIP(MIN) –125 mV

Reset Active Time Out Period

TC127XAxBVyy(3) tRST 1.09 2.19 4.38 ms VDD = VTRIP(MAX)TC127XAxAVyy(3) 17.5 35 70 ms VDD = VTRIP(MAX)TC127XAxVyy(3) 140 280 560 ms VDD = VTRIP(MAX)

MR Minimum Pulse Width tMR 10 — — µs

MR Noise Immunity tMRNI — 0.1 — µs

MR to Reset Propagation Delay tMD — 0.2 — µs

Note 1: Unless otherwise stated, data in the Typical (“Typ”) column is at 5V, +25C.2: RST output for TC1270A, RST output for TC1271A.3: TC127XA refers to the TC1270A, TC1270AN or TC1271A device.

“x” indicates the selected voltage trip point, while “yy” indicates the package code.

MR

RST

tRST

tMR

RST

tMD tMRNI

VTRIP(MAX)

VTRIP(MIN)

1VVDD

VTRIP

tRST

RST(1)

RST

tRST tRD

VDD < 1V is outside the device operating specification. The RST (or RST) output state is unknown while VDD < 1V.

Note 1: The TC1270AN requires an external pull-up resistor.


TC1270A/70AN/71A

TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = +1.0V to +5.5V, VSS = GND.

Parameters Sym Min Typ Max Units Conditions

Temperature RangesSpecified Temperature Range TA -40 — +125 °C

Operating Temperature Range TA -40 — +125 °C

Storage Temperature Range TA -65 — +150 °C

Thermal Package ResistancesThermal Resistance, 5L-SOT-23 JA — 256 — °C/W

Thermal Resistance, 4L-SOT-143 JA — 426 — °C/W


TC1270A/70AN/71A

NOTES:


TC1270A/70AN/71A

2.0 TYPICAL PERFORMANCE CURVES

Note: Unless otherwise indicated, all limits are specified for VDD = 1V to 5.5V, TA = –40°C to +125°C.

FIGURE 2-1: IDD vs. Temperature (Reset Power-up Timer Inactive)(TC1270AL, TC1270ANL, TC1271AL- 4.50V min./4.63V typ./4.75V max.).

FIGURE 2-2: IDD vs. Temperature (Reset Power-up Timer Inactive)(TC1270AT, TC1270ANT, TC1271AT- 3.00V min./3.08V typ./3.15V max.).

FIGURE 2-3: IDD vs. Temperature (Reset Power-up Timer Inactive)(TC1270AR, TC1270ANR, TC1271AR- 2.55V min./2.63V typ./2.70V max.).

FIGURE 2-4: IDD vs. Temperature (Reset Power-up Timer Active)(TC1270AL, TC1270ANL, TC1271AL- 4.50V min./4.63V typ./4.75V max.).

FIGURE 2-5: IDD vs. Temperature (Reset Power-up Timer Active)(TC1270AT, TC1270ANT, TC1271AT- 3.00V min./3.08V typ./3.15V max.).

FIGURE 2-6: IDD vs. Temperature (Reset Power-up Timer Active)(TC1270AR, TC1270ANR, TC1271AR- 2.55V min./2.63V typ./2.70V max.).

Note: The graphs and tables that follow this note are the result of a statistical summary based on a limited numberof samples and are provided for informational purposes only. The performance characteristics listed hereinare not tested or guaranteed. In some graphs or tables, the data presented may be outside the specifiedoperating range (e.g., outside specified power supply range) and therefore outside the warranted range.

0

0.5

1

1.5

2

2.5

-40

-20 0 20 40 60 80 100

120

Temperature (°C)

I DD (µ

A)

1.0V

2.0V

3.0V

4.0V

5.0V

0

0.5

1

1.5

2

2.5

3

-40

-20 0 20 40 60 80 100

120

Temperature (°C)

I DD (µ

A)

1.0V

2.0V

3.0V

4.0V

5.0V

0

0.5

1

1.5

2

2.5

3

-40

-20 0 20 40 60 80 100

120

Temperature (°C)

I DD (µ

A)

1.0V

2.0V

3.0V

4.0V

5.0V

4.5

5

5.5

6

6.5

7

-40

-20 0 20 40 60 80 100

120

Temperature (°C)

I DD (µ

A)

4.8V

5.5V

33.5

44.5

55.5

66.5

7

-40

-20 0 20 40 60 80 100

120

Temperature (°C)

I DD (µ

A)

4.5V

5.5V

3.5V

2.53

3.54

4.55

5.56

6.5

-40

-20 0 20 40 60 80 100

120

Temperature (°C)

I DD (µ

A) 4.0V

5.0V

3.0V


TC1270A/70AN/71A


FIGURE 2-7: IDD vs. VDD (Reset Power-up Timer Inactive)(TC1270AL, TC1270ANL, TC1271AL- 4.50V min./4.63V typ./4.75V max.).

FIGURE 2-8: IDD vs. VDD (Reset Power-up Timer Inactive)(TC1270AT, TC1270ANT, TC1271AT- 3.00V min./3.08V typ./3.15V max.).

FIGURE 2-9: IDD vs. VDD (Reset Power-up Timer Inactive)(TC1270AR, TC1270ANR, TC1271AR- 2.55V min./2.63V typ./2.70V max.).

FIGURE 2-10: IDD vs. VDD (Reset Power-up Timer Active) (TC1270AL, TC1270ANL, TC1271AL- 4.50V min./4.63V typ./4.75V max.).

FIGURE 2-11: IDD vs. VDD (Reset Power-up Timer Active)(TC1270AT, TC1270ANT, TC1271AT- 3.00V min./3.08V typ./3.15V max.).

FIGURE 2-12: IDD vs. VDD (Reset Power-up Timer Active) (TC1270AR, TC1270ANR, TC1271AR- 2.55V min./2.63V typ./2.70V max.).

0

0.5

1

1.5

2

2.5

3

1 2 3 4 5

VDD (V)

I DD (µ

A)

-40°C

+125°C

+25°C

0

0.5

1

1.5

2

2.5

3

1 2 3 4 5

VDD (V)

I DD (µ

A)

-40°C

+125°C

+25°C

0

0.5

1

1.5

2

2.5

3

3.5

1 2 3 4 5

VDD (V)

I DD (µ

A)

-40°C

+125°C

+25°C

4.5

5

5.5

6

6.5

7

4.5 4.7 4.9 5.1 5.3 5.5

VDD (V)

I DD (µ

A)

-40°C

+125°C

+25°C

2.53

3.54

4.55

5.56

6.57

3 3.5 4 4.5 5 5.5

VDD (V)

I DD (µ

A)

-40°C

+125°C

+25°C

2

3

4

5

6

7

2.5 3 3.5 4 4.5 5 5.5

VDD (V)

I DD (µ

A)

-40°C

+125°C

+25°C


TC1270A/70AN/71A


FIGURE 2-13: VTRIP and VHYS vs. Temperature(TC1270AL, TC1270ANL, TC1271AL - 4.50V min./4.63V typ./4.75V max.).

FIGURE 2-14: VTRIP and VHYS vs. Temperature(TC1270AT, TC1270ANT, TC1271AT - 3.00V min./3.08V typ./3.15V max.).

FIGURE 2-15: VTRIP and VHYST vs. Temperature(TC1270AR, TC1270ANR, TC1271AR- 2.55V min./2.63V typ./2.70V max.).

FIGURE 2-16: VOL vs. IOL (TC1270AL, TC1270ANL, TC1271AL - 4.50V min./4.63V typ./4.75V max.).

FIGURE 2-17: VOL vs. IOL (TC1270AT, TC1270ANT, TC1271AT- 3.00V min./3.08V typ./3.15V max.).

FIGURE 2-18: VOL vs. IOL (TC1270AR, TC1270ANR, TC1271AR- 2.55V min./2.63V typ./2.70V max.).

4.6054.61

4.6154.62

4.6254.63

4.6354.64

4.6454.65

-40 25 125

Temperature (°C)

V TR

IP (V

)

0.20.220.240.260.280.30.320.340.360.380.4

V HYS

(%)

VTRIP (with VDD Falling)

VHYS

VTRIP (with VDD Rising)

3.0663.0683.07

3.0723.0743.0763.0783.08

3.0823.0843.086

-40 25 125

Temperature (°C)

V TR

IP (V

)

0.20.220.240.260.280.30.320.340.360.380.4

V HYS

(%)

VHYS

VTRIP (with VDD Falling)


2.61

2.615

2.62

2.625

2.63

2.635

2.64

-40 25 125

Temperature (°C)

V TR

IP (V

)

0.20.220.240.260.280.30.320.340.360.380.4

V HYS

(%)

VHYS VTRIP (with VDD Falling)


0

0.02

0.04

0.06

0.08

0.1

0.12

0.00 1.00 2.00 3.00 4.00

IOL (mA)

VO

L (V

)

2.0V

3.0V

4.3V

4.4V

4.5V

0

0.05

0.1

0.15

0.2

0.25

0 2 4 6 8IOL (mA)

VO

L (V

) 3.2V4.0V

4.5V5.0V

5.5V

3.15

00.020.040.060.080.1

0.120.140.160.180.2

0 1 2 3 4

IOL (mA)

V OL

(V)

2.0V 2.45V

2.5V


TC1270A/70AN/71A


FIGURE 2-19: VOL vs. Temperature (TC1270AL, TC1270ANL, TC1271AL- 4.50V min./4.63V typ./4.75V max.).@ VDD = 4.5V).

FIGURE 2-20: VOL vs. Temperature (TC1270AT, TC1270ANT, TC1271AT- 3.00V min./3.08V typ./3.15V max.).@ VDD = 2.7V).

FIGURE 2-21: VOL vs. Temperature (TC1270AR, TC1270ANR, TC1271AR- 2.55V min./2.63V typ./2.70V max.).@ VDD = 1.8V).

FIGURE 2-22: VOH vs. IOL (TC1270AL, TC1270ANL, TC1271AL - 4.50V min./4.63V typ./4.75V max.)@ +25°C).

FIGURE 2-23: VOH vs. IOH (TC1270AT, TC1270ANT, TC1271AT- 3.00V min./3.08V typ./3.15V max.)@ +25°C).

FIGURE 2-24: VOH vs. IOH (TC1270AR, TC1270ANR, TC1271AR- 2.55V min./2.63V typ./2.70V max.)@ +25°C).

0

0.02

0.04

0.06

0.08

0.1

0.12

-40 10 60 110

Temperature (°C)

V OL

(V)

4 mA

2 mA

1 mA 0.5 0.35 mA0.2

A

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

-40 10 60 110

Temperature (°C)

V OL

(V)

8 mA

6 mA

4 mA

2 mA 1 mA 0.5 A

0

0.05

0.1

0.15

0.2

-40 10 60 110Temperature (°C)

V OL

(V)

4 mA

2 mA

1 mA 0.5 0.35 mA0.2

A

4.2

4.4

4.6

4.8

5

5.2

5.4

5.6

0.00 1.00 2.00 3.00 4.00 5.00

IOH (mA)

VO

H (V

)

5.5V

5.0V

4.8V

4.75V

1.7

1.9

2.1

2.3

2.5

2.7

2.9

0 1 2 3 4 5

IOH (mA)

V OH (V

)2.9V

2.7V

2.5V

22.5

33.5

44.5

55.5

6

0 1 2 3 4 5

IOH (mA)

V OH (V

)

5.5V

5.0V

4.5V

4.0V

3.0V

2.8V


TC1270A/70AN/71A


FIGURE 2-25: VDD Falling to Reset Propagation Delay (tRPD) vs. Temperature(TC1270AL, TC1270ANL, TC1271AL- 4.50V min./4.63V typ./4.75V max.).

FIGURE 2-26: VDD Falling to Reset Propagation Delay (tRPD) vs. Temperature(TC1270AT, TC1270ANT, TC1271AT- 3.00V min./3.08V typ./3.15V max.).

FIGURE 2-27: VDD Falling to Reset Propagation Delay (tRPD) vs. Temperature (TC1270AR, TC1270ANR, TC1271AR- 2.55V min./2.63V typ./2.70V max.).

FIGURE 2-28: Reset Time-Out Period (tRST) vs. Temperature(TC1270AL, TC1270ANL, TC1271AL - 4.50V min./4.63V typ./4.75V max.).

FIGURE 2-29: Reset Time-Out Period (tRST) vs. Temperature(TC1270AT, TC1270ANT, TC1271AT - 3.00V min./3.08V typ./3.15V max.).

FIGURE 2-30: Reset Time-Out Period (tRST) vs. Temperature(TC1270AR, TC1270ANR, TC1271AR - 2.55V min./2.63V typ./2.70V max.).

48

49

50

51

52

53

54

55


t RPD

(µs)

48

49

50

51

52

53

54

55

-40 10 60 110

Temperature (°C)

t RPD

(µs)

48

49

50

51

52

53

54

55

-40 10 60 110

Temperature (°C)

t RPD

(µs)

275280285290295300305310315320

-40 10 60 110

Temperature (°C)

t RST

(ms)

5.5V

5.0V

4.75V

275280285290295300305310315320325

-40 10 60 110

Temperature (°C)

t RST

(ms)

5.5V5.0V

4.5V4.0V

3.2V

3.15

275280285290295300305310315320

-40 10 60 110

Temperature (°C)

t RST

(ms)

5.5V

5.0V

4.5V

4.0V

3.0V

2.8V


TC1270A/70AN/71A


FIGURE 2-31: Reset Time-Out Period (tRST) (C time out option) vs. Temperature(TC1270AL, TC1270ANL, TC1271AL - 4.50V min./4.63V typ./4.75V max.).

FIGURE 2-32: Reset Time-Out Period (tRST) (C time out option) vs. Temperature(TC1270AT, TC1270ANT, TC1271AT - 3.00V min./3.08V typ./3.15V max.).

FIGURE 2-33: Reset Time-Out Period (tRST) (C time out option) vs. Temperature(TC1270AR, TC1270ANR, TC1271AR - 2.55V min./2.63V typ./2.70V max.).

FIGURE 2-34: Reset Time-Out Period (tRST) (B time out option) vs. Temperature(TC1270AL, TC1270ANL, TC1271AL - 4.50V min./4.63V typ./4.75V max.).

FIGURE 2-35: Reset Time-Out Period (tRST) (B time out option) vs. Temperature(TC1270AT, TC1270ANT, TC1271AT - 3.00V min./3.08V typ./3.15V max.).

FIGURE 2-36: Reset Time-Out Period (tRST) (B time out option) vs. Temperature(TC1270AR, TC1270ANR, TC1271AR - 2.55V min./2.63V typ./2.70V max.).

34

35

36

37

38

39

40


t RST

(ms)

5.5V

5.0V

4.75V

34

35

36

37

38

39

40


t RST

(ms)

5.5V5.0V

4.5V4.0V

3.2V

3.15V

34

35

36

37

38

39

40


t RST

(ms)

5.5V

5.0V

4.5V

4.0V

3.0V

2.8V

2.12.152.2

2.252.3

2.352.4

2.452.5


t RST

(ms)

5.5V

5.0V

4.75V

2.12.152.2

2.252.3

2.352.4

2.452.5


t RST

(ms)

5.5V5.0V

4.5V4.0V

3.2V

3.15V

2.12.15

2.22.25

2.32.35

2.42.45

2.5


t RST

(ms)

5.5V

5.0V

4.5V

4.0V

3.0V

2.8V


TC1270A/70AN/71A


FIGURE 2-37: MR Low to Reset Propagation Delay (tMD) vs. Temperature(TC1270AL, TC1270ANL, TC1271AL- 4.50V min./4.63V typ./4.75V max.).

FIGURE 2-38: MR Low to Reset Propagation Delay (tMD) vs. Temperature (TC1270AT, TC1270ANT, TC1271AT- 3.00V min./3.08V typ./3.15V max.).

FIGURE 2-39: MR Low to Reset Propagation Delay (tMD) vs. Temperature (TC1270AR, TC1270ANR, TC1271AR- 2.55V min./2.63V typ./2.70V max.).

FIGURE 2-40: VDD Transient Duration vs. Reset Threshold Overdrive(VTRIP (minimum) - VDD).

FIGURE 2-41: Open-Drain Leakage Current vs. Voltage Applied to RST Pin (TC1270AR, TC1270ANR, TC1271AR- 2.55V minimum).

0.17

0.18

0.19

0.2

0.21

0.22

-40 10 60 110

Temperature (°C)

t MD (µ

s)

5.5V

5.0V

4.8V4.75V

0.17

0.18

0.19

0.2

0.21

0.22

-40 10 60 110

Temperature (°C)

t MD (µ

s)

5.5V

5.0V

4.5V4.0V

0.17

0.18

0.19

0.2

0.21

0.22

-40 10 60 110

Temperature (°C)

t MD (µ

s)

5.5V

5.0V 4.5V

4.0V

0

10

20

30

40

50

60

0.001 0.01 0.1 1 10

VTRIPMIN - VDD (V)

Tran

sien

t Dur

atio

n (µ

s)

4.63V

3.08V

2.63VAbove Line, Reset Occurs

Below Line, No Reset Occurs

1.E-14

1.E-12

1.E-10

1.E-08

1.E-06

1.E-04

1.E-02

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14Output Voltage (V)

Leak

age

Cur

rent

(A)

-40°C

+25°C

+125°C

13.5V


TC1270A/70AN/71A

NOTES:


TC1270A/70AN/71A

3.0 PIN DESCRIPTIONSDescriptions of the pins are listed in Table 3-1.

TABLE 3-1: PINOUT DESCRIPTIONPin Number

Sym

Pin

Standard Function

TC1270A (Push-Pull, active-low)

TC1270AN (Open-Drain, active-low)

TC1271A (Push-Pull, active-high)

SOT-

23-5

SOT-

143-

4

SOT-

23-5

SOT-

143-

4

SOT-

23-5

SOT-

143-

4

Type Buffer / Driver

5 1 1 5 1 VSS — Power Ground

4 2 — — — — RST O Push-Pull

Reset output (Push-Pull), active-lowH = VDD > VTRIP, Reset pin is inactive

(after Reset Delay Timer completes) L = VDD < VTRIP, Reset pin is active

Goes active (Low) if one of these conditions occurs:1. If VDD falls below the selected Reset

voltage threshold.2. If the MR pin is forced low.3. During power-up.

— — 4 2 — — RST O Open-Drain

Reset output (Open-Drain), active-lowFloat = VDD > VTRIP, Reset pin is inactive

(after Reset Delay Timer completes) L = VDD < VTRIP, Reset pin is active

Goes active (Low) if one of these conditions occurs:1. If VDD falls below the selected Reset


— — — — 4 2 RST O Push-Pull

Reset output (Push-Pull), active-highH = VDD < VTRIP, Reset pin is active L = VDD > VTRIP, Reset pin is inactive

(after Reset Delay Timer completes)

Goes active (High) if one of these conditions occurs:1. If VDD falls below the selected Reset


Note 1: The MR pin has an internal weak pull-up (18.5 k typical).


TC1270A/70AN/71A

3.1 Ground Terminal (VSS) VSS provides the negative reference for the analoginput voltage. Typically, the circuit ground is used.

3.2 Supply Voltage (VDD)VDD can be used for power supply monitoring or avoltage level that requires monitoring.

3.3 Reset Output (RST and RST)There are three types of Reset output pins. These are:

1. Push-Pull active-low Reset2. Push-Pull active-high Reset3. Open-Drain active-low Reset, external pull-up

resistor required.

3.3.1 ACTIVE-LOW (RST) – PUSH-PULLThe RST push-pull output remains low while VDD isbelow the Reset voltage threshold (VTRIP). The timethat the RST pin is held low after the device voltage(VDD) returns to a high level (> VTRIP) is typically280 ms. After the Reset Delay Timer expires, the RSTpin will be driven to the high state.

3.3.2 ACTIVE-HIGH (RST) – PUSH-PULLThe RST push-pull output remains high while VDD isbelow the Reset voltage threshold (VTRIP). The timethat the RST pin is held high after the device voltage(VDD) returns to a high level (> VTRIP) is typically280 ms. After the Reset Delay Timer expires, the RSTpin will be driven to the low state.

3.3.3 ACTIVE-LOW (RST) – OPEN-DRAIN The RST open-drain output remains low while VDD isbelow the Reset voltage threshold (VTRIP). The timethat the RST pin is held low after the device voltage(VDD) returns to a high level (> VTRIP) depends on theReset time-out selected. After the Reset Delay Timerexpires, the RST pin will float.

3.4 Manual Reset Input (MR)The Manual Reset (MR) input pin allows a push buttonswitch to easily be connected to the system. When thepush button is depressed, it forces a system Reset.This pin has circuitry that filters noise that may bepresent on the MR signal.

The MR pin is active-low and has an internal pull-upresistor.

3 3 3 3 3 3 MR I ST(1) Manual Reset Input Pin This input allows a push button switch to be directly connected to a TC1270A/70AN/71A device’s MR pin, which can be used to force a system Reset. The input filter ignores noise pulses that occur on the MR pin.H = Switch is open (internal pull-up resistor

pulls signal high). State of the RST/RST pin is determined by other system condi-tions.

L = Switch is depressed (shorted to ground). This forces the RST/RST pin Active.

2 4 2 4 2 4 VDD — Power Supply Voltage

1 — 1 — 1 — NC — — No Connection

TABLE 3-1: PINOUT DESCRIPTION (CONTINUED)Pin Number

Sym

Pin

Standard Function

TC1270A (Push-Pull, active-low)

TC1270AN (Open-Drain, active-low)

TC1271A (Push-Pull, active-high)

SOT-

23-5

SOT-

143-

4

SOT-

23-5

SOT-

143-

4

SOT-

23-5

SOT-

143-

4

Type Buffer / Driver

Note 1: The MR pin has an internal weak pull-up (18.5 k typical).


TC1270A/70AN/71A

4.0 DEVICE OPERATION

4.1 General DescriptionFor many of today’s microcontroller applications, caremust be taken to prevent low-power conditions that cancause many different system problems. The mostcommon causes are brown-out conditions, where thesystem supply drops below the operating levelmomentarily. The second most common cause is whena slowly decaying power supply causes themicrocontroller to begin executing instructions withoutsufficient voltage to sustain volatile memory (RAM),thus producing indeterminate results.

The TC127XA family (TC1270A, TC1270AN andTC1271A) are cost-effective voltage supervisordevices designed to keep a microcontroller in Resetuntil the system voltage has reached and stabilized atthe proper level for reliable system operation. Thesedevices also operate as protection from brown-outconditions when the system supply voltage dropsbelow a safe operating level.

A Manual Reset input (MR pin) is provided. This allowsa push button switch to be directly connected to theTC127XA device, and is suitable for use as a pushbutton Reset. This allows the system to easily be resetfrom the external control of the push button switch. Noexternal components are required.

The Reset pin (RST or RST) will be forced active, if anyof the following occur:

• During device power-up• VDD goes below the device threshold voltage• The Manual Reset input (MR) goes low

Figure 4-1 shows a high level block diagram of thedevices. The device can be described with threefunctional blocks. These are:

• Voltage detect circuit • Manual Reset with glitch filter circuit • Reset generator circuit

The Reset generator circuit controls the Reset delaytime of the Reset output signal.

There are three Reset Delay Timer options. Dependingon the option, the Reset signal (RST/RST pin) will beheld active for a minimum of 1.09 ms, 17.5 ms, or140 ms.

The TC1271A has an active-high RST output while theTC1270A and TC1270AN have an active-low RSToutput.

The TC1270A and TC1271A have a push-pull outputdriver, while the TC1270AN has an open-drain output.

Figure 4-2 shows a typical circuit for a push-pull deviceand Figure 4-3 shows a typical circuit for an open-draindevice.

FIGURE 4-1: TC127XA High Level Block Diagram.

FIGURE 4-2: Typical Push-Pull Application Circuit.

FIGURE 4-3: Typical Open-Drain Application Circuit.The TC1270A and TC1271A devices are available in a4-Pin SOT-143 package (to maintain footprintcompatibility with the TC1270, TC1271, TCM811 andTCM812 devices) and a SOT-23-5 package. TheTC1270AN is only available in the SOT-23-5 package.

Low supply current makes these devices suitable forbattery-powered applications.

Device specific block diagrams are presented inFigure 4-4 through Figure 4-6.

VDD

MR

RST

RST

VoltageDetect

ResetCircuit

Manual Resetwith Glitch

Filter Circuit

GeneratorCircuit

or

VRST

MRRST

PushButton

MR

VSS VSS

VDDVDD

Reset Input

TC1270A/1A

VDD

0.1 µF

RST or

RST

PushButton

MR

VSS VSS

VDDVDD

RST Reset Input

TC1270AN

VDD

0.1 µF


TC1270A/70AN/71A

FIGURE 4-4: TC1270A Block Diagram.

FIGURE 4-5: TC1270AN Block Diagram.

FIGURE 4-6: TC1271A Block Diagram.

4.2 Voltage Detect CircuitThe voltage detect circuit monitors VDD. The device’sReset voltage trip point (VTRIP) is selected when thedevice is ordered. The voltage on the device’s VDD pindetermines the output state of the RST/RST pin.

VDD voltages above the VTRIP(MAX) force the RST/RSTpin inactive. VDD voltages below the VTRIP(MIN) forcethe RST/RST pin active. The state of the RST/RST pinis unknown for VDD voltages between VTRIP(MAX) andVTRIP(MIN). This is shown in Table 4-1

TABLE 4-1: VDD LEVELS TO RST/RST OUTPUT STATES

The term VTRIP will be used as the general term for thetrip point voltage where the device actually trips.

In the case where VDD is falling (for voltages startingabove VTRIP(MAX)):

• Voltages above VTRIP(MAX) will never cause the RST/RST output pin to be driven active.

• Voltages below VTRIP(MIN) will always cause the RST/RST output pin to be driven active.

In the case where VDD is rising (for voltages startingbelow VTRIP(MIN)):

• Voltages above VTRIP(MAX) will always cause the RST/RST output pin to be driven inactive, (or floated, in the TC1270AN) after the Reset Delay Timer (tRST), times out.

VDD

Comparator+

–

OutputDriver

RSTReference

Noise FilterMR

Voltage Delay

(Push-Pull)

VDD

Comparator+

–RST

Reference

VSSNoise Filter

MR

Voltage Delay

OutputDriver(Open-Drain)

VDD

Comparator+

–RST

Reference

Noise FilterMR

Voltage Delay

OutputDriver(Push-Pull)

VDD Voltage LevelOutput State

RST RST

VDD VTRIP(MAX) H(1, 2) L(1)

VTRIP(MIN) < VDD < VTRIP(MAX) U U

VDD VTRIP(MIN) L H

Legend: H = Driven High L = Driven LowU = Unknown, driven either High or Low

Note 1: The RST/RST pin will be driven inactive after the Reset Delay Timer (tRST) times out.

2: The TC1270AN RST pin will be floated after the Reset Delay Timer (tRST) times out.


TC1270A/70AN/71A

Table 4-2 shows the various device trip point optionsand their VTRIP(MAX) and VTRIP(MIN) voltages. The neg-ative percentage change from common regulatedvoltages is also shown.

If the VDD is falling from the regulated voltage as itcrosses the VTRIP voltage, the RST/RST pin is drivenactive. Then, the desired circuitry is forced into Reset,or the circuitry has the indication that the VDD is belowthe selected VTRIP.

If the VDD is rising as it crosses the VTRIP voltage, theRST/RST pin is driven inactive after the Reset DelayTimer elapses. Then, the desired circuitry is releasedfrom Reset and will start to operate in its Normal mode,or the circuitry has the indication that the VDD is abovethe selected VTRIP.

TABLE 4-2: SELECTING THE TRIP POINT

The TC1270A/TC1270AN/TC1271A devices areoptimized to reject fast transient glitches on the VDDline. If the low input signal (which is below VTRIP) is notrejected, the Reset output is driven active within 50 µsof VDD falling through the Reset voltage threshold.

After the device exits the Reset condition, the delaycircuitry will hold the RST/RST pin active until theappropriate Reset delay time (tRST) has elapsed.

During device power-up, the input voltage is below thetrip point voltage. The device must enter the valid oper-ating range for the device to start operation.

4.2.1 HYSTERESISThere is also a minimal hysteresis (VHYS) on the trippoint. This is so that small noise signals on the devicevoltage (VDD) do not cause the Reset pin (RST/RST) to“jitter” (oscillate between active and inactive levels).

The characterization graphs shown in Figures 2-13through 2-15 show the device hysteresis as apercentage of the voltage trip point (VTRIP).

The Reset Delay Timer (tRST) gives a time-basedhysteresis for the system.

4.2.2 POWER-UP/RISING VDD As the device VDD rises, the device’s Reset circuit willremain active until the voltage rises above the “actual”trip point (VTRIP).

Figure 4-7 shows a power-up sequence and thewaveform of the RST and RST pins. As the devicepowers up, the voltage will start below the validoperating voltage of the device. At this voltage, theRST/RST output is not valid. Once the voltage is abovethe minimum operating voltage (1V) and below theselected VTRIP, the Reset output will be active.

Once the device voltage rises above the VTRIP voltage,the Reset Delay Timer (tRST) starts. When the ResetDelay Timer times out, the Reset output (RST/RST) isdriven inactive.

FIGURE 4-7: RST/RST Pin Operation Power-up.

Trip Voltage

Selection

VTRIP(MAX)(1)/ VTRIP(MIN)(2)

- % From Regulated Voltage

5.0V 3.3V 3.0V

L 4.75V 5.0% — —4.50V 10.0% — —

M 4.50V 10.0% — —4.25V 15.0% — —

T 3.15V — 4.5% —3.00V — 9.2% —

S 3.00V — 9.2% —2.85V — 13.7% —

R 2.70V — — 10.0%2.55V — — 15.0%

Note 1: Voltage regulator circuit must have tighter tolerance (%) than VTRIP(MAX)% from regulated voltage.

2: Circuitry being reset must have a wider tolerance (%) than VTRIP(MIN)% from regulated voltage.

VTRIP

1VVDD tRST(1)

RST(2)

RST

Note 1: Additional system current is consumedduring the tRST time.

2: The TC1270AN requires an externalpull-up resistor.


TC1270A/70AN/71A

4.2.3 POWER-DOWN/BROWN-OUTAs the device powers-down/browns-out, the VDD fallsfrom a voltage above the devices trip point (VTRIP). Thedevice will trip at a voltage between the maximum trippoint (VTRIP(MAX)) and the minimum trip point(VTRIP(MIN)). Once the device voltage (VDD) goesbelow this voltage, the RST/RST pin will be forced tothe active state. Table 4-3 shows the state of the RSTor RST pins.

Figure 4-8 shows the waveform of the RST pin asdetermined by the VDD voltage. As the VDD voltage fallsfrom the normal operating point, the device “enters”Reset by crossing the VTRIP voltage (betweenVTRIP(MAX) and VTRIP(MIN)). Then, when VDD voltagerises, the device “exits” Reset by crossing the VTRIPvoltage (below, or at, VTRIP(MAX)). After the “exit” statehas been detected, the Reset Delay Timer (tRST) starts.When the tRST time completes, the Reset pin is driveninactive.

TABLE 4-3: RESET PIN STATES

FIGURE 4-8: RST Operation as determined by the VTRIP.

DeviceState of RST Pin when: State of RST Pin when:

Output DriverVDD < VTRIP VDD > VTRIP(1) VDD < VTRIP VDD > VTRIP(1)

TC1270A L H — — Push-Pull

TC1271A — — H L Push-Pull

Note 1: The RST/RST pin will be driven inactive after the Reset Delay Timer (tRST) times out.

VDD VTRIP

RST(1)

1V

< 1V is outside the device specificationstRD

tRST

tRD tRST

VTRIP

(with VDD Falling)

(with VDD Rising)

Note 1: The TC1270AN requires an external pull-up resistor.


TC1270A/70AN/71A

4.3 Negative-Going VDD TransientsThe minimum pulse width (time) required to cause aReset may be an important criteria in theimplementation of a Power-on Reset (POR) circuit.This time is referred to as transient duration. TheTC127XA devices are designed to reject a level ofnegative-going transients (glitches) on the powersupply line.

Transient duration is the amount of time needed forthese supervisory devices to respond to a drop in VDD.The transient duration time (tTRAN) is dependent on themagnitude of VTRIP – VDD (overdrive). Any combinationof duration and overdrive that lies under the duration/overdrive curve will not generate a Reset signal.Generally speaking, the transient duration timedecreases with an increase in the VTRIP – VDD voltage.

Figure 4-9 shows an example transient duration vs.Reset comparator overdrive. It shows that the fartherbelow the trip point the transient pulse goes, the shorterthe duration of the pulse required to cause a Resetgets. So, any combination of duration and overdrivethat lays under the curve will not generate a Resetsignal. Combinations above the curve are detected asa brown-out or power-down.

Transient immunity can be improved by adding abypass capacitor (typically 0.1 µF) as close as possibleto the VDD pin of the TC127XA device.

FIGURE 4-9: Example of Typical Transient Duration Waveform.

4.4 Manual Reset with Glitch Filter Circuit

The Manual Reset input pin (MR) allows the Reset pins(RST/RST) to be manually forced to their active states.The MR pin has circuitry to filter noise pulses that maybe present on the pin. Figure 4-10 shows a blockdiagram for using the TC127XA with a push buttonswitch. To minimize the required external components,the MR input has an internal pull-up resistor.

A mechanical push button or active logic signal candrive the MR input.

Once MR has been low for a time, tMD (the manualReset delay time), the Reset output pins are forcedactive. The Reset output pins will remain in their activestates for the Reset Delay Timer time-out period (tRST).

Figure 4-11 shows a waveform for the manual Resetswitch input and the Reset pins output.

FIGURE 4-10: Push Button Reset.

FIGURE 4-11: MR Input – Push Button.

4.4.1 NOISE FILTERThe noise filter filters out noise spikes (glitches) on theManual Reset pin (MR). Noise spikes less than 100 ns(typical) are filtered.

Time (µs)0V

Supp

ly V

olta

ge

5V

VTRIP(MIN) - VDD

tTRAN (Duration)

VTRIP(MAX)VTRIP(MIN)

(Overdrive)

Transient Overdrive Voltage (mV)

Tran

sien

t Dur

atio

n (m

s)

Area below curve will not generate a Reset signal

Area above curve will generate a Reset signal

VDD

MR

VSSRST MCLR

+5V

TC127XA PIC® MCU

RST

VIL

tMR

RST

tMD

VIH

tRST

MR

The MR input typically ignores input pulsesof 100 ns.


TC1270A/70AN/71A

4.5 Reset Generator CircuitThe output signals from the voltage detect circuit andthe manual Reset with glitch filter circuit are OR’dtogether and used to activate the Reset generatormodule.

After the Reset conditions have been removed (the MRpin is no longer forced low and the input voltage isgreater than the trip point voltage), the Reset generatorcircuit determines the Reset delay time-out required.

There are three options for the delay circuit. These are:

• 2.19 ms (typical) delay• 35 ms (typical) delay• 280 ms (typical) delay

4.5.1 RESET DELAY TIMERThe Reset Delay Timer ensures that the TC127XAdevice will “hold” the embedded system in Reset untilthe system voltage has stabilized. The Reset DelayTimer time-out is shown in Table 4-4.

The Reset Delay Timer starts when the voltage detectcircuit output AND the manual Reset with glitch filtercircuit output become inactive. While the Reset DelayTimer is active, the RST or RST pin is driven to theactive state. When the Reset Delay Timer times out,the RST or RST pin is driven inactive.

The Reset Delay Timer (tRST) starts after the devicevoltage rises above the “actual” trip point (VTRIP).When the Reset Delay Timer times out, the Reset out-put pin (RST/RST) is driven inactive.

The Reset Delay Timer is cleared if either, or both, thevoltage detector circuit output and the manual Resetwith glitch filter circuit output become active. The RSTor RST pin continues to be driven to the active state.

Figure 4-12 illustrates when the Reset Delay Timer(tRST) is active or inactive.

4.5.2 EFFECT OF TEMPERATURE ON RESET POWER-UP TIMER (tRPU)

The Reset Delay Timer time-out period (tRST)determines how long the device remains in the Resetcondition. This time out is affected by the device VDDand the temperature. Typical responses for varyingVDD values and temperatures are presented inFigures 2-28, 2-29 and 2-30.

TABLE 4-4: RESET DELAY TIMER TIME OUTS

FIGURE 4-12: Reset Power-up Timer Waveform.

tRSTUnits

Min Typ Max

1.09 2.19 4.38 ms17.5 35 70 ms140 280 560 ms

This is the minimum time that the Reset Delay Timer will “hold”

the Reset pin active after VDD

rises above VTRIP

This is the maximum time that

the Reset Delay Timer will “hold”

the Reset pin active after VDD

rises above VTRIP

Note 1: Shaded rows are custom-ordered time outs.

VTRIP

VDD

RST tRST

Reset DelayTimer Inactive

ResetDelayTimerInactiveR

eset

Del

ayTi

mer

Act

ive

See Figures 2-9,2-7 and 2-8

See Figures 2-12, 2-11 and 2-10

See Figures 2-9,2-7 and 2-8


TC1270A/70AN/71A

5.0 APPLICATION INFORMATIONThis section presents application-related informationthat may be useful for your particular design require-ments.

5.1 Supply Monitor Noise SensitivityThe TC127XA devices are optimized for fast responsesto negative-going changes in VDD. A system with aninordinate amount of electrical noise on VDD (such as asystem using relays) may require a 0.01 µF or 0.1 µFbypass capacitor to reduce detection sensitivity. Thiscapacitor should be installed as close to the TC127XAas possible to keep the capacitor lead length short.

FIGURE 5-1: Typical Application Circuit with Bypass Capacitor.

5.2 Conventional Voltage MonitoringFigure 5-2 and Figure 5-3 show the TC127XA inconventional voltage monitoring applications.

FIGURE 5-2: Battery Voltage Monitor.

FIGURE 5-3: Power Good Monitor.

5.3 Using in PIC® Microcontroller, ICSP™ Applications

Figure 5-4 shows the typical application circuit for usingthe TC1270AN for voltage supervisory function whenthe PIC microcontroller will be programmed via theIn-Circuit Serial Programming™ (ICSP™) feature.Additional information is available in the MicrochipTechnical Brief TB087, “Using Voltage Supervisors withPICmicro® Microcontroller Systems which ImplementIn-Circuit Serial Programming™” (DS91087).

FIGURE 5-4: Typical Application Circuit for PIC Microcontroller with the ICSP Feature.

TC127XAVDD

RST

VSS

0.1 µF

RSTMR

VDD

RST

VSS

BATLOWTC127XA

+

––

VDD

RST

VSS

Power GoodTC127XA

+

–

PwrSply

Note: This operation can only be done using thedevice that has an Open-Drain RST pin(TC1270AN).

Note: It is recommended that the current into theRST pin is current that is limited by a 1 kresistor.

TC1270ANVDD

VDD/VPP

VDD

RSTMCLR Reset input) (Active-Low)

VSS VSS

PIC®Microcontroller

RPU0.1 µF

1 k


TC1270A/70AN/71A

5.4 Modifying The Trip Point, VTRIPAlthough the TC127XA device has a fixed voltage trippoint (VTRIP), it can be necessary to make customadjustments. This is accomplished by connecting anexternal resistor divider to the TC127XA VDD pin. Thiscauses the VSOURCE voltage to be higher than it iswhen the TC127XA input equals its VTRIP voltage(Figure 5-5).

To maintain detector accuracy, the bleeder currentthrough the divider should be significantly higher thanthe 15 µA maximum operating current required by theTC127XA. A reasonable value for this bleeder currentis 1 mA (67 times the 10 µA required by the TC127XA).For example, if VTRIP = 2V and the desired trip point is2.5V, the value of R1 + R2 is 2.5 k (2.5V/1 mA). Thevalue of R1 + R2 can be rounded to the neareststandard value and plugged into the equation shown inFigure 5-5 to calculate values for R1 and R2.

1% tolerance resistors are recommended.

FIGURE 5-5: Modifying Trip-Point using External Resistor Divider.

5.5 MOSFET Low-Drive ProtectionLow operating power and small physical size make theTC1270AN series ideal for many voltage detectorapplications. Figure 5-6 shows a low-voltage gate driveprotection circuit that prevents the logic-level MOSFETfrom overheating due to insufficient gate voltage. Whenthe input signal is below the threshold of theTC1270AN, its output grounds the gate of theMOSFET.

FIGURE 5-6: MOSFET Low-Drive Protection.

TC127XAVDD RST

VSSR1

VSOURCE

R2

or RST

VSOURCE

R1R1 R2+-------------------- VTRIP

Where:

Note: In this example, VSOURCE must be greater than VTRIP.

VSOURCE = Voltage to be monitoredVTRIP = Threshold Voltage setting

VDD

RST

VSS

TC1270AN

270(1)

MTP3055EL

VDD

RL

VTRIP

Note 1: This resistance should be sized appro-priately for the selected trip point volt-age related to the VOL operation.


TC1270A/70AN/71A

5.6 Controllers and Processors With

Bidirectional I/O PinsSome microcontrollers have bidirectional Reset pins.Depending on the current drive capability of thecontroller pin, an indeterminate logic level may result ifthere is a logic conflict. This can be avoided by addinga 4.7 k resistor in series with the output of theTC127XA (Figure 5-7). If there are other componentsin the system that require a Reset signal, they shouldbe buffered so as not to load the Reset line. If the othercomponents are required to follow the Reset I/O of themicrocontroller, the buffer should be connected asshown with the solid line.

FIGURE 5-7: Interfacing the TC1270A or TC1271A Push-Pull Output to a Bidirectional Reset I/O pin.

5.7 Migration PathsFigure 5-8 shows the 5-pin SOT-23 footprint of theTC1270A, TC1270AN and TC1271A devices. Devicesthat are in the 3-pin SOT-23 package could be used inthat circuit with the loss of manual Reset functionality.Examples of compatible footprint devices in the SOT-23-3 package are the MCP111, MCP112, TC54 andTC51 devices. This allows the system to be designedto offer a “base” functionality and a higher end systemwith the “enhanced” functionality, which includes amanual Reset.

FIGURE 5-8: SOT-23 5-pin to 3-pin Comparison.

5.8 Reset Signal Integrity During Power-Down

The TC1270A and TC1271A Reset output is validdown to VDD = 1.0V. Below this voltage the outputbecomes an “open circuit” and does not sink current.This means CMOS logic inputs to the microcontrollerwill be floating at an undetermined voltage. Most digitalsystems are completely shut down well above this volt-age. However, in situations where the Reset signalmust be maintained valid to VDD = 0V, external circuitryis required.

For devices where the Reset signal is active-low, apull-down resistor must be connected from theTC1270A RST pin to ground to discharge straycapacitances and hold the output low (Figure 5-9).

Similarly for devices where the Reset signal isactive-high, a pull-up resistor to VDD is required toensure a valid high RST signal for VDD below 1.0V(Figure 5-10).

This resistor value, though not critical, should bechosen such that it does not appreciably load the Resetpin under normal operation (100 k should be suitablefor most applications).

FIGURE 5-9: Ensuring a valid active-low Reset pin output state as VDD approaches 0V.

FIGURE 5-10: Ensuring a valid active-high Reset pin output state as VDD approaches 0V.

MR

VSS VSS

VDDVDD

RST Reset I/O

TC1270A/71A

VDD

orRST

BufferedReset tosystem

4.7 k

3

2

1

SOT-23-3

1

2

3

5

4

SOT-23-5

NC

VDDMR

RST

VSS VSS

VDD

orRST

RSTorRST

MR

VSS

VDD

RST

TC1270A

VDD

R1100 k

MR

VSS

VDD

RST

TC1271A

VDD

R1100 k


TC1270A/70AN/71A

NOTES:


TC1270A/70AN/71A

6.0 STANDARD DEVICES Table 6-1 shows the standard devices, with ordernumbers, as well as the corresponding configurations.

Configurations can include the following options:

• Voltage Trip Point (VTRIP)• Reset Time Out (tRST)

TABLE 6-1: STANDARD VERSIONS

Device

Reset Threshold (V) Reset Time Out (ms)

Pack

age

Order Number ReplacesM

inim

um

Typi

cal

Max

imum

Cod

e

Min

imum

Typi

cal

Max

imum

Cod

e(1)

TC1270A 4.50 4.63 4.75 L 140 280 560 “blank”SOT-23-5 TC1270ALVCTTR —

SOT-143 TC1270ALVRCTR TC1270LERC/ TCM811LERC

TC1270A 4.25 4.38 4.50 M 140 280 560 “blank”SOT-23-5 TC1270AMVCTTR —

SOT-143 TC1270AMVRCTR TC1270MERC/ TCM811MERC

TC1270A 3.00 3.08 3.15 T 140 280 560 “blank”SOT-23-5 TC1270ATVCTTR —

SOT-143 TC1270ATVRCTR TC1270TERC/ TCM811TERC

TC1270A 2.85 2.93 3.00 S 140 280 560 “blank”SOT-23-5 TC1270ASVCTTR —

SOT-143 TC1270ASVRCTR TC1270SERC/ TCM811SERC

TC1270A 2.55 2.63 2.70 R 140 280 560 “blank”SOT-23-5 TC1270ARVCTTR —

SOT-143 TC1270ARVRCTR TC1270RERC/ TCM811RERC

TC1270AN 4.50 4.63 4.75 L 140 280 560 “blank”SOT-23-5 TC1270ANLVCTTR —SOT-143 TC1270ANLVRCTR —

TC1270AN 4.25 4.38 4.50 M 140 280 560 “blank”SOT-23-5 TC1270ANMVCTTR —SOT-143 TC1270ANMVRCTR —

TC1270AN 3.00 3.08 3.15 T 140 280 560 “blank”SOT-23-5 TC1270ANTVCTTR —SOT-143 TC1270ANTVRCTR —

TC1270AN 2.85 2.93 3.00 S 140 280 560 “blank”SOT-23-5 TC1270ANSVCTTR —SOT-143 TC1270ANSVRCTR —

TC1270AN 2.55 2.63 2.70 R 140 280 560 “blank”SOT-23-5 TC1270ANRVCTTR —SOT-143 TC1270ANRVRCTR —

TC1271A 4.50 4.63 4.75 L 140 280 560 “blank”SOT-23-5 TC1271ALVCTTR —

SOT-143 TC1271ALVRCTR TC1271LERC/ TCM812LERC

TC1271A 4.25 4.38 4.50 M 140 280 560 “blank”SOT-23-5 TC1271AMVCTTR —

SOT-143 TC1271AMVRCTR TC1271MERC/ TCM812MERC

TC1271A 3.00 3.08 3.15 T 140 280 560 “blank”SOT-23-5 TC1271ATVCTTR —

SOT-143 TC1271ATVRCTR TC1271TERC/ TCM812TERC

TC1271A 2.85 2.93 3.00 S 140 280 560 “blank”SOT-23-5 TC1271ASVCTTR —

SOT-143 TC1271ASVRCTR TC1271SERC/ TCM812SERC

TC1271A 2.55 2.63 2.70 R 140 280 560 “blank”SOT-23-5 TC1271ARVCTTR —

SOT-143 TC1271ARVRCTR TC1271RERC/ TCM812RERCNote 1: “A” time-out delay options are only standard in the SOT-23-5 package. SOT-143 package is a custom request.


TC1270A/70AN/71A

NOTES:


TC1270A/70AN/71A

7.0 CUSTOM CONFIGURATIONSThe following Custom Reset Trip Point is available (seeTable 7-1).

TABLE 7-1: CUSTOM TRIP POINT

Table 7-2 shows the codes that specify the desiredReset time out (tRST) for custom devices.

TABLE 7-2: DELAY TIME OUT ORDERING CODES

Trip Voltage

Selection

VTRIP(MAX)/VTRIP(MIN)

- % From Regulated Voltage

3.0V(1) 2.85V 5.0%

2.70V 10.0%Note 1: Contact your local Microchip sales office

for additional information.

Code Reset Delay Time (Typ) (ms)

Comment

A 35 Note 1B 2.19 Note 1

“blank” 280 Delay timings for standard device offeringsNote 1: This delay timing option is not the standard offering. For information on ordering devices with these delay

times, contact your local Microchip sales office. Minimum purchase volumes are required.


TC1270A/70AN/71A

NOTES:


TC1270A/70AN/71A

8.0 DEVELOPMENT TOOLS

8.1 Evaluation/Demonstration BoardsThe SOT-23-5/6 Evaluation Board (VSUPEV2) can beused to evaluate the characteristics of the TC127XAdevices.

This blank PCB has footprints for:

• Pull-up Resistor• Pull-down Resistor• Loading Capacitor• In-line Resistor

There is also a power supply filtering capacitor.

For evaluating the TC127XA devices, the selecteddevice should be installed into the Option A footprint.

FIGURE 8-1: SOT-23-5/6 Voltage Supervisor Evaluation Board (VSUPEV2).

The SOIC-14 Evaluation Board (SOIC14EV) has aSOT-23-6 footprint that can be jumpered into any por-tion of the circuit. This will allow any footprint that theTC1270A requires in the SOT-23-5 package.

FIGURE 8-2: SOIC-14 Evaluation Board (Microchip Part Number SOIC14EV).The PCB number, 102-00094, appears on the lower leftside of the board. These evaluation boards can be pur-chased directly from the Microchip web site atwww.microchip.com.


TC1270A/70AN/71A

NOTES:


TC1270A/70AN/71A

9.0 PACKAGING INFORMATION

9.1 Package Marking Information

5-Pin SOT-23

Part Number Code Part Number Code

TC1270ALVCTTR F1NN TC1271ALVCTTR J1NNTC1270AMVCTTR F2NN TC1271AMVCTTR J2NNTC1270ATVCTTR F3NN TC1271ATVCTTR J3NNTC1270ASVCTTR F4NN TC1271ASVCTTR J4NNTC1270ARVCTTR F5NN TC1271ARVCTTR J5NNTC1270ANLVCTTR FSNNTC1270ANMVCTTR FTNNTC1270ANTVCTTR FUNNTC1270ANSVCTTR FVNNTC1270ANRVCTTR FWNN

Example:

Legend: XX...X Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week ‘01’)NN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn)* This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it willbe carried over to the next line, thus limiting the number of availablecharacters for customer-specific information.

3e

3e

XXNN F125

4-Lead SOT-143

XXNN

Example:

C125

Part Number Code Part Number Code

TC1270ALVRCTR D1NN TC1271ALVRCTR C1NNTC1270AMVRCTR D2NN TC1271AMVRCTR C2NNTC1270ATVRCTR D3NN TC1271ATVRCTR C3NNTC1270ASVRCTR D4NN TC1271ASVRCTR C4NNTC1270ARVRCTR D5NN TC1271ARVRCTR C5NNTC1270ANLVRCTR E1NNTC1270ANMVRCTR E2NNTC1270ANTVRCTR E3NNTC1270ANSVRCTR E4NNTC1270ANRVRCTR E5NN


TC1270A/70AN/71A

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TC1270A/70AN/71A

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Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging


TC1270A/70AN/71A

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TC1270A/70AN/71A

9.2 Product Tape and Reel Specifications

FIGURE 9-1: EMBOSSED CARRIER DIMENSIONS (8 MM TAPE ONLY)

FIGURE 9-2: 5-LEAD SOT-23 DEVICE TAPE AND REEL SPECIFICATIONS

TABLE 1: CARRIER TAPE/CAVITY DIMENSIONS

Case Outline

Package Type

Carrier Dimensions

Cavity Dimensions Output

QuantityUnits

Reel Diameter in

mmWmm

Pmm

A0mm

B0mm

K0mm

CT SOT-23 5L 8 4 3.23 3.17 1.37 3000 180RC SOT-143 4L 8 4 3.1 2.69 1.3 3000 330


TC1270A/70AN/71A

FIGURE 9-3: 4-LEAD SOT-143 DEVICE TAPE AND REEL SPECIFICATIONS

Component Taping Orientation for 4-Pin SOT-143 Devices

Carrier Tape, Number of Components Per Reel and Reel Size:

Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size

4-Pin SOT-143 8 mm 4 mm 3000 7 in.


TC1270A/70AN/71A

NOTES:


TC1270A/70AN/71A

APPENDIX A: REVISION HISTORY

Revision D (August 2011)The following is the list of modifications:

1. Added the SOT-143 package to the TC1270ANdevice and related information throughout thedocument.

Revision C (October 2010)The following is the list of modifications:

1. Modified the Product Identification Systemsection to reflect the custom manufacturingcode used for devices with a Reset Delay timeout of 35 ms (was a “C”, now is an “A”).

2. Clarified information presented in Section 4.2“Voltage Detect Circuit” (page 21).

Revision B (June 2007)The following is the list of modifications:

1. Added new options:- Open-Drain output- New Reset Delay time outs.

2. Updated Package Outline Drawings3. Updated Revision History4. Added new options to Product Identification

System

Revision A (March 2007)• Original Release of this Document.


TC1270A/70AN/71A

NOTES:


TC1270A/70AN/71A

PRODUCT IDENTIFICATION SYSTEMTo order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Device: TC1270A: Voltage Supervisor with Manual Reset

TC1270AN: Voltage Supervisor with Manual ResetTC1271A: Voltage Supervisor with Manual Reset

VTRIP Options: R = 2.55V (min.) / 2.63V (typ.) / 2.70V (max.)S = 2.85V (min.) / 2.93V (typ.) / 3.00V (max.)T = 3.00V (min.) / 3.08V (typ.) / 3.15V (max.)M = 4.25V (min.) / 4.38V (typ.) / 4.50V (max.)L = 4.50V (min.) / 4.63V (typ.) / 4.75V (max.)

Time-Out Options: “blank” = tRST = 280 ms (typ)A = tRST = 35 ms (typ)B = tRST = 2.19 ms (typ)

Temperature Range: V = -40°C to +125°C

Package: CT = Plastic Small Outline Transistor, SOT-23, 5-leadRC = Plastic Small Outline Transistor, SOT-143,

4-lead

Tape/Reel Option: TR = Tape and Reel

Examples:a) TC1270ASVCTTR:

2.85V min./2.93V typ./3.00V max.voltage trip point, Push-pull active-low Reset, Reset Delay Timer = 280 ms, 5-LD SOT-23, Tape and Reel, -40°C to +125°C

b) TC1270ALVRCTR: 4.50V min./4.63V typ./4.75V max.voltage trip point, Push-pull active-low Reset, Reset Delay Timer = 280 ms, 4-LD SOT-143, Tape and Reel,-40°C to +125°C

c) TC1270ANMBVCTTR: 4.25V min./4.38V typ./4.50V max.Open-drain active-low Reset, Reset Delay Timer = 2.19 ms, 5-Lead SOT-23, Tape and Reel, -40°C to +125°C

d) TC1270ANLAVCT: 4.50V min./4.63V typ./4.75V max. Open-drain active-low Reset, Reset Delay Timer = 35 ms, 5-Lead SOT-23, -40°C to +125°C

e) TC1271ARVCTTR: 2.55V min./2.63V typ./2.70V max.voltage trip point, Push-pull active-high Reset, Reset Delay Timer = 280 ms, 5-LD SOT-23, Tape and Reel, -40°C to +125°C

f) TC1271ATVRCTR: 3.00V min./3.08V typ./3.15V max.voltage trip point, Push-pull active-high Reset, Reset Delay Timer = 280 ms, 4-LD SOT-143, Tape and Reel,-40°C to +125°C

PART NO. XX X

TemperatureVTRIPOptions

DeviceRange

XX

Package

X

Tape/ReelOption

X

Reset DelayOptions


TC1270A/70AN/71A

NOTES:


Note the following details of the code protection feature on Microchip devices:• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyer’s risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights.

2007-2011 Microchip Technology Inc.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

© 2007-2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.

Printed on recycled paper.

ISBN: 978-1-61341-466-8

DS22035D-page 47

Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.


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1.0 Electrical Characteristics1.1 AC CharacteristicsFIGURE 1-1: Test Load Conditions.

2.0 Typical Performance CurvesFIGURE 2-1: IDD vs. Temperature (Reset Power-up Timer Inactive) (TC1270AL, TC1270ANL, TC1271AL - 4.50V min./4.63V typ./4.75V max.).FIGURE 2-2: IDD vs. Temperature (Reset Power-up Timer Inactive) (TC1270AT, TC1270ANT, TC1271AT - 3.00V min./3.08V typ./3.15V max.).FIGURE 2-3: IDD vs. Temperature (Reset Power-up Timer Inactive) (TC1270AR, TC1270ANR, TC1271AR - 2.55V min./2.63V typ./2.70V max.).FIGURE 2-4: IDD vs. Temperature (Reset Power-up Timer Active) (TC1270AL, TC1270ANL, TC1271AL - 4.50V min./4.63V typ./4.75V max.).FIGURE 2-5: IDD vs. Temperature (Reset Power-up Timer Active) (TC1270AT, TC1270ANT, TC1271AT - 3.00V min./3.08V typ./3.15V max.).FIGURE 2-6: IDD vs. Temperature (Reset Power-up Timer Active) (TC1270AR, TC1270ANR, TC1271AR - 2.55V min./2.63V typ./2.70V max.).FIGURE 2-7: IDD vs. VDD (Reset Power-up Timer Inactive) (TC1270AL, TC1270ANL, TC1271AL - 4.50V min./4.63V typ./4.75V max.).FIGURE 2-8: IDD vs. VDD (Reset Power-up Timer Inactive) (TC1270AT, TC1270ANT, TC1271AT - 3.00V min./3.08V typ./3.15V max.).FIGURE 2-9: IDD vs. VDD (Reset Power-up Timer Inactive) (TC1270AR, TC1270ANR, TC1271AR - 2.55V min./2.63V typ./2.70V max.).FIGURE 2-10: IDD vs. VDD (Reset Power-up Timer Active) (TC1270AL, TC1270ANL, TC1271AL - 4.50V min./4.63V typ./4.75V max.).FIGURE 2-11: IDD vs. VDD (Reset Power-up Timer Active) (TC1270AT, TC1270ANT, TC1271AT - 3.00V min./3.08V typ./3.15V max.).FIGURE 2-12: IDD vs. VDD (Reset Power-up Timer Active) (TC1270AR, TC1270ANR, TC1271AR - 2.55V min./2.63V typ./2.70V max.).FIGURE 2-13: VTRIP and VHYS vs. Temperature (TC1270AL, TC1270ANL, TC1271AL - 4.50V min./4.63V typ./4.75V max.).FIGURE 2-14: VTRIP and VHYS vs. Temperature (TC1270AT, TC1270ANT, TC1271AT - 3.00V min./3.08V typ./3.15V max.).FIGURE 2-15: VTRIP and VHYST vs. Temperature (TC1270AR, TC1270ANR, TC1271AR - 2.55V min./2.63V typ./2.70V max.).FIGURE 2-16: VOL vs. IOL (TC1270AL, TC1270ANL, TC1271AL - 4.50V min./4.63V typ./4.75V max.).FIGURE 2-17: VOL vs. IOL (TC1270AT, TC1270ANT, TC1271AT - 3.00V min./3.08V typ./3.15V max.).FIGURE 2-18: VOL vs. IOL (TC1270AR, TC1270ANR, TC1271AR - 2.55V min./2.63V typ./2.70V max.).FIGURE 2-19: VOL vs. Temperature (TC1270AL, TC1270ANL, TC1271AL - 4.50V min./4.63V typ./4.75V max.). @ VDD = 4.5V).FIGURE 2-20: VOL vs. Temperature (TC1270AT, TC1270ANT, TC1271AT - 3.00V min./3.08V typ./3.15V max.). @ VDD = 2.7V).FIGURE 2-21: VOL vs. Temperature (TC1270AR, TC1270ANR, TC1271AR - 2.55V min./2.63V typ./2.70V max.). @ VDD = 1.8V).FIGURE 2-22: VOH vs. IOL (TC1270AL, TC1270ANL, TC1271AL - 4.50V min./4.63V typ./4.75V max.) @ +25°C).FIGURE 2-23: VOH vs. IOH (TC1270AT, TC1270ANT, TC1271AT - 3.00V min./3.08V typ./3.15V max.) @ +25°C).FIGURE 2-24: VOH vs. IOH (TC1270AR, TC1270ANR, TC1271AR - 2.55V min./2.63V typ./2.70V max.) @ +25°C).FIGURE 2-25: VDD Falling to Reset Propagation Delay (tRPD) vs. Temperature (TC1270AL, TC1270ANL, TC1271AL - 4.50V min./4.63V typ./4.75V max.).FIGURE 2-26: VDD Falling to Reset Propagation Delay (tRPD) vs. Temperature (TC1270AT, TC1270ANT, TC1271AT - 3.00V min./3.08V typ./3.15V max.).FIGURE 2-27: VDD Falling to Reset Propagation Delay (tRPD) vs. Temperature (TC1270AR, TC1270ANR, TC1271AR - 2.55V min./2.63V typ./2.70V max.).FIGURE 2-28: Reset Time-Out Period (tRST) vs. Temperature (TC1270AL, TC1270ANL, TC1271AL - 4.50V min./4.63V typ./4.75V max.).FIGURE 2-29: Reset Time-Out Period (tRST) vs. Temperature (TC1270AT, TC1270ANT, TC1271AT - 3.00V min./3.08V typ./3.15V max.).FIGURE 2-30: Reset Time-Out Period (tRST) vs. Temperature (TC1270AR, TC1270ANR, TC1271AR - 2.55V min./2.63V typ./2.70V max.).FIGURE 2-31: Reset Time-Out Period (tRST) (C time out option) vs. Temperature (TC1270AL, TC1270ANL, TC1271AL - 4.50V min./4.63V typ./4.75V max.).FIGURE 2-32: Reset Time-Out Period (tRST) (C time out option) vs. Temperature (TC1270AT, TC1270ANT, TC1271AT - 3.00V min./3.08V typ./3.15V max.).FIGURE 2-33: Reset Time-Out Period (tRST) (C time out option) vs. Temperature (TC1270AR, TC1270ANR, TC1271AR - 2.55V min./2.63V typ./2.70V max.).FIGURE 2-34: Reset Time-Out Period (tRST) (B time out option) vs. Temperature (TC1270AL, TC1270ANL, TC1271AL - 4.50V min./4.63V typ./4.75V max.).FIGURE 2-35: Reset Time-Out Period (tRST) (B time out option) vs. Temperature (TC1270AT, TC1270ANT, TC1271AT - 3.00V min./3.08V typ./3.15V max.).FIGURE 2-36: Reset Time-Out Period (tRST) (B time out option) vs. Temperature (TC1270AR, TC1270ANR, TC1271AR - 2.55V min./2.63V typ./2.70V max.).FIGURE 2-37: MR Low to Reset Propagation Delay (tMD) vs. Temperature (TC1270AL, TC1270ANL, TC1271AL - 4.50V min./4.63V typ./4.75V max.).FIGURE 2-38: MR Low to Reset Propagation Delay (tMD) vs. Temperature (TC1270AT, TC1270ANT, TC1271AT - 3.00V min./3.08V typ./3.15V max.).FIGURE 2-39: MR Low to Reset Propagation Delay (tMD) vs. Temperature (TC1270AR, TC1270ANR, TC1271AR - 2.55V min./2.63V typ./2.70V max.).FIGURE 2-40: VDD Transient Duration vs. Reset Threshold Overdrive (VTRIP (minimum) - VDD).FIGURE 2-41: Open-Drain Leakage Current vs. Voltage Applied to RST Pin (TC1270AR, TC1270ANR, TC1271AR - 2.55V minimum).

3.0 Pin DescriptionsTABLE 3-1: Pinout Description3.1 Ground Terminal (VSS)3.2 Supply Voltage (VDD)3.3 Reset Output (RST and RST)3.4 Manual Reset Input (MR)

4.0 Device Operation4.1 General DescriptionFIGURE 4-1: TC127XA High Level Block Diagram.FIGURE 4-2: Typical Push-Pull Application Circuit.FIGURE 4-3: Typical Open-Drain Application Circuit.FIGURE 4-4: TC1270A Block Diagram.FIGURE 4-5: TC1270AN Block Diagram.FIGURE 4-6: TC1271A Block Diagram.

4.2 Voltage Detect CircuitTABLE 4-1: VDD Levels to RST/RST Output StatesTABLE 4-2: Selecting The Trip PointFIGURE 4-7: RST/RST Pin Operation Power-up.TABLE 4-3: Reset Pin StatesFIGURE 4-8: RST Operation as determined by the VTRIP.

4.3 Negative-Going VDD TransientsFIGURE 4-9: Example of Typical Transient Duration Waveform.

4.4 Manual Reset with Glitch Filter CircuitFIGURE 4-10: Push Button Reset.FIGURE 4-11: MR Input – Push Button.

4.5 Reset Generator CircuitTABLE 4-4: Reset Delay Timer time outsFIGURE 4-12: Reset Power-up Timer Waveform.

5.0 Application Information5.1 Supply Monitor Noise SensitivityFIGURE 5-1: Typical Application Circuit with Bypass Capacitor.

5.2 Conventional Voltage MonitoringFIGURE 5-2: Battery Voltage Monitor.FIGURE 5-3: Power Good Monitor.

5.3 Using in PIC® Microcontroller, ICSP™ ApplicationsFIGURE 5-4: Typical Application Circuit for PIC Microcontroller with the ICSP Feature.

5.4 Modifying The Trip Point, VTRIPFIGURE 5-5: Modifying Trip-Point using External Resistor Divider.

5.5 MOSFET Low-Drive ProtectionFIGURE 5-6: MOSFET Low-Drive Protection.

5.6 Controllers and Processors With Bidirectional I/O PinsFIGURE 5-7: Interfacing the TC1270A or TC1271A Push-Pull Output to a Bidirectional Reset I/O pin.

5.7 Migration PathsFIGURE 5-8: SOT-23 5-pin to 3-pin Comparison.

5.8 Reset Signal Integrity During Power-DownFIGURE 5-9: Ensuring a valid active-low Reset pin output state as VDD approaches 0V.FIGURE 5-10: Ensuring a valid active-high Reset pin output state as VDD approaches 0V.

6.0 Standard DevicesTABLE 6-1: Standard Versions

7.0 Custom ConfigurationsTABLE 7-1: Custom Trip PointTABLE 7-2: dELAY tIME OUT oRDERING cODES

8.0 Development Tools8.1 Evaluation/Demonstration BoardsFIGURE 8-1: SOT-23-5/6 Voltage Supervisor Evaluation Board (VSUPEV2).FIGURE 8-2: SOIC-14 Evaluation Board (Microchip Part Number SOIC14EV).

9.0 Packaging information9.1 Package Marking Information9.2 Product Tape and Reel Specifications

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TC1270A/70AN/71A Voltage Supervisor with Manual Reset Inputww1.microchip.com/downloads/en/DeviceDoc/22035D.pdfTC1270A/70AN/71A DS22035D-page 4 2007-2011 Microchip Technology Inc. Reset