Taming the SEU Beast - Approaches and Results for FPGA ... · To be presented by Melanie Berg at the NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop,

To be presented by Melanie Berg at the NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop, Greenbelt, Maryland, June 28-30, 2011, and published on nepp.nasa.gov.

Taming the SEU Beast - Approaches and Results for FPGA Devices and

How To Apply Them Melanie Berg, MEI Technologies/NASA GSFCM. Friendlich, C. Perez, H. Kim: MEI Technologies/NASA GSFCK. LaBel: NASA GSFC

National Aeronautics and Space Administration

NEPP Electronic Technology WorkshopJune 28-30, 2011

1


Introduction

• Field Programmable Gate Array(FPGA) Single Event Effect (SEE) Models have been developed by NASA/GSFC Radiation Effects and Analysis Group (REAG)– Compartmentalize SEEs to enhance analysis– Uses a top-down approach

• Details of SEE generation and other electrical properties are part of ongoing development

• Presented models are only expected to fit synchronous designs as per NASA design guidelines.

2


Goal:

• Application of the NASA REAG FPGA Single Event Upset (SEU) Cross Section (σSEU) Model to a variety of FPGA types

3

( ) SEFILogicfunctionalionConfiguraterror PfsPPfsP ++∝ )(Probability for Design Specific system SEE:

Probability for Configuration SEE

Probability for Functional logic SEE

Probability for Single Event

functional Interrupt

Top Level Model has 3 major categories of σSEU :


Impact to Community

• Provides a standard method for comparing various types of FPGAs

• Enhances analysis by providing a means for evaluating Single Event Upsets (SEUs) and Single Event Transients (SETs):– Generation– System Propagation– Evaluate effectiveness of mitigation strategies– Determine dominant SEE components– Eases the overall analysis process

• Analysis provides designers with dominant or insignificant susceptible components… enhanced design for radiation strategies

4


Technical Highlights

• This presentation will focus on:– Configuration: Pconfiguration

– Data Path functional logic: PfunctionalLogic

• Model Derivation is presented• Model application to Microsemi FPGAs:

– RTAXs: Embedded Radiation Hardened by Design (RHBD)

– ProASIC3: No embedded mitigation

5

( ) SEFILogicfunctionalionConfiguraterror PfsPPfsP ++∝ )(


Configuration

ionConfiguratP

6


Place, Route, and Gate Utilization are Stored in the FPGA Configuration

• Configuration Defines: Arrangement of pre-existing logic via programmable switches– Functionality (logic cluster)– Connectivity (routes)– Placement

• Programming Switch Types:– Antifuse: One time Programmable (OTP)– SRAM: Reprogrammable (RP)– Flash: Reprogrammable (RP)

7


Programmable Switch Implementation and Single Event Upset (SEU) Susceptibility

ANTIFUSE (OTP)SRAM (RP)

8


Configuration Test and Analysis• Configuration is static during operation… hence we test

and evaluate it staticallyAntifuse SRAM FLASH SEU Hardened

SRAMManufacturer Microsemi

AeroflexXilinxAchronix

Microsemi Xilinx, AcrhonixAtmel

Upset Signature Fuse Resistivity

Bit State Bit State or resistivity

Bit State

Configuration Test

Non-Specific Read-backpost-irradiation

Verify Post-irradiation

Read-back post-irradiation

Information from Configuration Test

N/A Upsetconfiguration bits

Pass/Fail Upset configuration bits

Results No upsets observed

Dominant upsets

Insignificant Low significance

REAG Tested Yes Yes Yes Atmel, AchronixYes/Xilinx No

9


Impact of Configuration Testing and Analysis to the REAG Model

REAG ModelAntifuse

SRAM (non-mitigated)

Flash

Hardened SRAM

( ) SEFILogicfunctionalerror PfsPfsP +∝ )(

( ) ionConfiguraterror PfsP ∝

( ) SEFILogicfunctionalerror PfsPfsP +∝ )(


10


Data Path Functional Logic andConcepts of Synchronous Design

11


Synchronous Design Basic Building Blocks: Combinatorial Logic and Flip-

Flops (DFF’s)

D Q

reset

CLK

DFF: Captures data input at clock edge and is a function of the clock period (τclk)

Q=f(D,τclk)

Combinatorial Logic: Output is a function of the inputs after some

delay(τdly) Output=f(input,τdly)

12


Component Libraries: Basic Designer Building Blocks

• Combinatorial logic blocks Vary in complexity Vary in I/O

• Sequential Memory blocks (Flip-flops or DFFs) Uses global Clocks Uses global ResetsMay have mitigation

13


Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

DQ

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

DQ

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

DFF’s in a Synchronous Design

• All DFFs are connected to a clock• Clock period: τclk• Clock frequency: fs

Clock Tree

DFFs are BOUNDARY POINTs in a synchronous design

fsclk1

=τ

14


Deterministic Data Capture…Adhering to Setup and Hold Time for a DFF

Setup:τsu

Hold:τh

Data Launch from StartPointDFF1

clock

τdly : Data Delay through combinatorial logic and routes

Q

QSET

CLR

D

StartPointDFF1

EndPointDFF2

τdly

τclkQ

QSET

CLR

D

Data Capture is Deterministic when:

τdly

)( jitterskewsuclkdly τττττ ++−<

15


DFFs are boundary pointsTiming is performed from one DFF to the next DFFFor each DFF, data paths are traced backwards to their start-points

Combinatorial logic and routes are part of the delay

Making Setup Time: Static Timing Analysis (STA)

DFF0 DFF1 DFF2 DFF3τdly0 τdly1 τdly2

Shift Register:

DFF0 DFF1τdly01

τdly00

DFF2

τdly02

τdly21

16


Start Point DFFs → End Point DFFs τdly and the “Cone of Logic”

))1(()( −= TStartDFFsfTEndDFF

Referred to as the “Cone of Logic”

TT-1 T+1

Signal will arrive at destination by τdly … but it will not be captured until the next clock edge

τdly τclk

17


System States System state is defined by the logic values within

all DFFs In between clock edges (intermediate points)

Computations are occurring (combinatorial logic) SETs or SEUs can occur

System state is captured at each rising clock edge... after clock cycle computations are completed

Note: Upsets occur at intermediate points. They become part of the system state if they are captured into the next state

18


Synchronous Design Take Away Points

• Basic Blocks: DFFs and Combinatorial logic• DFFs are boundary points

– For each DFF (end point) there is a backwards trace to start point DFFs

– There is delay between start point DFFs and endpoint DFFs

• Combinatorial logic• Routes

• SEE analysis is based on utilized DFFs in a design because an upset is not an upset unless it is captured by a DFF

The question is… If an upset occurs will it reach an endpoint DFF?

19


Data Path Functional Logic

LogicfunctionalP

20


Configuration versus Data Path (Functional Logic) SEE

• Configuration and Functional logic are separate logic

• Can be implemented with different technologies within one device (e.g. antifuse versus CMOS)

• Configuration is static and data paths are not. Requires a different test and analysis approach

21

This explains why there are separate categories of error:

Pconfiguration vs. PfunctionalLogic


Combinatorial SequentialLogic function generation (computation)

Captures and holds state of combinatorial Logic

SET: Glitch in the combinatorial logic: Capture is frequency dependent

SEU: State changes until next cycle of enabled input: Next state capture can be frequency dependent

Primary functional logic components can be classified into:SEU and SET Background

SET effects are nonlinear and are heavily design and state dependent.

SET SEU

22


Data Path Model and DFF Logic Cones

LogicfunctionalfsP )(Probability for

Functional logic SEE

+∃ ∑∑

=→

=→

ialCellsCombinator

iiSEUSET

DFFsStartPo

jjSEUDFFSEUDFF

fsPfsP#

1)(

int#

1)( )()(

Probability for Captured DFF Events

Probability for Captured Combinatorial logic

DFFk Cone of LogicAll Start Point DFFs and Combinatorial Logic gates that feed

into End Point DFF under Evaluation (DFFk):

Evaluate for Each DFF

23


Combinatorial Logic Contribution to System Error in a Synchronous

System: Capturing a SET

PSET→SEU

24


SETs and a Synchronous System

• Generation (Pgen)• Propagation (Pprop)• Logic Masking (Plogic.)• Capture

All Components comprise: PSET→SEU

25


SET Generation: Pgen

• SET generation occurs due to an “off” gate turning “on”.

• A transient in a CMOS circuit will be generated with an amplitude and width (τwidth) based on: – Amount of deposited charge

(i.e. small Linear Energy Transfer (LET) values produce small transients)

– The strength of the gate’s load– The strength of its

complimentary “ON” gate – The dissipation strength of the

process.26

VDD

Current Flows

through On Transistor

Off Transistor isSusceptible

nodenodecrit VCQ *=QcritQcoll >

Collected Charge

Critical Charge

Node Capacitance

Node Voltage


SET Propagation to an EndPoint DFF: Pprop

• In order for the data path SET to become an upset, it must propagate and be captured by its endpoint DFF

• Pprop only pertains to electrical medium (capacitance of path… combinatorial logic and routing) – Capacitive SET amplitude reshaping– Capacitive SET width reshaping– Small SETs or paths with high capcitance have low Pprop

• Pprop heavily contributes to the non-linearity of PSET→SEU because of the variation in path capacitance

27

StartPoint EndPoint


SET Logic Masking: Plogic

• Plogic: Probability that a SET can logically propagate through a cone of logic. Based on state of the combinatorial logic gates and their potential masking.

0<Plogic <1

Determining Plogic for a complex system can be very difficult

0<Plogic <1

“AND” gate reduces probability that SET will logically propagate

28


clk

widthSEUSETclkP

τττ ∝→)(

SET Capture at Destination DFF

Probability of capture is proportional to the width of the transient as seen from the destination DFF

fsfsP widthSEUSET τ∝→)(

Each combinatorial element can generate a transient. The transient width will be a fraction of the clock period for a synchronous design in a CMOS process.

29


LogicfunctionalfsP )(

+∃ ∑∑

=→

=→

ialCellsCombinator

iiSEUSET

DFFsStartPo

jjSEUDFFSEUDFF

fsPfsP#

1)(

int#

1)( )()(

∑=

ialCellsCombinator

iiwidthiicipropigen fsPPP

#

1)()(log)()( τ

∑=

ialCellsCombinator

iiwidthipropigen fsPP

#

1)()()( τUpper Bound SET Plogic=1

Data Path Model and Combinatorial Logic SETs

30


DFF Contribution to System Error in a Synchronous System

PDFFSEU→SEU

31


Conventional Theory:System Upsets Have a Static

Component+Dynamic Component

σ DFF

erro

r

Frequency

( ) SEUSETDFFSEUerror fsPPfsP →+= )(

Composite Cross Section

PDFFSEU & PDFFMBU

Does not fully characterize DFF upsets as they pertain to a synchronous system

Takes into account upsets from combinatorial logic in DFF data path and the DFF potential for flipping its state

32


SEUs and a Synchronous System: New Stuff

• Generation (PDFFSEU)• Pprop=1 for hard state switch• Logic Masking (Plogic.)• Capture

All Components comprise: PDFFSEU→SEU

33


Generation of DFF Upsets: PDFFSEU

• Probability that a DFF will flip its state• Can be a hard flip:

– Will not change until the next clock cycle– Amplitude and width are not affected as with a SET

• Can be a metastable flip– No real defined state– Otherwise known as a “weak” state– Can cause oscillations in the data path

34

PDFFSEU


Generation PDFFSEU versusP(fs)DFFSEU→SEU

35

PDFFSEU P(fs)DFFSEU→SEU

Probability a StartpointDFF becomes upset

Probability that the Startpoint upset is captured by the endpoint DFF

Occurs at some point in time within a clock period

Occurs at a clock edge (capture)

Not frequency dependent Frequency dependent


Logic Masking DFFs… Plogic

• Logic masking for DFF start points is similar to logic masking of combinatorial logic.

• DFF logic masking is generally the point where Triple Modular Redundancy (TMR) is inserted

VoterPlogic=0 for DFFs… their upsets are masked

Plogic>0 for Voter… its upsets are not masked

36


• If a DFF is affected by an SEU it will change its state somewhere within a clock cycle at time τ

DFF Upsets (SEUs) and Next State Capture: PDFFSEU and PDFFSEU→SEU

τclk

Previous State

τclkττ <<0 τ Is defined to be within 1 clock period (τclk)

Will the endpoint DFF capture the upset?

Will the endpoint DFF capture the correct value? OR…


0

11

0

1

SEU Capture Example: Assume τclk=15ns

If DFFD flips its state… 0<τ<(5.5)ns

The upset will get caught… otherwise it’s as if the event never occurred

38

1

0???


Percentage of Clock Cycle for SEU Capture:

dlyclk τττ −<

clk

dlyclk

clk τττ

ττ −

<

clk

dly

clk ττ

ττ

−<1

fsfs dlyττ −<1

Upset is caught within this timeframe

Fraction of clock period for upset

capture

Fraction of clock period for upset capture wrt to

frequency

39



+∃ ∑∑

=→

=→

ialCellsCombinator

iiSEUSET

DFFsStartPo

jjSEUDFFSEUDFF

fsPfsP#

1)(

int#

1)( )()(

)1(int#

1)()(log)(∑

=

−DFFsStartPo

jjdlyjicjDFFSEU fsPP τ

Data Path Upsets and Start Point DFFs

40


Putting it all together:P(fs)functionalLogic=P(fs)DFFSEU→SEU+P(fs)SET→SEU

DFF SEU capture Combinatorial Logic SET capture

DFF SEU capture

41


NASA REAG FPGA Data Path Functional Logic Susceptibility Model


( )SEUSETSEUDFFSEUDFFfsPfsP →→ +∃ )()(

+−∃ ∑∑

==

ialCellsCombinator

iiwidthicipropigen

DFFsStartPo

jjicjdlyjDFFSEUDFF

fsPPPPfsP#

1)(log)()(

int#

1)(log)()( )())1(( ττ

42


NASA REAG FPGA Upper Bound Susceptibility Model

+−∃ ∑∑

==

ialCellsCombinator

iiwidthicipropigen

DFFsStartPo

jjicjdlyjDFFSEUDFF

fsPPPPfsP#

1)(log)()(

int#

1)(log)()( )())1(( ττ

+∃ ∑∑

==

ialCellsCombinator

iiwidthipropigen

DFFsStartPo

jDFFSEUDFF

fsPPP#

1)()()(

int#

1)( τ

Upper-bound assumes Plogic=1 (no mitigation) and NO DFF frequency (fs) dependency

43


NASA REAG Models + Heavy Ion Data:RTAXs

44


RTAXs FPGA Core Logic: Basic Building Blocks are R-CELLs and C-CELLs

C-CELL: Combinatorial

R-CELL: Sequential + Combinatorial

Combinatorial Logic is susceptible to Single Event Transients (SETs)(RCELLs, CCELLs, and buffers are susceptible to SETs)

DFF

45


Model Application to RTAXs: Embedded Localized Triple Modular Redundancy (LTMR)

( ) SEFILogicfunctionalionConfiguraterror PfsPPfsP ++∝ )(Design Specific SEE upset rate

Configuration SEE upset rate

Functional logic SEE upset rate

Single Event functional Interrupt

SEUSETSEUDFFSEU fsPP →→ + )(

Combinatorial logic cells

(LTMR): DFF46


Testing Combinatorial Logic Contributions to SEU Cross-Sections: WSRs with Inverters

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

N levels of Inverters between DFF stages:

N = 0, 8, and 18Shift Register Chain

4-bit Window Output

Windowed Shift Register (WSR)WSR0: N=0 Chain … Only DFFs

WSR8: N=8 Chain… 8 Inverters per 1 DFF

WSR16: N=16 Chain… 16 Inverters per 1 DFFDFFs

Combinatorial Logic

CCELLs: Inverters

Think of DFFs as your boundary points… They capture SETs

Q

QSET

CLR

D

Q

QSET

CLR

D

47

+∃ ∑∑

==

ialCellsCombinator

iiwidthipropigen

jiwidthipropigenDFF

fsPPfsPP#

1)()()(

1

1)()()( )()(( ττ

RCELL: Combinatorial CCELL: Combinatorial


RTAXs: SET Capture across LET affects WSR SEU Cross Sections

Increase Frequency→ Increase Cross sectionIncrease Combinatorial Logic → Increase Cross section

0.0E+00

1.0E-08

2.0E-08

3.0E-08

4.0E-08

5.0E-08

6.0E-08

7.0E-08

N=16INV N=8INV N=0

σ SEU

(cm

2 /bit)

WSR Chains

LET=75 MeV*cm2/mgWSRs with Checkerboard Input Pattern

1MHz

40MHz

80MHz

48

+ ∑∑

==

ialCellsCombinator

iiwidthipropigen

jiwidthipropigen fsPPfsPP

#

1)()()(

1

1)()()( )()(( ττ Per WSR

stage


RTAXs: SET Capture across LET affects SEU Cross Sections (Non-Linearity)

Low LETs: attenuation of Single Event Transients (SETs) at low LET values

0.0E+00

1.0E-08

2.0E-08

3.0E-08

4.0E-08

5.0E-08

6.0E-08

7.0E-08

N=16INV N=8INV N=0

σ SEU

(cm

2 /bit)

WSR Chains

LET=75 MeV*cm2/mgWSRs with Checkerboard Input Pattern

1MHz40MHz80MHz

LET MeV*cm2/mg

σ SEU

(cm

2 /bit)

Non-Linear Effects:WSR0 has the lowest σSEU at High LETs

WSR0 σSEU > WSR8 σSEU at Low LETs

49


Why is WSR0 > WSR8 for Low LET?

80))(())((

W SRSEUSETW SRSEUSET fsPfsP →→ >

RCELL Additional buffer after LTMR DFFs

Q

QSET

CLR

D

Q

QSET

CLR

D

WSR8

Q

QSET

CLR

D

Q

QSET

CLR

D

WSR0

Can’t make it to end point (Pprop is low)

50


Why is WSR0 > WSR8 for Low LET? Proof using the REAG Model

08

1

1)()()(

#

1)()()(

1

1)()()(

W SRjjwidthjpropjgen

W SR

natorialCCELLCombi

iiwidthipropigen

jjwidthjpropjgen fsPPfsPPfsPP ∑∑∑

===

<+ τττ

WSR8 CCELL Pprop is low

08

1

1)()()(

1

1)()()(

W SRjjwidthjpropjgen

W SRjjwidthjpropjgen fsPPfsPP ∑∑

==

< ττ

WSR8 WSR0

51

RCELL PpropWSR8< RCELL PpropWSR0

Q

QSET

CLR

D

Q

QSET

CLR

D

WSR8

Can’t make it to end point (Pprop is low)

RCELL RCELL


NASA REAG Models + Heavy Ion Data:ProASIC

52


Background: Micro-Semi (Actel) ProASIC3 Flash Based FPGA

• Originally a commercial device

• Configuration is flash based and has proven to be almost immune to SEUs

• No embedded mitigation in device

• Evaluation of user mitigation insertion has been performed

Word

Sensing

Floating Gate Switch In

Switching

Switch Out

Control gate (poly silicon)

Floating gate (poly silicon)

Tunnel oxide (100A-SiO2)

SiO2Si2N

53


Actel ProASIC3 Shift Register Study• Shift Register Functional Logic Designs Under Test:

– Six WSR strings with various levels of combinatorial logic


+∃ ∑

=→→

Inverters

iiSEUSETSEUDFFSEUDFF

fsPfsP#

0)()()(

54


σSEU Test Results: Windowed Shift Registers (WSRs) No-TMR

• N=0: WSR with only DFFs• N=8: WSR with 8 inverters between each DFF stage• No Mitigation: σSEU WSR0> σSEU WSR8 For every LET

0.0E+00

5.0E-08

1.0E-07

1.5E-07

2.0E-07

2.5E-07

2.80 3.96 8.60 12.16 20.30 28.71

σ SEU

(cm

2 /bit)

LET MeV*cm2/mg

No-TMR100MHz CheckerboardLET Versus SEU Cross Section

WSR N=8

WSR N=0

55


Why is WSR0 > WSR8 for Non-Mitigated ProASIC: τdly

Combinatorial Logic: InvertersQ

QSET

CLR

D

Q

QSET

CLR

DWSR8

Q

QSET

CLR

D

Q

QSET

CLR

DWSR0

DFFa DFFb

DFFa DFFb

dlyτ

For a clock period = τclk, if DFFa flips @ timeτ >(τclk −τdly) then DFFb will never capture the upset.

(0<τ<τclk)

56

Startpoint Endpoint

WSR0 τdly << WSR8 τdly


80))()(()((

W SRSEUSETSEUDFFSEUW SRSEUDFFSEU fsPfsPfsP →→→ +>

∑=

→+−>−8

1)()()1()1( 80

iiSEUSET

clk

W SRdly

DFFSEUclk

W SRdly

DFFSEU fsPPPτ

τ

τ

τ

∑=

→−>

8

1)()(

08i

iSEUSET

W SRdlyW SRdly

clkDFFSEU fsPP

τττ

DFF Capture (P(fs)DFFSEU→SEU) for WSR0 is not the same as WSR8because of τdly

Why is WSR0 σSEU > WSR8 σSEU for The Non-Mitigated ProASIC3 Design?

New Research!

57

τdly|WSR0 < τdly|WSR8

<τclk

DFF σSEU > combinatorial logic σSET


PfuntionalLogic: Comparison of PDFFSEU→SEU and PSET→SEU … How it Impacts System Susceptibility

PDFFSEU→SEU PSET→SEULogic Startpoint DFF Capture

by Endpoint DFFCombinatorial SETCapture by EndpointDFF

Capturepercentage of clock period (τclk)

Frequency Dependency

As frequency increases,PDFFSEU→SEU decreases

As frequency increases,PSET→SEU Increases

Combinatorial Logic Effects

Increase Combinatorial logic increases τdly and decreases PDFFSEU→SEU

Increase in combinatorial logic increases Pgen and increases PDFFSEU→SEU

)1()1( fsdlyclk

dly τττ

−=− fswidthclk

width τττ

=

58


Another Application of the P(fs)functionalLogic Model Components

• If the DFFs are mitigated and the σSEU is decreasing over frequency, how do you analyze this?– Combinatorial logic effects are directly proportional to

system frequency

– Hence, most likely not due to combinatorial logic… i.enot PSET→SEU.

• More than likely, the DFFs are not as mitigated as you expected them to be– As system frequency increases cross section decreases

– Plogic ≠0

59

)1( fsdlyτ−

fsPP jwidthjpropjgen )()()( τ


Local Triple Modular Redundancy (LTMR):Triple DFFs Only

• Triple Each DFF + Vote+ Feedback Correct at DFF• Unprotected:

– Clocks and Resets… SEFI– Transients (SET->SEU)– Internal/hidden device logic: SEFI

–Comb–Logic

–Voter

–Voter

–Voter

LTMR

0 ??( ) SEFISEUSETSEUDFFSEUionConfiguraterror PfsPfsPPfsP +++∝ →→ )()(60


ProASIC LTMR Shift Register Data Path Model

+∃ ∑∑

=→

=→

tesialLogicGaCombinator

iiSEUSET

DFFsStartPo

jjSEUDFFSEUDFF

fsPfsP#

1)(

int#

1)( )()(

Evaluate for Each DFF

+∃ ∑

=→→


iiSEUSETSEUDFFSEUDFF

fsPfsP#

1)()()(

∃ ∑

=→


iiSEUSETDFF

fsP#

1)()(

61

As we increase #combinatorial logic gates we increase σSEU

LTMR: Plogic=0


σSEU Test Results: Windowed Shift Registers (WSRs) No-TMR versus TMR

• LTMR is effective and has reduced PDFFSEU

• LTMR: SEU cross Sections WSR0<WSR8 For every LET

1.0E-10

1.0E-09

1.0E-08

1.0E-07

1.0E-06

2.80 3.96 8.60 12.16 20.30 28.71

σ SEU

(cm

2 /bit)

LET MeV*cm2/mg

No-TMR and LTMR 100MHz Checkerboard LET Versus SEU Cross Section

WSR N=8 No-TMRWSR N=0 No-TMRWSR N=8 LTMRWSR N=0 LTMR

62


Deliverables

• Further develop components of model for all FPGAs of concern

• Apply the model to an Application Specific Integrated Circuit (ASIC) Design

• Utilize the models to develop:– Develop design guidelines for radiation effects per

FPGA– Evaluate strength of a variety of mitigation strategies

per FPGA type

63


Summary• REAG has developed a FPGA SEE model:

– Specifically for Synchronous designs – Categorizes SEE upsets to assist analysis and test

structure development– Successfully applied across a variety of FPGA types– Great method for comparing different device types– Upper-bound version is mostly utilized

64

SEFILogicfunctionalionConfiguraterror fsPfsPfsPfsP )()()()( ++∝

( )SEUSETSEUDFFSEUDFFfsPfsP →→ +∃ )()(

+−∃ ∑∑

==

icGatesialCombinator

iiwidthicipropigen

DFFsStartPo

jjicjdlyjDFFSEUDFF

fsPPPPfsPlog#

1)(log)()(

int#

1)(log)()( )())1(( ττ

Documents

Taming the SEU Beast - Approaches and Results for FPGA ... · To be presented by Melanie Berg at the NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop,