TABLE 8-1 Control Signals for Binary Multiplierusers.ece.gatech.edu/hamblen/2030/chapter8.pdf · Symbolic Microprogram and Binary Microprogram for Multiplier ... Symbolic Microprogram

1997 by Prentice-Hall, Inc.LOGIC AND COMPUTER DESIGN FUNDAMENTALS Simon & Schuster / A Viacom CompanyMano & Kime Upper Saddle River, New Jersey 07458

T-192

TABLE 8-1Control Signals for Binary Multiplier

Block DiagramModule Microoperation

Control Signal Name

ControlExpression

Register A: Initialize Load

Shift_dec

Register B: Load_B

Flip-Flop C: Clear_C Load —

Register Q: Load_QShift_dec —

Counter P: Initialize —Shift_dec —

A 0← IDLE GA A B← MUL0 Q0C A Q sr C A Q← MUL1

B IN← LOADB

C 0← IDLE G MUL1C Cout←

Q IN← LOADQC A Q sr C A Q←

P n 1←P P 1←

Control Signals for Binary Multiplier


T-193

TABLE 8-2State Table for Sequence Register and Decoder Part of Multiplier Control Unit

Presentstate Inputs

Nextstate Decoder Outputs

Name M1 M0 G Z M1 M0 IDLE MUL0 MUL1

IDLE 0 0 0 0 0 1 0 00 0 1 0 1 1 0 0

MUL0 0 1 1 0 0 1 0

MUL1 1 0 0 0 1 0 0 11 0 1 0 0 0 0 1

— 1 1

State Table for Sequence Register and Decoder Part of Multiplier Control Unit


T-194

TABLE 8-3Control Signals for Microprogrammed Multiplier Control

Control Signal Register Transfers

States in WhichSignal is Active

Micro-instructionBit Position

SymbolicNotation

Initialize INIT 0 ITLoad ADD 1 LDClear_C INIT, MUL1 2 CCShift_dec MUL1 3 SD

A 0 P n 1←,←A A B C Cout←,←C 0←C A Q sr C A Q P P 1←,←

Control Signals for Microprogrammed Multiplier Control

1997 by Prentice-Hall, Inc.LOGIC AND COMPUTER DESIGN FUNDAMENTALS Simon & Schuster / A Viacom CompanyMANO & KIME Upper Saddle River, New Jersey 07458

T-195

TABLE 8-4SEL Field Definition for Binary Multiplier Control Sequencing

SEL

SequencingMicrooperations

Symbolicnotation

BinaryCode

NXT 00

DG 01

DQ 10

DZ 11

CAR NXTADD0←

G: CAR NXTADD0←G: CAR NXTADD1←

Q0: CAR NXTADD0←

Q0: CAR NXTADD1←

Z: CAR NXTADD0←Z: CAR NXTADD1←

SEL Field Definition for Binary Multiplier Control Sequencing


T-196

TABLE 8-5Register Transfer Description of Binary Multiplier Microprogram

Address Symbolic transfer statement

IDLEINITMUL0ADDMUL1

G: CAR INIT← G: CAR IDLE←,C 0← A 0← P n 1← CAR MUL0←,, ,Q0: CAR ADD Q0: CAR MUL1←,←A A B C Cout CAR MUL1←,←,←C 0 C A Q, sr C A Q , Z: CAR IDLE Z: CAR MUL0, ←,←← ←P P 1←

Register Transfer Description of Binary Multiplier Microprogram


T-197

TABLE 8-6Symbolic Microprogram and Binary Microprogram for Multiplier

Address NXTADD1 NXTADD0 SEL DATAPATH Address NXTADD1 NXTADD0 SEL DATAPATH

IDLE INIT IDLE DS None 000 001 000 01 0000INIT — MUL0 NXT IT, CC 001 000 010 00 0101MUL0 ADD MUL1 DQ None 010 011 100 10 0000ADD — MUL1 NXT LD 011 000 100 00 0010MUL1 IDLE MUL0 DZ CC, SD 100 010 000 11 1100

Symbolic Microprogram and Binary Microprogram for Multiplier


T-198

TABLE 8-7Truth Table for Instruction Decoder Logic

Instruction Bits Control Word Bits

Typical Operation CategoryBit 15 Bit 14 Bit 13 MB MD RW MW

0 0 0 0 0 1 0 ALU function using registers0 0 1 0 0 1 0 Shifter function using registers0 1 0 0 1 0 1 Memory write using register data0 1 1 0 1 1 0 Memory read using register data1 0 0 1 0 1 0 ALU operation using a constant1 0 1 1 0 1 0 Shifter function using registers1 1 0 1 1 0 1 Memory write using constant data1 1 1 1 1 1 0 Memory read using constant data

Truth Table for Instruction Decoder Logic


T-199 Six Instructions for the Single-Cycle Computer

Operationcode

Symbolicname Format Description Function MB MD RW MW

1000010 ADI Immediate Add immediate operand

1 0 1 0

0110000 LD Register Load memory content intoregister

0 1 1 0

0100000 ST Register Store register content inmemory

0 1 0 1

0000001 INC Register Increment register

0 0 1 0

0001110 NOT Register Complement register

0 0 1 0

0000010 ADD Register Add registers 0 0 1 0

R DR[ ] R SA[ ] zf I(2:0)1←

R DR[ ] M R SA[ ][ ]←

M R SA[ ][ ] R SB[ ]←

R DR[ ] R SA[ ] 11←

R DR[ ] R SA[ ]←

R DR[ ] R SA[ ] R SB[ ]1←


T-200

TD TA TB MB

Code

FS MD RW MM MW

CodeSelect Select Select Select Function Code Select Function Select Function

R[DR] R[SA] R[SB] Register 0 00000 FnUt No write(NW) Address No write(NW) 0

R8 R8 R8 Constant 1 00001 Data In Write(WR) PC Write(WR) 10001000011001000010100110001110100001010011000111010000100101010010110

F A5

F A 115F A B15F A B 11 15F A B15F A B 11 15F A 125F A5F A B∧5F A B∨5F A B%5F A5F A5F sl A5F sr A5F 05

Control Word Information for Datapath


T-201

MS MC IL PI

CodeActionSymbolicNotation Code Select

SymbolicNotation Action

SymbolicNotation Action

SymbolicNotation

Increment CAR CNT 000 NA NXA No load NLI No load NLP 0Load CAR NXT 001 Opcode OPC Load instr. LDI Increment PC INP 1If C 5 1, load CAR;else increment CAR

BC 010

If V 5 1, load CAR;else increment CAR

BV 011

If Z 5 1, load CAR;else increment CAR

BZ 100

If N 5 1, load CAR;else increment CAR

BN 101

If C 5 0, load CAR;else increment CAR

BNC 110

If Z 5 0, load CAR,else increment CAR

BNZ 111

Control Information for Sequence Control Fields


T-202

AddressNXTADD MS MC IL PI TD TA TB MB FS MD RW MM MW

IF EX0 CNT — LDI INP — — — — — — NW PC NWEXO — NXT OPC NLI NLP — — — — — — NW — NWADI IF NXT NXA NLI NLP DR SA — Constant FnUt WR — NWLD IF NXT NXA NLI NLP DR SA — — — Data WR MA NWST IF NXT NXA NLI NLP — SA SB Register — — NW MA WRINC IF NXT NXA NLI NLP DR SA — — FnUt WR — NWNOT IF NXT NXA NLI NLP DR SA — — FnUt WR — NWADD IF NXT NXA NLI NLP DR SA SB Register FnUt WR — NW

F A B15

F A 115F A5F A B15

Symbolic Microprogram for Fetch and Execution of Six Instructions


T-203

AddressNXTADD MS MC IL PI TD TA TB MB FS MD RW MM MW

192 193 000 0 1 1 0 0 0 0 00000 0 0 1 0193 000 001 1 0 0 0 0 0 0 00000 0 0 0 0000 192 001 0 0 0 0 0 0 1 00010 0 1 0 0001 192 001 0 0 0 0 0 0 0 00000 1 1 0 0002 192 001 0 0 0 0 0 0 0 00000 0 0 0 1003 192 001 0 0 0 0 0 0 0 00001 0 1 0 0004 192 001 0 0 0 0 0 0 0 01110 0 1 0 0005 192 001 0 0 0 0 0 0 0 00010 0 1 0 0

Binary Microprogram for Fetch and Execution of Six Instructions


T-204

IDLE

R 0RUN

(b) Example of state box

000NameBinarycode

Register operationor output

(a) State box (c) Decision box

0 1Condition

0 1START

IDLE

PC 0

(e) Example of decision and condition output box

R 0

From decision box

Register operationor output

(d) Conditional output box

→

→

→

ASM Chart Elements


T-205

0 1START

IDLE

ASM BLOCK

AVAIL

Entry

Exit

Q0

MUL0 MUL1

Exit Exit

0 1

A 0→

ASM Block


T-206

Clock cycle 1

Clock

START

Q0

State

AVAIL

A

IDLE MUL1

0034 0000

Clock cycle 2 Clock cycle 3

ASM Timing Behavior


T-207

23 10111 Multiplicand

19 10011 Multiplier

10111

10111

00000

00000

437 110110101 Product

101110000

Hand Multiplication Example


T-208

23 10111 Multiplicand

19 10011 Multiplier

00000 Initial partial product

10111 Add multiplicand, since multiplier bit is 1

10111 Partial product after add and before shift

010111 Partial product after shift


1000101 Partial product after add and before shifta





110110101 Partial product after add and before shift

437 0110110101 Product after final shift

a. Note that overflow temporarily occurred.

Hardware Multiplication Example


T-209

Cout

n

n

n–1

Counter P

Zero detect

Controlunit

G (Go)

log2n

Qo

Z

Parallel adder

Multiplicand

Register B

Shift register A0 C Shift register Q

Multiplier

Product

OUT

IN

Control signals

n

n n

5

Block Diagram for Binary Multiplier


T-210

0 1G

IDLE

Q0

MUL0

0 1Z

MUL1

C 0, A 0P n – 1

→ →

→

A A + B,C Cout

→

→

C 0, C || A || Q sr C || A || Q,P P – 1

→ →

→

0 1

ASM Chart for Binary Multiplier


T-211

0 1G

IDLE

MUL0

0 1Z

01

MUL1 10

00

Sequencing Part of ASM Chart for the Binary Multiplier


T-212

••IDLEMUL0MUL1

Initialize

Clear_C

Shift_dec

M0

Load

Clock

M1

G

Z

Q0

D

C

D

C

DECODERA0

A1

0

321

• •

••

•

•

•

Control Unit for Binary Multiplier Using a Sequence Register and a Decoder


T-213

(a) State box

(b) Decision box

(c) Junction

(d) Conditional output box

0 1X

Entry

Exit 0Exit 1

Entry 1 Entry 2

Exit

Entry 1

Exit

Entry 2

• •

Entry

X

Exit 0 Exit 1

••

Entry

X

Exit 1Control

Entry

Exit

State

EntryState

Exit

D

C

1X

Entry

Exit 1

•

Transformation Rules for Control Unit with One Flip-Flop per State


T-214

••

D

C

IDLE

D

C

MUL0

D

C

MUL1

••

•

•

•

•

••

••

Initialize

Clear _C

Load

Shift_dec

Clock Z

Q0

3

1

G

2

4

34

1

1 4

2

••

Control Unit with One Flip-Flop per State for the Binary Multiplier


T-215

Sequencer

Control address

Controlinputs Status signals from datapath

Next-addressgenerator

Control addressregister

Address

Controlmemory(ROM)

Data

Control data register(optional)

Next-addressinformation

Controloutputs

Control signalsto datapath

Microinstruction

Microprogrammed Control Unit Organization


T-216

0 1G

IDLE

0 1Q0

MUL0

0 1Z

MUL1

000

INIT 001

010

ADD 011

A A + B,C Cout

→

→

C 0, C || A || Q sr C || A || Q,P P – 1

→ →

→

A 0, C 0P n – 1

→ →

→

100

ASM Chart for Microprogrammed Binary Multiplier Control Unit


T-217

NXTADD1 NXTADD0 SEL DATAPATH

11 9 8 6 5 4 3 0

Microinstruction Control Unit Word Format


T-218

3

n

n

4Datapath

OUT

IN

2

5 x 12ControlMemory(ROM)

DATAPATH

SEL

NXTADD0

NXTADD1

CAR3

3

3

2

MUX1

2–to–1MUX

0

1

S

MUX2

4–to–1MUX

01

S1S0

23

0G

Q0Z

Microprogrammed Control Unit for Multiplier


T-219

(a) Register

OpcodeDestinationregister (DR)

Source reg-ister A (SA)

Source reg-ister B (SB)

15 9 8 6 5 3 2 0

(b) Immediate

OpcodeDestinationregister (DR)

Source reg-ister A (SA)

15 9 8 6 5 3 2 0

Operand (OP)

Two Instruction Formats


T-220

Decimaladdress

Memorycontents

Decimalopcode

Other specifiedfields Operation

→R1 R2 – R3

→M [R4] R5

→R2 R7 + 3

25 0000101 001 010 011 5 (Subtract) DR:1, SA:2 SB:3

35 0100000 000 100 101 32 (Store) SA:4 SB:5

45 1000010 010 111 011 66 (Add Immedi-ate)

DR:2 SA:7 OP:3

70 0000000 011 000 000 Data = 192. After execution of instruction in 35, Data = 80.

Memory Representation of Instructions and Data


T-221

Instructionmemory215 x 16

Datamemory215 x 16

Register file8 x 16

Program counter(PC)

Storage Resource Diagram for a Simple Computer


T-222

Bus ABus B

Address out

Data outMW

Data in

MUX B1 0

MUX D0 1

PC

Address

Instructionmemory

Instruction

Instruction decoder

Zero fill

DA

BA

AA

MB

FS

MD

RW

MW

CONTROL

DATAPATH

RW

DA

AA

Constantin

BA

Registerfile

D

A B

MB

FS

V

C

N

Z

Functionunit

A B

F

Data in Address

Datamemory

Data out

MDBus D

Block Diagram of a Single-Cycle Computer


T-223

5 3 3 3

5

••

••

Bit 13

18 - 16 15 - 13 12 - 10 9 8 - 4 2 1

Instruction

Opcode DR SA SB

15 14 13 - 9 5 - 3 2 - 08 - 6

DA AA BA MB FS MD RW

0

MW

Control word

•

•

Diagram of Instruction Decoder


T-224

1 ns

4 ns

3 ns

1 ns

4 ns

1 ns

3 ns

PC

Instructionmemory

Register file(Read)

MUX B

MUX D

Functionunit orData memory

Register file(Write)

Worst Case Delay Path in Single-Cycle Computer


T-225

8

RW

4TD || DR

TD || SA4

••

PC

4

2

2

Z C N C V C 1 0

7 6 5 4 3 2 1 0MUX S

3MS 16

ILIR

Opcode DR SA SB

3 3 3710

0 1MUX CMC

CAR

8

Controlmemory256 x 28

NA

MS

MC

IL

PI

TD

TA

TB

MB

FS

MD

RW

MM

MW

Sequencecontrol

Datapathcontrol

4

MICROPROGRAMMED CONTROL DATAPATH

PI

DA

AA

D

9 x 16Registerfile

A BBA

4TB || SB

MB1 0

MUX B

Bus B

Bus AMM

0 1

MUX M

Dataout

MW Addressout

Data in Address

MemoryM

Data out

Data in

A B

Functionunit

F

0 1

MUX DMDBus D

FSV

C

N

Z

Zero fill

Multiple-Cycle Microprogrammed Computer


T-226

27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

NA MS MC

IL

PI

TD

TA

TB MB FS M

DRW

MM

MW

Format for Microinstruction


T-227

ST

INC

NOT

ADD

ADl

EX0 11000001

0 1IR = 0000000?

00000000

R [DR] R [SA] + zf IR [2:0]→

LD0 1

IR = 0000001?00000001

R [DR] M [R [SA] ]→

0 1IR = 0000010?

00000010

M [R [SA] ] R [SB]→

0 1IR = 0000011?

00000011

R [DR] R [SA] + 1→

0 1IR = 0000100?

00000100

R [DR] R [SA]→

0 1IR = 0000101?

00000101

R [DR] R [SA] + R [SB]→

0 1IR = 0000110?

0 1IR = 0000111?

IF 11000000

IR M [PC]→PC PC + 1→

… …

ASM Chart for Multiple-Cycle Microprogrammed Computer


T-228

LRI0

0 1IR = 0000110?

00000110

R8 M [R [ SA] ]→

LRI1 10000110

R [DR] M [R8]→

To IF

…

…

ASM Chart for Register Indirect Instruction


T-229

0

SRM1

0 1IR = 0000111?

00000111

R8 zf IR [2:0]→

SRM2 10000111

R [DR] sr R [SA],→

…

…

1zf IR [2:0] = 0?

R8 R8 – 1→

R8 = 0?1

T0 IF

0

SRM3 10001000

T0 IF

NOTE: SA = DR

ASM Chart for Right-Shift Multiple Instruction


T-230

(ST)

(INC)

(NOT)

(ADD)

(ADl)

EX0 01

0 1IR = 0000000?

(LD)0 1IR = 0000001?

R [DR] M [R [SA] ]→

0 1IR = 0000010?

M [R [SA] ] R [SB]→

0 1IR = 0000011?

R [DR] R [SA] + 1→

0 1IR = 0000100?

R [DR] R [SA]→

0 1IR = 0000101?

R [DR] R [SA] + R [SB]→

0 1IR = 0000110?

IF 00

IR M [PC],→PC PC + 1→

(LRI)

R8 M [R [SA] ]→

R [DR] M [R8]→

R [DR] R [SA] + zf IR [2:0]→

EX1 10

ASM Chart for Multiple-Cycle, Decoder-Based Computer


T-231

CR

Decoder

Control logicDecoder

ADILDSTINCNOTADDLRI

0123456

CR

IL

PI

TD

TA

TB

MB

FS

MD

RW

MM

MW

IR

91011

IL

Syn. resetCounter

0 1 2IF

EX

EX

0 1

Block Diagram of Hardwired Counter and Decoder-Based,Multiple-Cycle Control Unit


T-232

WAREHOUSE

Assembly Line Analogy to Computer Pipeline


T-233

IF

IF

DOF

Stage

1

Address

Instructionmemory

Instruction

DOF

EX

EX

WB

Stage

2

Stage

3

AA BA

Registerfile

A data B data

Zero fill

Instruction decoderMUX B MB

Data A Data B

Address outFS MW

AA BA MB

FS

C

V

N

Z

A B

Functionunit

MDDA RWStage

4

WB

F

MD MUX D

RWD

D dataregister

file (sameas above)

Datamemory(same asabove)

Data F Data IData in Address

Data in

Data out MW

Data out

Datamemory

Address

CONTROL DATAPATH

5

PC

IR

Block Diagram of Pipelined Computer


T-234

1

2

3

4

5

6

7

Instruction

1 2 3 4 5 6 7 8 9 10

Clock cycle

DOF EX WB

DOF EX WB

DOF EX WB

DOF EX WB

DOF EX WB

DOF EX WB

DOF EX WB

IF

IF

IF

IF

IF

IF

IF

Pipeline Execution Pattern of Register Number Program


T-235

DOF EX WBIF1

2

3

4

5

6

7

Instruction

Clock cycle

8

9

10

DOF EX WBIF

DOF EX WBIF

DOF EX WBIF

DOF EX WBIF

DOF EX WBIF

DOF EX WBIF

DOF EX WBIF

DOF EX WBIF

DOF EX WBIF

R1

R3

R5

R7

R3

R7

R3, R7

R1, R3

R5, R7

1 2 3 4 5 6 7 8 9 10 11 12 13

Pipeline Execution Pattern of Register Sum Program

Documents

TABLE 8-1 Control Signals for Binary Multiplierusers.ece.gatech.edu/hamblen/2030/chapter8.pdf · Symbolic Microprogram and Binary Microprogram for Multiplier ... Symbolic Microprogram