VESTEL STB

SERVICE MANUAL

DIGITAL TERRESTRIAL STB MODEL

T 201

Schematic Version PCB 16MB21E1_E2_E3

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REVISION HISTORY ................................................................................................................................................................. 3

GENERAL DESCRIPTION ........................................................................................................................................................ 3

STi5518 (IC100) ..................................................................................................................................................... 3 SDRAM 8MByte (IC300, IC301)........................................................................................................................... 20 Flash Memory 2 MByte (IC302) .......................................................................................................................... 20 EEPROMs 32K 2-wire Serial (IC303) ................................................................................................................. 21 DVB-T COFDM Demodulator + FEC + ADC(IC401) ............................................................................................ 22

IC 602 AND IC 603 AS AN AV SWITCH ................................................................................................................................ 28

IC 601 AND IC600 DC-DC CONVERTERS........................................................................................................................... 29

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RS ................................................................................................................................................................................................. 29

RS 232 PINS THROUGH TV SCART(OPTIONAL).............................................................................................................. 30

USED IC LISTS.......................................................................................................................................................................... 30

MAINBOARD (16MB21e1)................................................................................................................................... 30 POWER supply ................................................................................................................................................... 30

CONNECTORS .......................................................................................................................................................................... 30

Jk1:POWER connector....................................................................................................................................... 30 PL100:5518 JTAG Connectors ........................................................................................................................... 31 PL201:SCART connector.................................................................................................................................... 31 PL601:VCR scart socket..................................................................................................................................... 32

POWER REQUIREMENTS...................................................................................................................................................... 33

PCB EXPLANATIONS.............................................................................................................................................................. 33

MAIN BOARD ( 16MB21e1 )................................................................................................................................ 33

SERVICE MENU INTERFACE ............................................................................................................................................... 34

FIRST TIME INSTALLATION............................................................................................................................... 34 SOFTWARE DOWNLOAD THROUGH rs232 connector.................................................................................... 35 RS232 TEST ........................................................................................................................................................ 36 RECEIVER UPGRADE OVER THE AIR............................................................................................................... 37

SCHEMATICS............................................................................................................................................................................ 46

16MB21E1 MAINBOARD SCHEMATIC .............................................................................................................. 46

BILL OF MATERIALS ............................................................................................................................................................. 46

REVISION HISTORY

Rev 1.0 15/08/03

GENERAL DESCRIPTION

Major functional blocks are discussed briefly in this section. A more detailed description is contained later in the document. STi5518 (IC100)

1. Introduction The STi5518 integrates in a single chip: a transport demultiplex block; an ST20 32-bit system CPU; an

audio/video MPEG2 decoder; display and graphics features; a digital video encoder; and system peripherals. The

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Sti5518 integrates DirecTV and DVB descramblers in the transport demultiplex block, allowing it to be used in both Digital Video Broadcasting (DVB) and Digital Satellite System (DSS) set-top box applications.

2. Technical Specification Integrated 32-bit host CPU up to 81 MHz 2 Kbytes of Icache, 2 Kbytes of Dcache, and 4 Kbytes of SRAM configurable as Dcache. Audio decoder 5.1 channel Dolby Digital® /MPEG-2 multi-channel decoding, 3 X 2-channel PCM outputs IEC60958 -IEC61937 digital output SRS®/TruSurround® DTS® digital out and MP3 decoding Alignment beep for satellite dishes. Video decoder Supports MPEG-2 MP@ML Fully programmable zoom-in and zoom-out NTSC to PAL conversion. DVD and SVCD subpicture decoder High performance on-screen display 2 to 8 bits per pixel OSD options Anti-flicker, anti-flutter and anti-aliasing filters. PAL/NTSC/SECAM encoder RGB, CVBS, Y/C and YUV outputs with 10-bit DACs Macrovision® 7.01/6.1 compatible (optional). Shared SDRAM memory interface 1 or 2x16-Mbit, or 1x64-Mbit 125 MHZ SDRAM. Programmable CPU memory interface for SDRAM, ROM, peripherals... Front-end interface DVD, VCD, SVCD and CD-DA compatible Serial, parallel and ATAPI interfaces Hardware sector filtering Integrated CSS decryption and track buffer. Hardware transport-stream demultiplexor Parallel/serial input DES and DVB descramblers 32 PID support. Integrated peripherals

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2 UARTs, 2 SmartCards, I2C controller, 3 PWM outputs, 3 capture timers Modem support 44 bits of programmable I/O IR transmitter/receiver. Professional toolset support ANSI C compiler and libraries. 208 pin PQFP package. The STi5518 is a highly integrated single-chip decoder, designed for use in feature-rich mass-market set-top boxes. It integrates a high-performance 32-bit CPU, a dedicated block for DVB/DirecTV transport demultiplexing and descrambling, modules for MPEG-2 video and audio decoding with 3D-surround and MP3 support, advanced display and graphics features, a digital video encoder and all of the system peripherals required in a typical low-cost interactive receiver. To cover the needs of DVD-capable set-top boxes, STi5518 integration options include a CSS decryption block, a Dolby Digital audio decoder and Macrovision copy protection. An ATAPI interface is built-in, supporting the glueless connection of standard Hard Disk Drives. In this way, the STi5518 is ideal for set-top boxes featuring trick modes such as live TV recording, pausing and time-shifting. The STi5518 is backward compatible with the popular STi5500 set-top box decoder, allowing easy migration from the previous generation. The high level of integration in a single PQFP-208 package makes the STi5518 ideally suited for low-cost, high-volume set-top box applications.

3. Architecture overview The figure below shows the architecture of the Sti5518. This chapter gives a brief overview of each of the functional blocks of the STi5518.

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4. STi5518 functional modules a. Central processor The STi5518 Central Processing Unit is a ST20C2+ 32-bit processor core. It contains instruction processing logic, instruction and data pointers, and an operand register. It directly accesses the high-speed on-chip SRAM, which can store data or programs and uses the cache to reduce access time to off-chip program and data memory. The processor can access memory via the Programmable CPU Interface (often referred to as the EMI) or the Shared Memory Interface (SMI), which is shared with the video, audio, sub-picture and OSD decoders. b. MPEG video decoder This is a real-time video compression processor supporting the MPEG-1 and MPEG-2 standards at video rates up t 720 x 480 x 60 Hz and 720 x 576 x 50 Hz. Picture format conversion for display is performed by vertical and horizontal filters. User-defined bitmaps can be super-imposed on the display picture by using the on-screen display function. The display unit is part of the MPEG video decoder, it overlays the four display planes shown in the figure below. The display planes are normally overlaid in the order illustrated, with the background color at the back and

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the sub-picture at the front (used as a cursor plane). The sub-picture plane can alternatively be positioned between the OSD and MPEG video planes where it can be used as a second on-screen display plane. c. Audio decoder The audio decoder accepts: Dolby Digital, MPEG-1 layers I, II and III, MPEG-2 layer II 6-channel, PCM, CDDA data formats; MPEG2 PES streams for MPEG-2, MPEG-1, Dolby Digital, MP3, and Linear PCM (LPCM). The audio decoder supports DTS® digital out (DVD DTS and CDDA DTS). SPDIF input data (IEC-60958 or IEC-61937 standards) is accepted if an external circuitry extracts the PCM clock from the stream. Skip frame, repeat blocks and soft mute frame features can be used to synchronize audio and video data. PTS audio extraction is also supported. The device outputs up to 6 channels of PCM data and appropriate clocks for external digital-to-analog converters. Programmable downmix enables 1,2,3 or 4 channel outputs. Data can be output in either I²S format or Sony format. The decoder can format output data according to IEC-60958 standard (for non compressed data: L/R channels, 16, 18, 20 and 24-bits) or IEC-61937 standard (for compressed data), for FS = 96 kHz, 48 kHz, 44.1 kHz or 32 kHz. Sampling frequencies of 96 kHz, 48 kHz, 44.1 kHz, 32 kHz and half sampling frequencies are supported. A downsampling filter (96 kHz/48 kHz) is available. The decoder supports dual mode for MPEG and Dolby Digital. It includes a Dolby surround compatible downmix and a ProLogic decoder. A pink noise generator enables the accurate positioning of speakers for optimal surround sound setup. PCM beep tone is a special mode used for Set Top Box. It generates a triangular signal of variable frequency and amplitude on the left and right channels. In global mute mode, the decoder decodes the incoming bitstream normally but the PCM and SPDIF outputs are softmuted. This mode is used to prepare a period of decoding mode, to synchronize audio and video data without hearing the audio. Slow-forward and fast-forward trick modes are available for compressed and non-compressed data. The control interface of the decoder is activated via memory mapped registers in the ST20 address space. d. IR transmitter/receiver The STi5518 provides a pulse-position modulated signal for automatic VCR programming by the set-top box. The signal is output to the IR blast pin and an accessory jack pin, simultaneously. The pulse frequency, number of pulses (envelope length) and the total cycle time is controlled by registers. e. Modem analog front-end interface The Modem Analog Front-end interface is used to transfer transmit and receive DAC and ADC samples between the memory and an external modem analog front-end (MAFE), using a synchronous serial protocol. DMA is used to transfer the sample data between memory buffers and the MAFE interface module, with separate transmit and receive buffers and double buffering of the buffer pointers. FIFOs are used to take into account the access latency to memory, in a worst case system and to allow the use of bursts for memory bandwidth efficiency improvement. The V22 bis standard is supported. f. Memory subsystem On-chip The on-chip memory includes 2Kbytes of instruction cache, 2Kbytes of data cache and 4Kbytes of SRAM that can be optionally configured as data cache. The subsystem provides 240M/bytes of internal bandwidth, supporting pipelined 2- cycle internal memory access. The instruction and data caches are direct-mapped, with a write-back system for the data-cache. The caches support burst accesses to the external memories for refill and write-back. Burst access increases the performance of pagemode DRAM memories. Off-chip There are two off-chip memory interfaces: • The external memory interface (EMI) accessed by the ST20 is used for the transfer of data and programs between the STi5518 and external peripherals, flash and additional SDRAM and DRAM. • Shared memory interface (SMI) controls the movement of data between the STi5518 and 16, 32 or 64 Mbits of SDRAM. This external SDRAM stores the display data generated by the MPEG decoder and CPU and the C2+ code data. The EMI uses minimal external support logic to support memory subsystems, and accesses a 32 Mbytes of physical

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address space (greater if SDRAM or DRAM is used) in four general purpose memory banks of 8 or 16 bits wide, 21 or 22 address lines, and byte select. For applications requiring extra memory, the EMI supports this extra memory with zero external support logic, even for 16-bit SDRAM devices. The EMI can be configured for a wide variety of timing and decode functions by the configuration registers. The timing of each of the four memory banks can be set separately, with different device types being placed in each bank with no need for external hardware. g. Serial communication Asynchronous serial controllers The Asynchronous Serial Controller (ASC), also referred to as the UART interface, provides serial communication between the STi5518 and other microcontrollers, microprocessors or external peripherals. The STi5518 has four ASCs, two of which are generally used by the SmartCard controllers. Eight or nine bit data transfer, parity generation, and the number of stop bits are programmable. Parity, framing, and overrun error detection increase data transfer reliability. Transmission and reception of data can be double-buffered, or 16-deep FIFOs can be used. A mechanism to distinguish the address from the data bytes is included for multiprocessor communication. Testing is supported by a loop-back option. A 16-bit baud-rate generator provides the ASC with a separate serial clock signal. Two ASCs support full-duplex and 2 half-duplex asynchronous communication, where both the transmitter and the receiver use the same data frame format and the same baud rate. Each ASC can be set to operate in SmartCard mode for use when interfacing to a SmartCard. Synchronous serial controller Two Synchronous Serial Controllers (SSC) provide high-speed interfaces to a wide variety of serial memories, remote control receivers and other microcontrollers. The SSCs support all of the features of the Serial Peripheral Interface bus (SPI) and the I2C bus. The SSCs can be programmed to interface to other serial bus standards. The SSCs share pins with the parallel input/output (PIO) ports, and support half-duplex synchronous communication. h. Front-end interface The STi5518 can be connected to a front-end through the following interfaces: • I2S interface; • multi-format serial interface; • multi-format parallel interface; • ATAPI interface (for Hard Disk Drives and DVD-ROMs) i. On-chip PLL The on-chip PLL accepts 27 MHz input and generates all the internal high-frequency clocks needed for the CPU, MPEG and audio subsystems. j. Diagnostic controller (DCU) The ST20 Diagnostic Controller Unit (DCU) is used to boot the CPU and to control and monitor the chip systems via the standard IEEE 1194.1 Test Access Port. The DCU includes on-chip hardware with ICE (In Circuit Emulation) and LSA (Logic State Analyzer) features to facilitate verification and debugging of software running on the on-chip CPU in real time. It is an independent hardware module with a private link from the host to support real-time diagnostics. k. Interrupt subsystem The interrupt system allows an on-chip module or external interrupt pin to interrupt an active process so that an interrupt handling process can be run. An interrupt can be signalled by one of the following: a signal on an external interrupt pin, a signal from an internal peripheral or subsystem, software asserting an interrupt in the pending register. Interrupts are implemented by an on-chip interrupt controller and an on-chip interrupt-level controller. The interrupt controller supports eight prioritized interrupts as inputs and manages the pending interrupts. This allows

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the nesting of pre-emptive interrupts for real-time system design. Each interrupt can be programmed to be at a lower or higher priority than the high priority process queue. l. PAL/NTSC/SECAM encoder The integrated digital encoder converts a multiplexed 4:2:2 or 4:4:4 YCbCr stream into a standard analog baseband PAL/NTSC or SECAM signal and into RGB, YUV, Yc and CVBS components. The encoder can perform closed-caption, CGMS encoding, and allows MacrovisionTM 7.01/6.1 copy protection. The DENC is able to encode Teletext according to the “CCIR/ITU-R Broadcast Teletext System B” specification, also known as “World System Teletext”. In DVB applications, Teletext data is embedded within DVB streams as MPEG data packets. It is the responsibility of the software to handle incoming data packets and in particular to store Teletext packets in a buffer, which then passes them to the DENC on request. m. SmartCard interfaces Two SmartCard interfaces support SmartCards compliant with ISO7816-3. Each interface is has a UART (ASC), a dedicated programmable clock generator, and eight bits of parallel IO port. n. PWM and counter module The PWM and counter module provides three PWM encoder outputs, three PWM decoder (capture) inputs and four programmable timers. Each capture input can be programmed to detect rising edge, falling edge, both edges or neither edge (disabled). These facilities are clocked by two independent clocks, one for PWM outputs and one for capture inputs/timers. The PWM counter is 8-bit, with 8-bit registers to set the output-high time. The capture/compare counter and the compare and capture registers are 32-bit. The module generates a single interrupt signal. o. Parallel I/O module 44 bits of parallel I/O are configured in 6 ports, and each bit is programmable as output or input. The output can be configured as a totem-pole or open-drain driver. The input compare logic can generate an interrupt on any change of any input bit. Many parallel IO have alternate functions and can be connected to an internal peripheral signal such as a UART or SSC.

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5. Pin list sorted by function Alternate functions printed in Italic show a suggested use of the PIO; alternate functions not printed in Italic are multiplexed with a specific hardware.

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1. FEI_CFG bits 8 and 9 must be programmed according to the required NRSS configuration. 2. The NRSS_IN and NRSS_OUT pins are swapped around on the STi5518 compared to the STi5508. 3. Register LNK_SDAV_CONF bit 22 (SDE) must be set to 1 to validate the output path. 4. Inverted. ATTENTION! the PIO input is also inverted. 5. The PIO must be configured in open drain. 6. BOOT_FROM_ROM is active during reset. 7. Tie low whenever JTAG is not used.

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6. Pins sorted by pin number

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1. FEI_CFG bits 8 and 9 must be programmed according to the required NRSS configuration. 2. The NRSS_IN and NRSS_OUT pins are swapped around on the STi5518 compared to the STi5508. 3. Register LNK_SDAV_CONF bit 22 (SDE) must be set to 1 to validate the output path. 4. Inverted. ATTENTION! the PIO input is also inverted. 5. The PIO must be configured in open drain. 6. Tie low whenever JTAG is not used 7. BOOT_FROM_ROM is active during reset.

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SDRAM 8MByte (IC300, IC301) IC300 SDRAM is on the Shared Memory Interface (SMI) and decoded picture is stored in this sdram .The smi sdram has 121.5Mhz clock input.IC301 SDRAM is on the EMI( external memory interface) and software runs over this sdram.The emi sdram has 81 Mhz clock input.

FEATURES • PC66-, PC100- and PC133-compliant • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal banks for hiding row access/ precharge • Programmable burst lengths: 1, 2, 4, 8 or full page • Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes • Self Refresh Modes: standard and low power • 64ms, 4,096-cycle refresh • LVTTL-compatible inputs and outputs • Single +3.3V ±0.3V power supply

GENERAL DESCRIPTION The 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 67,108,864 bits. It is

internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 16,777,216 -bit banks is organized as 4,096 rows by 1,024 columns by 4 bits. Each of the x8’s 16,777,216-bit banks is organized as 4,096 rows by 512 columns by 8 bits. Each of the x16’s 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.

The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4 or 8 locations, or the full page, with a burst terminate option. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The 64Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. The 64Mb SDRAM is designed to operate in 3.3V, lowpower memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAM’s offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks in order to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access. Flash Memory 2 MByte (IC302) • Single 3.0 V read, program and erase • Compatible with JEDEC-standard commands • Compatible with JEDEC-standard world-wide pinouts • Minimum 100,000 program/erase cycles 80 ns maximum access time • Sector erase architecture One 8K word, two 4K words, one 16K word, and thirty-one 32K words sectors in word mode One 16K byte, two 8K bytes, one 32K byte, and thirty-one 64K bytes sectors in byte mode

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Any combination of sectors can be concurrently erased. Also supports full chip erase • Boot Code Sector Architecture T = Top sector • Embedded Erase TM Algorithms Automatically pre-programs and erases the chip or any sector • Embedded program TM Algorithms Automatically programs and verifies data at specified address •Data Polling and Toggle Bit feature for detection of program or erase cycle completion • Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion • Automatic sleep mode When addresses remain stable, automatically switches themselves to low power mode •Low VCC write inhibit ≤ 2.5 V

GENERAL DESCRIPTION The MBM29LV160T is a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M words of 16 bits each. The MBM29LV160T is offered in a 48-pin TSOP FBGA packages. The device is designed to be programmed in-system with the standard system 3.0 V VCC supply. The standard MBM29LV160T offers access times of 80 ns and 120 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls. The MBM29LV160T is pin and command set compatible with JEDEC standard E 2 PROMs. Commands are written to the command register using standard microprocessor write timings. The MBM29LV160T is programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margins. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margins. Any individual sector is typically erased and verified in 1.0 second. (If already preprogrammed.) The device also features a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The device features single 3.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7 , by the Toggle Bit feature on DQ6 , or the RY/BY output pin. Once the end of a program or erase cycle has been comleted, the device internally resets to the read mode. The MBM29LV160Thas a hardware RESET pin. When this pin is driven low, execution of any Embedded Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the read mode. The RESET pin is tied to the system reset circuitry. Therefore, if a system reset occurs during the Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read mode and will have erroneous data stored in the address locations being programmed or erased.. Resetting the device enables the system’s microprocessor to read the boot-up firmware from the Flash memory. EEPROMs 32K 2-wire Serial (IC303) The 24WC32is a 32K-bit Serial CMOS E 2 PROM internally organized as 4096/8192 words of 8 bits each. Zero Standby Current Features Commercial, Industrial and AutomotiveTemperature Ranges 1,000,000 Program/Erase Cycles 100 Year Data Retention 24WC32 features a 32-byte page write buffer. The device operates via the I 2 C bus serial interface and is available in 8-pin DIP or 8-pin SOIC packages.

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400 KHz I 2 C Bus Compatible* 1.8 to 6 Volt Read and Write Operation 32-Byte Page Write Buffer Self-Timed Write Cycle with Auto-Clear Schmitt Trigger Inputs for Noise Protection Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-O Red with any number of other open-drain or open collector devices. DEVICE/PAGE ADDRESSES (A1, A0): The A1 and A0 pins are device address inputs that are hardwired or left not connected for hardware compatibility with 24C32. When the pins are hardwired, as many as four 32K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). When the pins are not hardwired, the default A1 and A0 are zero. WRITE PROTECT (WP): The write protect input, when tied to GND, allows normal write operations. When WP is tied high to VCC, all write operations to the memory are inhibited. If left unconnected, WP is internally pulled down to GND. Switching WP to VCC prior to a write operation creates a software write protect function. Absolute Maximum Ratings Operating Temperature.................................. -55C to +125C Storage Temperature ..................................... -65C to +150C Voltage on Any Pin with Respect to Ground .....................................-1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5.0 mA DVB-T COFDM Demodulator + FEC + ADC(IC401)

Features Decodes DVB-T (ETS300744) and NorDig II _Single frequency network (SFN) compliant _Adjacent channel interference canceller (ACI) _Excellent Doppler performance (200 Hz) _Automatic guard interval and mode detection _Accepts 6, 7 and 8 MHz channel bandwidths _Lock indicators and general purpose I/O pins _Supports 2K, 8K modes _Supports QPSK, 16, 64 QAM constellations _1/4, 1/8, 1/16, 1/32 guard interval _Supports hierarchical and non-hierarchical modes _Fully digital demodulation _Impulsive noise rejection feature _Digital timing and frequency correction _Channel equalization through scattered pilots _Common phase error correction _Transmitter parameter signalling decoding (TPS) TPS decoded or automatic FEC mode detection _Inner decoder: - Punctured codes 1/2, 2/3, 3/4, 5/6 and 7/8 _Sync word extraction _Convolutive de-interleaver

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_Outer decoder: - Reed-Solomon decoder for 16 parity bytes; correction of up to 8 byte errors _Integrated signal quality monitors _Parallel and serial output interfaces compliant with DVB common interface _Hierarchical auxiliary FEC input/output Embeds PGA for IF level adaptation _High-performance ADC for direct IF (36 MHz) architecture _Dual AGC (.......outputs) _10-bit ADC for RF signal strength indicator Generates system clock on-chip from 20 to 27-MHz crystal quartz _No external VCXO required _Programmable o/p clock derived from system clock Four I²C addresses available _Easy control/monitoring via fast I²C bus (4 MHz) _Additional private I²C bus (I²C repeater) dedicated to tuner control for minimum tuner disturbance Absolute maximum ratings Maximum limits indicate where permanent device damages occur. Continuous operation at these limits is not intended, and should be limited to those conditions specified below,

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SAW FILTER(Z400) X6966M is band pass filter at center frequency of 36.125Mhz typically. It is used for 8Mhz bandwidth broadcast reception.

DIGITAL TERRESTRIAL TUNER(TU400) - PLL TUNER OPTIMIZED FOR LOW PHASE NOISE LO. 5V AND 30V POWER SUPPLY. - LOW OUTPUT IMPEDANCE OF SIMMETRICAL I.F. AMPLIFIER, SPECIFICALLY DESIGNED FOR DIRECT SAW FILTER DRIVE. - MIXER OSCILLATOR I.C. IMPROVES PERFORMANCE OF SIGNAL HANDLING. - IT COMPLIES WITH EUROPEAN STANDARD EN 55013 AND EN 55020. PLL I²C BUS TUNING SYSTEM. Input frequencies between 474 MHz and 858 Mhz(UHF band) Normal operating voltages +5V:4.75Vmin 5.5Vmax. +33V:30Vmin 35Vmax.

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Voltage at PİN 2 (agc input) can be max 3.3V to receive low RF signal or a breakdown occurs in the demodulator or discrete if amplifier section.If tuner and discrete if amplifier circuit is operating properly about 400mVp-p baseband signal should be measured at pin 61 and pin62 of IC400.

DIGITAL TERRESTRIAL TUNER with RF MODULATOR INSIDE(TU500) - PLL TUNER OPTIMIZED FOR LOW PHASE NOISE LO. 5V AND 30V POWER SUPPLY.

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IC 602 AND IC 603 AS AN AV SWITCH 74hc4052; LOWPOWER DISSIPATION ICC =4mA (MAX.) AT TA =25 o C LOGIC LEVEL TRANSLATION TO ENABLE 5V LOGIC SIGNAL TO COMMUNICATE WITH ±5V ANALOG SIGNAL LOW”ON” RESISTANCE: 70Ω TYP. (VCC -VEE = 4.5 V) 50Ω TYP. (VCC -VEE =9V) WIDE ANALOGINPUT VOLTAGERANGE: ±6V FAST SWITCHING: tpd = 15 ns (TYP.) AT TA =25 o C LOWCROSSTALK BETWEEN SWITCHES HIGH ON/OFF OUTPUT VOLTAGE RATIO WIDE OPERATING VOLTAGE RANGE (VCC -VEE) = 2V TO 12V LOWSINE WAVE DISTORTION 0.02% AT VCC -VEE =9V HIGH NOISE IMMUNITY VNIH =VNIL =28%VCC (MIN.)

IC602 is used to switch for audio and IC603 is used for video switching between vcr scart and tv scart connector.

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IC 601 AND IC600 DC-DC CONVERTERS

Ic 601 is used as a step down converter and IC 600 is used as an step down converter. The MC34063A Series is a monolithic control circuit containing the primary functions required for DC–to–DC converters. These devices consist of an internal temperature compensated reference, comparator, controlled duty cycle oscillator with an active current limit circuit, driver and high current output switch. This series was specifically designed to be incorporated in Step–Down and Step–Up and Voltage–Inverting applications with a minimum number of external components. Refer to Application Notes AN920A/D and AN954/D for additional design information.

Operation from 3.0 V to 40 V Input Current Limiting Output Switch Current to 1.5 A Output Voltage Adjustable Frequency Operation to 100 kHz

32V is supplied through fast switching diodes and capacitors. 12V is adjusted to around 11.5v not to heat ic602 and ic603 Main power of the board is 6V 1.5amp dc .

RS

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RS 232 PINS THROUGH TV SCART(OPTIONAL)

TXD and RXD are the lines to update the stb software.The discrete circuits including q106 q107 and q108 transistors do this function. To overcome a problem during operation of the stb a 220pf smd capacitor must be soldered to the base of q108.

USED IC LISTS

MAINBOARD (16MB21e1) Sti5518 (IC100) Set Top Box Backend Decoder With Integrated Host Processor TSH 22 (IC103) Dual Bipolar Operational Amplifier M74HCU04 (IC102) Hex Inverter HY57V641620HG (IC301,IC300) 8 Mbyte SDRAM 29LV160TE (IC302) 2Mbyte(top boot) Flash Memory AT24C32(IC303) 32Kbit Serial EEPROM Stv0360 (IC400) COFDM demodulator. LM833 (IC200) Low Noise Dual Operational Amplifier CS4335 (IC500) 8-Pin, 24 Bit, 96 KHz Stereo D/A Converter AAT3524(IC5) Optional (150 msec delay Reset IC. With R59=4k7 R PULL UP .) POWER supply 6V 1.5Amp dc power supply or 6V 2.5amp dc power supply can be used.

CONNECTORS

Jk1:POWER connector

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PL100:5518 JTAG Connectors

JTAG Connector – PL100 Pin Description Pin Description 1 ------ 11 TCK 2 GND 12 GND 3 TRIGOUT 13 TDI 4 GND 14 GND 5 TRIGIN 15 TDO 6 GND 16 GND 7 ------ 17 JTAGRESET 8 GND 18 GND 9 TMS 19 TRST 10 GND 20 GND

PL201:SCART connector

20 18 16 14 12 10 8 6 4 2

21 19 17 15 13 11 9 7 5 3 1

TV Scart Socket – PL201

Pin Description Pin Description 1 Audio Right Output 12 Not connected

2 Audio Right Input 13 GND

3 Audio Left Output 14 GND

4 GND 15 RED Output/C OUTPUT

5 GND 16 Fast Blanking Output

6 Audio Left Input 17 GND

7 BLUE Output 18 GND

8 Function Switching Output 19 CVBS Output/Y OUTPUT

9 GND 20 CVBS Input

10 Not connected 21 GND

11 GREEN Output

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PL601:VCR scart socket

PIN SIGNAL PIN SIGNAL

1 Audio Right Output 12 No Connection

2 Audio Right Input 13 GND

3 Audio Left Output 14 GND

4 GND 15 RED Output/C OUTPUT 5 GND 16 No Connection

6 Audio Left Input 17 GND

7 BLUE Output 18 GND

8 Function Switching Input 19 CVBS Output/Y OUTPUT 9 GND 20 CVBS Input

10 No Connection 21 GND

11 GREEN Output

JK3:SPDIF CONNECTOR DİGİTAL AUDIO OUTPUT 700mvp-p at 75 r load

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POWER REQUIREMENTS

When stb is active maximum power consumption of the stb is 12Wmax. The external power supply uses 14W max.

PCB EXPLANATIONS

MAIN BOARD ( 16MB21e1 ) The main board contains two parts: Front-end (sheet4) and Back-end. The digital signal is demodulated in Front-end and then decoded in Back-end. Analog signals are processed in different part. The tuner (TU400 thomson or SAMSUNG) is capable of getting both digital broadcasts. Tuner IF ouput is bandpass filtered at z400(saw fiter ) and pass along the discrete if amplifier circuit (sheet 4 left side) and analogue digital signal is converted to transport stream signals after some filtering, COFDM (coded orthogonal) demodulation(by using 2k or 8k carriers) and correction.The demodulator output is configured as parallel.The digital data is transported to the sti5518 mpeg-2 decoder(ic100) with fc_clk(clock signal to decoder), fc_valid(indicates valid data bits of transport stream(ts)) and fc_sync (indicates start of a ts ). The ts has all the multiplexed signals which includes video, audio and data information related to one or more than one program . TS_ERROR signal should be low for valid data and for mpeg-2 decoder to decode properly.stv0360 DEMODULATOR is controlled via I2C by sti5518 decoder and TU400 is controled by demodulator(ic401) via sclk and sdata. At the backend part, there is a 32-bit CPU ST20 (in Sti 5518 embeded ) that controls all processes. Demultiplexer of the CPU provides the transmission of the desired channel’s information from TS (Transport Stream) to MPEG Decoder section. The program that runs on Sti5518 is in Flash memory(IC302). 64Mbits SDRAMs (IC301, IC300) are used for data memory of this program.IC300 is SMI sdram and decoded data is stored here.It has a clock input of 121.5Mhz.Software is mostly run over IC301 EMI sdram. Some program and status information is stored in eeprom(IC304). ST20 uses 32- bit data and 22- bit address buses for access to flash, DRAM and MPEG decoder. It uses RAS, CAS etc. (read, write, enable) signals to activate related IC while accessing them. The main clock which is needed by Sti 5518 (IC100), is generated at power on mode and at stby by 27MHz crystal (X112) and IC102 (74HCU04). The output of PWM outputs of Sti

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5518, is filtered to have a DC level via R128 and C133. At the output of IC103, the 27MHz clock can be adjusted according to capacity of pins of 27MHz crystal to ground. This capacity is related with DC value on D100 and D101 (BB133) at pins of crystal. This operation maintains synchronization between audio-video that are coming from MPEG transport stream and PCR clock. Sti 5518 (IC100) can communicate with any other micro controller via TV scart PİN10 and pin11 . The RS232 port of receiver through tv scart is used to debug any problem using Windows Hyper Terminal program and to update sw of the stb. MPEG decoder in Sti 5518, is responsible for decoding of MPEG video and audio signals. The video, which is compressed using MPEG2 and audio, which is compressed using MPEG1 Layer 1-2, are processed here. After decoding, CCIR 601 formatted 8-bit video and PCM formatted audio, are generated by mpeg decoder. Digital audio that is PCM formatted on Sti 5518’ s output, is processed by CS4335 (IC500) and amplified by LM833 (IC200) and then outputed through scart(pl203) and pl750. When FB signal (pin16 of scart)is high(>2V) RGB signals are selected by TV as input and when it is low then CVBS output is selected as an input by tv .TV is activated by pin8 of scart. When pin8 is about 12 volt tv is forced to 4:3 mode , when it is about 6 V tv is forced to 16:9 mode and when it is 0v TV can not get any video. VCR pin8 pin has the highest priority so, what ever the dvb-t receiver’s mode TV will show the vcr’s output .If vcr output does not have pin8 output then user must force the dvb-t receiver to AV mode to activate VCR.. Some program information is stored in 32Kbits EEPROM (24C32 – IC304) via I2C. An analog esd overcome(external hardware watchdog circuit that reset the mainboard if something uncontrolled happens) circuit is built on the mainboard .IC104, q124, q123 are some of the related components that reset the mainboard.If during sw download or operation of stb interrupts/reset happen in a few seconds period then Q123 TRANSİSTOR can be removed and left unconnected .without any problem. SERVICE MENU INTERFACE

FIRST TIME INSTALLATION

In Installation menu first time installation sub-menu exists. If you choose YES by pressing SELECT button on the remote control, EEPROM and database is erased.

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SOFTWARE DOWNLOAD THROUGH rs232 connector list of the necessary equipment is as follows: • USE the “scart to rs232 connector “cable supplied • Receiver and TV • PC with “Hyper Terminal” function, Steps to be followed by the user are given below: 1. Connect the serial communication cable between the RS232 outport of the receiver and the

serial communication port (COM1 or COM2) of the PC. 2. Make sure that the PC is on and the receiver is in Power on mode. 3. Run “Hyper Terminal” program of the PC from Start / Programs / Accessories /

Communications / Hyper Terminal menu. 4. For a new connection, run Hypertrm.exe file. 5. Give a name and choose an icon for the connection. (You do not need to make a new

connection every time. You can use this name for the future connections.) 6. Choose communication port in the new coming window (COM1 or COM2) whichever you

have used in Step 1. 7. Port settings should be as follows:

Bits per second : 115200 Data Bits : 8 Parity : None Stop bits : 1 Flow control : None

8. Now Hyper Terminal connection is established. 9. Go to Transfer>Send file menu.Press “Browse” button and by using “up one level” button

find the directory where you had stored the new software in your PC.Then select the new software name by pressing “open “.Software name and its path is written in SEND FILE “file Name “ bar.Also check that 1K Xmodem option is selected in the “ protocol” menu.Then press ”send” button of SEND FILE menu. You will see that file is started to be transferred. If there is no transfer process that is; counter is not active then please turn off and on the stb through main power chord . During software transfer process software will be transferred with 9k packages and ACTIVE led at the front panel of the stb will be flashing red, later it will turn off for some time. PLEASE WAIT FOR UNTIL ACTIVE LED IS FLASHING RED FOR A FEW TIMES AGAIN AND SOME DIFFERENT CHARACTERS IN THE HYPER TERMINAL SCREEN IS SEEN. During this waiting time new software is written into the flash memory and writing into the flash is not a quick process. Also waiting time increases

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as the software size increases. This waiting time may be about 3 minutes . Then activate the STB and do “first time installation” for the new software to run properly. Then you can tune to a channel and test that the new software is functioning properly.

RS232 TEST The list of the necessary equipment is as follows: Receiver and TV PC with “Hyper Terminal” function, RS232 serial communication cable (male to female modem cable). Steps to be followed by the user are given below: 1. Connect the serial communication cable between the TVSCART of the receiver and the

serial communication port (COM1 or COM2) of the PC. 2. Make sure that the PC is on and the receiver is powered off. 3. Run “Hyper Terminal” program of the PC from Start / Programs / Accessories /

Communications / Hyper Terminal menu. 4. For a new connection, run Hypertrm.exe file. 5. Give a name and choose an icon for the connection. (You do not need to make a new

connection every time. You can use this name for the future connections.) 6. Choose communication port in the new coming window (COM1 or COM2) whichever you

have used in Step 1. 7. Port settings should be as follows:

Bits per second : 38400 Data Bits : 8 Parity : None Stop bits : 1 Flow control : Hardware

8. Now Hyper Terminal connection is established.When you power on the stb you will see that stb is going to stby state .Then you can activate the stb by remote control and see every result of command from the remote control

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RECEIVER UPGRADE OVER THE AIR The STB can be upgraded via the configuration menu, entered from the main menu.

In the configuration menu, there is the “Receiver Upgrade” button. Upgrade process can be started by pressing this button.

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There are two possibilities for receiver software to be upgraded: automatic and manual. Automatic upgrade can be enabled or disabled by pressing Left/Right buttons. If it is enabled, then there are two ways for automatic upgrade. The first one is checking the existence of a new software every time the STB goes to standby. The second one is waking up at 04:00 a.m. every night, provided that the STB is left in standby mode. Both automatic upgrade methods result in standby mode either upgraded or not. If the automatic upgrade is set to ‘Disable’ then this function will not work. Manual upgrade starts if the ‘Search for New Version’ button is pressed.

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After pressing the ‘Search for New Version’ button, the STB tunes to each frequency that have been stored in its database and looks for the new software. Since this process takes some time, a warning message is displayed.

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Depending on the existence of a new software, two different messages can appear on the screen: ‘No new software found. Press SELECT to exit.’ or ‘New software found! Upgrade?’ If there is no new software, pressing SELECT button returns the STB to the configuration menu.

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If there is a new software, pressing “Yes” will cause upgrading to be started. By, pressing “No” user can return to the configuration menu.

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Loading will be displayed on the screen by a message and a progress bar, together with a percentage button will indicate the status. User can cancel the upgrade any time by pressing the MENU button.

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If the upgrade is cancelled or any error is occurred during the loading process, a warning message is displayed and user is asked to press the SELECT button for returning the last watched channel.

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After loading the software into memory(SDRAM ), it will be written permanent memory (flash).If the STB power is down while new software is being written into the flash memory then new software will not run and old software will be cleaned also. The restoring code is G-O-L-F (3-5-4-2).To restore the receiver software please power off the stb from mains. When you power on the stb again you will recognize that the led at the front panel is first green for some time and then it is turning into red colour. To open the zipped software which is stored in the factory you should at least press the G button of the remote control while the led is green during start up and pressing O-L-F buttons consecutively. For the back up software to run properly do First Time Installation .

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If there is no problem during software download through the air process then the above message indicating a successful upgrade will be shown and the STB should go into standby mode in order the changes to take place.

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SCHEMATICS 16MB21E1 MAINBOARD SCHEMATIC

BILL OF MATERIALS Ürün Ağacı Pozisyon Numaralı Bileşen Listesi 20168678 MAIN.MB21Y/C+FP+RS23 2+UHFTHOMSPDIFMANE1 GEÇERLİLİK TARİHİ: 19.05.2004 - 19.05.2004

SIRA SEVİYE MALZEME TANIM BRM MİKTAR POZİSYON 1 1 20168679 MAIN.MB21Y/C+FP+RS232+UHFTHOMSPDIFRADE1 ADT 1,000 2 2 20168680 MAIN.MB21Y/C+FP+RS232+UHFTHOMSPDIFSMDE1 ADT 1,000 3 3 30000284 CAP SMD 1NF 50V K R (0805) ADT 2,000 C493 C645 4 3 30000294 CAP SMD 100NF 50V K (0805) ADT 13,000 C480 C120 C458 C437 C492 C637 C617 C316 C306 C307 C310 C253 C254 5 3 30000710 RES SMD 1/10W 47R J (0805) ADT 1,000 R127 6 3 30001734 JUMPER SMD (0805) ADT 13,000 S602 L810 L604 L214 S401 S402 S514 L616 S516 S517 L613 R708 R709 7 3 30001971 FERRITE SMD 600R/100MHz 200mA (805) ADT 13,000 L413 L105 L229 L228 L230 L222 L111 L112 L113 L114 L115 L116 L617 8 3 30007366 IC TSH22 (SO8) tape&reel ADT 1,000 IC103 9 3 30007378 IC LM 833(SO8) tape&reel ADT 1,000 IC200 10 3 30010028 DIODE BAS16 (SMD) ADT 4,000 Q600 Q601 Q603 Q604 11 3 30010056 IC 24C32 (SOIC8) TAPE&REEL ADT 1,000 IC303 12 3 30010555 CAP SMD 1UF 16V K R (0805) ADT 2,000 C489 C101 13 3 30010689 DIODE VAR BB133 SMD ADT 2,000 D100 D101 14 3 30010780 IC 74HCU04 (SO14) tape&reel ADT 1,000 IC102 15 3 30010822 IC M74HC4052 (SO16) tape&reel ADT 2,000 IC602 IC603 16 3 30012506 RES SMD 1/16W 1.5K J (0603) ADT 2,000 R400 R700 17 3 30012510 RES SMD 1/16W 100R J (0603) ADT 7,000 R251 R252 R404 R612 R139 R146 R719 18 3 30012551 TR BC847B SMD ADT 23,000 Q101 Q102 Q104 Q106 Q107 Q108 Q119 Q200 Q201 Q202 Q208 Q210 Q211 Q212 Q403 Q605 Q606 Q120 Q121 Q123 Q213 Q214 Q215 19 3 30012552 TR BC857B SMD ADT 8,000 Q100 Q103 Q203 Q204 Q205 Q209 Q602 Q124

16MB21E1PCBILEAYNI.zip

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20 3 30012559 CAP SMD 10PF 50V D COG (0603). ADT 1,000 C464 21 3 30012560 CAP SMD 100PF 50V J (0603) ADT 4,000 C409 C445 C446 C141 22 3 30012564 CAP SMD 18PF 50V J (0603) ADT 4,000 C255 C256 C470 C469 23 3 30012567 CAP SMD 220PF 50V J (0603) ADT 4,000 C228 C230 C232 C264 24 3 30012568 CAP SMD 270PF 50V J (0603) ADT 2,000 C226 C231 25 3 30012570 CAP SMD 330PF 50V J (0603) ADT 2,000 C122 C606 26 3 30012573 CAP SMD 47PF 50V J (0603) ADT 9,000 C200 C203 C204 C207 C208 C209 C225 C227 C649 27 3 30012577 CAP SMD 560PF 50V J (0603) ADT 1,000 C633 28 3 30012579 CAP SMD 82PF 50V J (0603) ADT 2,000 C460 C461 29 3 30012581 CAP SMD 1NF 50V K R (0603) ADT 30,000 C244 C245 C246 C473 C474 C601 C602 C603 C604 C277 C274 C275 C276 C266 C265 C272 C271 C273 C499 C503 C494 C495 C496 C497 C498 C504 C642 C643 C644 C646 30 3 30012582 CAP SMD 10NF 50V K R (0603) ADT 12,000 C100 C102 C104 C114 C117 C404 C411 C414 C415 C420 C429 C433 31 3 30012599 CAP SMD 33PF 25V J COG (0603) ADT 1,000 C650 32 3 30012603 CAP SMD 100NF 25V K R (0603) ADT 4,000 C249 C251 C648 C139 33 3 30012607 CAP SMD 150PF 50V J (0603) ADT 1,000 C462 34 3 30012616 CAP SMD 2.7NF 50V K B (0603) ADT 2,000 C221 C222 35 3 30012641 RES SMD 1/16W 10K J (0603) ADT 17,000 R108 R110 R112 R113 R114 R115 R154 R269 R305 R318 R409 R741 R160 R739 R754 Ürün Ağacı Pozisyon Numaralı Bileşen Listesi ZMRUA088 19.05.2004 SULEYMANE 12:03:59 Sayfa No: 2 20168678 MAIN.MB21Y/C+FP+RS23 2+UHFTHOMSPDIFMANE1 GEÇERLİLİK TARİHİ: 19.05.2004 - 19.05.2004

SIRA SEVİYE MALZEME TANIM BRM MİKTAR POZİSYON R755 R756 36 3 30012649 RES SMD 1/16W 150R J (0603) ADT 1,000 R608 37 3 30012650 RES SMD 1/16W 15K J (0603) ADT 1,000 R268 38 3 30012655 RES SMD 1/16W 180R J (0603) ADT 2,000 R428 R449 39 3 30012657 RES SMD 1/16W 1K J (0603) ADT 10,000 R107 R109 R116 R247 R248 R249 R250 R421 R744 R59 40 3 30012658 RES SMD 1/16W 1M J (0603) ADT 1,000 R122 41 3 30012659 RES SMD 1/16W 2.2K J (0603) ADT 17,000 R197 R199 R401 R402 R411 R410 R415 R416 R609 R758 R277 R278 R279 R214 R219 R220 R284 42 3 30012662 RES SMD 1/16W 2.7K J (0603) ADT 2,000 R100 R103 43 3 30012667 RES SMD 1/16W 220K J (0603) ADT 2,000 R221 R222 44 3 30012668 RES SMD 1/16W 220R J (0603) ADT 9,000 R275 R291 R292 R293 R294 R295 R296 R283 R240

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45 3 30012669 RES SMD 1/16W 22K J (0603) ADT 14,000 R123 R129 R130 R131 R132 R320 R613 R600 R602 R603 R605 R618 R626 R701 46 3 30012673 RES SMD 1/16W 270R J (0603) ADT 2,000 R276 R740 47 3 30012677 RES SMD 1/16W 3.3K J (0603) ADT 1,000 R200 48 3 30012678 RES SMD 1/16W 3.3M J (0603) ADT 1,000 R742 49 3 30012684 RES SMD 1/16W 330R J (0603) ADT 4,000 R615 R625 R239 R270 50 3 30012688 RES SMD 1/16W 390R J (0603) ADT 3,000 R282 R281 R280 51 3 30012692 RES SMD 1/16W 4.7K J (0603) ADT 12,000 R133 R287 R418 R419 R621 R622 R623 R624 R627 R631 R632 R738 52 3 30012694 RES SMD 1/16W 470K J (0603) ADT 2,000 R118 R119 53 3 30012695 RES SMD 1/16W 470R J (0603) ADT 8,000 R223 R225 R227 R408 R616 R218 R216 R213 54 3 30012696 RES SMD 1/16W 47K J (0603) ADT 4,000 R245 R246 R470 R720 55 3 30012698 RES SMD 1/16W 5.6K J (0603) ADT 2,000 R198 R271 56 3 30012707 RES SMD 1/16W 680R J (0603) ADT 5,000 R212 R217 R273 R617 R215 57 3 30012712 RES SMD 1/16W 8.2K J (0603) ADT 4,000 R120 R128 R226 R229 58 3 30012713 RES SMD 1/16W 75R J (0603) ADT 9,000 R101 R102 R117 R147 R447 R448 R614 R745 R451 59 3 30012714 RES SMD 1/16W 820R J (0603) ADT 1,000 R241 60 3 30012800 IC DAC CS4335 tape&reel ADT 1,000 IC500 61 3 30012982 RES SMD 1/16W 10R J 0603 ADT 3,000 R403 R407 R414 62 3 30012985 JUMPER SMD 0603 ADT 10,000 R406 R405 R288 R289 S303 S513 R721 S43 S44 S606 63 3 30012986 RES SMD 1/16W 68R J (0603) ADT 5,000 R274 R244 R706 R705 R707 64 3 30012987 RES SMD 1/16W 56R J (0603) ADT 3,000 R230 R224 R228 65 3 30013412 FERRITE SMD 1.5K/100MHz (0805) ADT 32,000 S301 L7 L8 L10 L11 L12 L13 L104 L110 L107 L106 L108 L109 L226 L224 L225 L223 L15 L14 L16 L17 L18 R628 R629 R630 R633 L614 L100 R158 R159 R465 R456 66 3 30014022 RES SMD 1/16W 47R J (0603) ADT 3,000 R319 R413 R417 67 3 30014088 IC SDRAM 4MX16 133MHZ tape&reel ADT 2,000 IC300 IC301 68 3 30014128 RES SMD 1/16W 33R J (0603) ADT 2,000 R463 R466 69 3 30014162 IC FLASH 16MBit (TSOP) ADT 1,000 IC302 70 3 30014180 CAP SMD 180PF 50V J (0603) ADT 1,000 C463 71 3 30016126 CAP SMD 220NF 16V K R (0603) ADT 3,000 C412 C488 C490 72 3 30016230 RES SMD 1/16W 16K F (0603) ADT 3,000 R467 R285 R286 73 3 30016424 TR BFS17P/A ADT 3,000 Q400 Q401 Q402 Ürün Ağacı Pozisyon Numaralı Bileşen Listesi ZMRUA088 19.05.2004 SULEYMANE 12:03:59 Sayfa No: 3 20168678 MAIN.MB21Y/C+FP+RS23 2+UHFTHOMSPDIFMANE1 GEÇERLİLİK TARİHİ: 19.05.2004 - 19.05.2004

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SIRA SEVİYE MALZEME TANIM BRM MİKTAR POZİSYON 74 3 30016425 DIODE BA595 ADT 1,000 D400 75 3 30016427 IC STI5518 ADT 1,000 IC100 76 3 30016651 RES SMD 1/16W 560R F (0603) ADT 8,000 R201 R202 R290 R203 R235 R236 R204 R205 77 3 30016654 CAP SMD 100NF 16V K R (0603) ADT 57,000 C112 C113 C115 C116 C118 C119 C121 C123 C124 C125 C126 C128 C129 C131 C201 C218 C235 C237 C300 C301 C303 C304 C305 C308 C309 C311 C312 C313 C314 C315 C405 C402 C403 C408 C422 C423 C416 C424 C428 C430 C434 C438 C439 C440 C451 C456 C457 C477 C487 C611 C615 C616 C621 C623 C260 C261 C514 78 3 30016659 COIL 1UH (0805) SMD ADT 3,000 L401 L402 L822 79 3 30016845 RES SMD 1/16W 18K F(0603) ADT 1,000 R610 80 3 30017001 IC MAX809LTR (RESET IC) ADT 1,000 IC5 81 3 30017143 FIXED COIL SMD 22UH J Q25 125mA (2520) ADT 10,000 L101 L102 L103 L208 L210 L211 L212 L404 L824 L207 82 3 30017542 FIXED COIL SMD 10UH J Q25 155mA (2520) ADT 2,000 L823 L231 83 3 30017653 RES SARRAY 1/16W 47RX4 J (0603) ADT 2,000 R443 R444 84 3 30017973 RES SMD 1/16W 2.32K F (0603) ADT 1,000 R604 85 3 30018612 COIL 330nH (0805) SMD ADT 2,000 L411 L412 86 3 30019104 CAP SMD 2PF 50V J (0603) ADT 1,000 C471 87 3 30020607 IC LDO LM1117 1.8V/800mA SOT223 ADT 1,000 IC402 88 3 30020847 RES SMD 1/16W 510K J (0603) ADT 1,000 R468 89 3 30020848 CAP SMD 36PF 50V D COG (0603) ADT 3,000 C435 C436 C502 90 3 30020849 IC STV0360 ADT 1,000 IC401 91 3 30021960 RES SMD 1/16W 47R J (0402) ADT 5,000 R730 R729 R306 R300 R310 92 3 30021991 RES SMD 1/16W 100R J (0402) ADT 1,000 R106 93 3 30024811 RES SMD 1/16W 33K F(0603) ADT 2,000 R104 R105 94 3 30025953 DIODE 1N4148 SE (SOT23) ADT 1,000 IC104 95 3 30026054 RES SARRAY 1/32W 47R J (0402) ADT 20,000 R731 R732 R728 R727 R724 R725 R726 R733 R734 R735 R736 R737 R302 R144 R311 R312 R746 R747 R748 R752 96 3 30030840 PCB 16MB21E1 ADT 1,000 97 2 30000345 CAP EL 10UF 50V M ADT 11,000 C135 C136 C137 C233 C241 C242 C247 C248 C406 C610 C133 98 2 30000352 CAP EL 100UF 16V M ADT 15,000 C132 C215 C257 C410 C453 C475 C476 C484 C600 C609 C622 C630 C631 C635 C238 99 2 30000353 CAP EL 100UF 25V M ADT 4,000 C205 C608 C618 C619 100 2 30000375 CAP EL 220UF 16V M ADT 4,000 C481 C485 C614 C515 101 2 30000384 CAP EL 2.2UF 50V M ADT 4,000 C214 C216 C472 C262

SERVICE MANUAL

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102 2 30000400 CAP EL 47UF 50V M ADT 5,000 C252 C401 C612 C624 C625 103 2 30000407 CAP EL 470UF 16V M ADT 4,000 C607 C634 C636 C486 104 2 30011011 FIXED COIL 22UH J RAD ADT 1,000 L405 105 1 30000359 CAP EL 1000UF 16V M. ADT 1,000 C605 106 1 30000382 CAP EL 2200UF 16V M ADT 1,000 C632 107 1 30001130 RES MO 1/2W 0.22R J ADT 1,000 R702 108 1 30001158 RES MO 1/2W 0.33R J ADT 1,000 R606 109 1 30001197 RES MO 2W 6.8R J ADT 1,000 R471 110 1 30001329 DIODE 1N4007 1A/1000V 30A ADT 2,000 D601 D602 Ürün Ağacı Pozisyon Numaralı Bileşen Listesi ZMRUA088 19.05.2004 SULEYMANE 12:03:59 Sayfa No: 4 20168678 MAIN.MB21Y/C+FP+RS23 2+UHFTHOMSPDIFMANE1 GEÇERLİLİK TARİHİ: 19.05.2004 - 19.05.2004

SIRA SEVİYE MALZEME TANIM BRM MİKTAR POZİSYON 111 1 30001377 DIODE ZENER 33V UZT 33B ADT 1,000 D604 112 1 30001835 CONN HEADER 3P 2.5MM TOP WHT SD ADT 1,000 PL105 113 1 30001851 CONN HEADER 7P 2.5MM TOP WHT ADT 1,000 PL107 114 1 30002170 FERRITE CORE 1A RAD (FTZ) ADT 6,000 L601 L607 L608 L826 L827 L619 115 1 30002838 CAP EL 470UF 6.3V M ADT 2,000 C638 C452 116 1 30007367 XTAL 27MHZ R=20 OHM ADT 2,000 X100 X400 117 1 30010902 CONN HEADER 20P 2.54MM TOP DR WO/LOCK ADT 1,000 PL100 118 1 30010940 JACK DC ADT 1,000 JK1 119 1 30011596 SOCKET SCART (SATELLITE) ADT 2,000 PL201 PL601 120 1 30015953 FILTER SAW X6966M ADT 1,000 Z400 121 1 30016451 FIXED COIL IF Q=30 7.96KHZ ADT 1,000 L400 122 1 30019382 DIODE SCH 1N5819 1A/40V (DO-41) ADT 2,000 D603 D600 123 1 30020954 IC STEP UP MC34063 1.5A (DIP-8) ADT 2,000 IC600 IC601 124 1 30020955 COIL PEAKING 220 UH RADIAL ADT 2,000 L602 L603 125 1 30023535 JACK RCA 1P(SCP-625V) MINI PING ADT 1,000 JK3 126 1 30023813 TUNER TERRESTRIAL UHF DTT7107 (HOR) ADT 1,000 TU400 127 1 50010715 UYDU ALICISI IC TEST ETİKETİ ADT 1,000 128 1 50010759 LABEL SERIAL NO (UNIVERSAL) ADT 1,000