2
how to draw timing diagram?discuss the various steps You first need to understand the machine cycles of 8085 The status signals are as follows IO/M(bar) :--- 1 IO 0 Memory S1 | S0 | Process ----------------------------------------------------------- 0 | 0 | Halt 0 | 1 | Write 1 | 0 | Read 1 | 1 | Opcode fetch 1)Opcode fetch ( Compulsory Machine cycle) This cycle requires 4 T-states. 1st T state ALE is high and lower byte of address from PC(Program Counter) is placed on the multiplexed data/address bus. In the second T-state, after checking the status of READY pin, RD(bar) goes low the opcode is placed on the data bus, This state continues in the 3rd T- State. The fourth T-state is used by the uP to decode the instruction and to generate the relevant control signals. The state of the address bus is unspecified( This T-state is used by some DMA controllers to transfer data in hidden/transperant mode) IO/M_ = 0 S1=1 S0=1 2)Memory read(for 1 byte) Three T states, similar to the first 3 T states of opcode fetch( as first 3 states of opcode fetch is effectively memory read) IO/M_ 0 S1 = 1 S0 = 0 3) Memory Write(for 1 byte) Similar to Write but instead of RD bar WR bar is used. Also the data stays on the bus a little longer than READ*. IO/M_ 0 S1 = 0 S0 = 1 4) & 5) IO write and read Simlar to the above two, only IO/M_ = 1 These are the basic machine cycles you will require to draw timing diagrams for most instructions. There are additional cycles such as INTA bar and Bus idle. If anyone requires diagrams for these cycles, message me and i will explain them later. Also some instructions like CALL require 6 T-state Opcode fetch. For this you can draw the 4 T state Opcode fetch but 4th T state extended to the fifth and sixth T state. ------------------------------------------------------------------------------ ------------

T States Calculation

Embed Size (px)

Citation preview

Page 1: T States Calculation

how to draw timing diagram?discuss the various steps You first need to understand the machine cycles of 8085 The status signals are as follows IO/M(bar) :--- 1 IO 0 Memory S1 | S0 | Process----------------------------------------------------------- 0 | 0 | Halt 0 | 1 | Write 1 | 0 | Read 1 | 1 | Opcode fetch 1)Opcode fetch ( Compulsory Machine cycle)This cycle requires 4 T-states. 1st T state ALE is high and lower byte of address from PC(Program Counter) is placed on the multiplexed data/address bus. In the second T-state, after checking the status of READY pin, RD(bar) goes low the opcode is placed on the data bus, This state continues in the 3rd T-State. The fourth T-state is used by the uP to decode the instruction and to generate the relevant control signals. The state of the address bus is unspecified( This T-state is used by some DMA controllers to transfer data in hidden/transperant mode) IO/M_ = 0 S1=1 S0=1 2)Memory read(for 1 byte)Three T states, similar to the first 3 T states of opcode fetch( as first 3 states of opcode fetch is effectively memory read) IO/M_ 0 S1 = 1 S0 = 0 3) Memory Write(for 1 byte)Similar to Write but instead of RD bar WR bar is used. Also the data stays on the bus a little longer than READ*. IO/M_ 0 S1 = 0 S0 = 1 4) & 5) IO write and readSimlar to the above two, only IO/M_ = 1 These are the basic machine cycles you will require to draw timing diagrams for most instructions. There are additional cycles such as INTA bar and Bus idle. If anyone requires diagrams for these cycles, message me and i will explain them later. Also some instructions like CALL require 6 T-state Opcode fetch. For this you can draw the 4 T state Opcode fetch but 4th T state extended to the fifth and sixth T state. ------------------------------------------------------------------------------------------Now, to draw the timing diagram for any instruction you need to understand what exactly the instruction does. I will explain a few. If you need a specific instruction, msg me.A) MOV A,BDraw only opcode fetch as no further memory acces is required as operands specified in registers only B) MVI A,32HDraw opcode fetch and memory read as operand(1 byte) has to be fetched from memory C) LXI H, 2000HDraw Opcode Fetch and two memory Reads as two bytes, 00H and 20H, (lower byte fetched first) have to be read from memory. D) STA 2000H

Page 2: T States Calculation

This instruction stores the value of accumulator(8 bit) at the location specified. Opcode fetch + Memory read * 2 (byte address) + Memory write * 1(1 byte) i.e 13 T-states 4+3+3+3 During the memory write the address bus contains the address fetched by the memory read cycle earlier E) CALL addresss(can be specifed in terms of a label)During a call instruction the uP pushes the current value of program counter(16 bit ie 2 byte) to the stack and then copies the new value from the memory(specified in the instruction) 6 T state Opcode fetch + Memory write * 2 (PC pushed to stack) + Memory read * 2 (New value of PC fetched from memory) ie 6 + 3 + 3 + 3 + 3 = 18 T-states Note that during the memory write cycle the address bus contains the address of the top of the stack(Stack Pointer) 

F)JMP 16-bit address3 Cycles as Follows 

4 T-State Opcode Fetch + 2 * Memory Read ( 16 bit = 2 bytes) ie 4 + 3 + 3 = 10 T-states. Note that seperate cycle is not required for loading the address into the PC as PC is a register.