Syst

ems

Des

ign

& P

rogr

amm

ing

8086

/88

Chi

p Se

tC

MPE

310

1(F

eb. 2

0, 2

002)

UM

BC

U M

B C

UNIVERSITY OF M

AR

YL

AN

D B

ALTIM

ORE COUNTY

1 9

6 6

8086

/88

Dev

ice

Spec

ifica

tion

sBo

th a

re p

acka

ged

in D

IP (D

ual I

n-Li

ne P

acka

ges)

.•

8086

: 16-

bit m

icro

proc

esso

r w

ith

a16

-bit

dat

a bu

s•

8088

: 16-

bit m

icro

proc

esso

r w

ith

an8-

bit d

ata

bus.

Both

are

5V

par

ts:

• 80

86: D

raw

s a

max

imum

sup

ply

curr

ent o

f 360

mA

.•

8086

: Dra

ws

a m

axim

um s

uppl

y cu

rren

t of 3

40m

A.

• 80

C86

/80C

88: C

MO

S ve

rsio

n dr

aws

10m

A w

ith

tem

p sp

ec -4

0 to

225

degF

.

Inpu

t/O

utpu

t cur

rent

leve

ls:

Yiel

dsa

350m

Vno

ise

imm

unit

yfo

rlog

ic0

(Out

putm

axca

nbe

ashi

ghas

450m

V w

hile

inpu

t max

can

be

no h

ighe

r th

an 8

00m

V).

This

lim

its

the

load

ing

on th

e ou

tput

s.

Logi

c le

vel

Volt

age

Cur

rent

00.

8V m

ax+/

- 10u

A m

ax1

2.0V

min

+/- 1

0uA

max

Logi

c le

vel

Volt

age

Cur

rent

00.

45V

max

+2m

A m

ax1

2.4V

min

- 400

uA m

ax

INPU

TO

UTP

UT

Syst

ems

Des

ign

& P

rogr

amm

ing

8086

/88

Chi

p Se

tC

MPE

310

2(F

eb. 2

0, 2

002)

UM

BC

U M

B C

UNIVERSITY OF M

AR

YL

AN

D B

ALTIM

ORE COUNTY

1 9

6 6

8086

/88

Pin

out

GN

DC

LK

INT

RN

MI

AD

0A

D1

AD

2A

D3

AD

4A

D5

AD

6A

D7

AD

8A

D9

AD

10A

D11

AD

12A

D13

AD

14G

ND

RE

SET

RE

AD

YT

EST

(QS1

)(Q

S0)

( S0)

( S1)

(S2)

( LO

CK

)( R

Q/G

T1)

( RQ

/GT

0)R

DM

N/M

XB

HE

/S7

A19

/S6

A18

/S5

A17

/S4

A16

/S3

AD

15V

CC

WR

HL

DA

Hol

d

M/I

OD

T/R

DE

NA

LE

INT

A

MIN

MO

DE

(M

AX

MO

DE

)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

8086

CPU

Syst

ems

Des

ign

& P

rogr

amm

ing

8086

/88

Chi

p Se

tC

MPE

310

3(F

eb. 2

0, 2

002)

UM

BC

U M

B C

UNIVERSITY OF M

AR

YL

AN

D B

ALTIM

ORE COUNTY

1 9

6 6

8086

/88

Pin

out

Pin

func

tion

s: A

D15

-AD

0M

ulti

plex

ed a

ddre

ss(A

LE=1

)/da

ta b

us(A

LE=0

). A

19/S

6-A

16/S

3 (m

ulti

plex

ed)

Hig

h or

der

4 bi

ts o

f the

20-

bit a

ddre

ss O

R s

tatu

s bi

ts S

6-S3

. M

/IO

Indi

cate

s if

add

ress

is a

Mem

ory

or IO

add

ress

.R

D Whe

n 0,

dat

a bu

s is

dri

ven

by m

emor

y or

an

I/O

dev

ice.

WR M

icro

proc

esso

ris

driv

ing

data

bus

tom

emor

yor

anI/

Ode

vice

.Whe

n0,

data

bus

con

tain

s va

lid d

ata.

ALE

(Add

ress

latc

h en

able

)W

hen

1, a

ddre

ss d

ata

bus

cont

ains

a m

emor

y or

I/O

add

ress

. D

T/R

(Dat

a Tr

ansm

it/R

ecei

ve)

Dat

a bu

s is

tran

smit

ting

/rec

eivi

ng d

ata.

DEN

(Dat

a bu

s En

able

)A

ctiv

ates

ext

erna

l dat

a bu

s bu

ffer

s.

Syst

ems

Des

ign

& P

rogr

amm

ing

8086

/88

Chi

p Se

tC

MPE

310

4(F

eb. 2

0, 2

002)

UM

BC

U M

B C

UNIVERSITY OF M

AR

YL

AN

D B

ALTIM

ORE COUNTY

1 9

6 6

8086

/88

Pin

out

Pin

func

tion

s: S

7, S

6, S

5, S

4, S

3,S2

,S1,

S0S7

: Log

ic 1

, S6:

Log

ic 0

.S5

: Ind

icat

es c

ondi

tion

of I

F fla

g bi

ts.

S4-S

3: In

dica

te w

hich

seg

men

t is

acce

ssed

dur

ing

curr

ent b

us c

ycle

:

S2,S

1,S0

: Ind

icat

e fu

ncti

on o

f cur

rent

bus

cyc

le (d

ecod

ed b

y 82

88).

S4S3

Func

tion

00

Extr

a se

gmen

t0

1St

ack

segm

ent

10

11

Cod

e or

no

segm

ent

Dat

a se

gmen

t

S2S1

Func

tion

00

Inte

rrup

t Ack

01

I/O

Rea

d1

01

1I/

O W

rite

Hal

t

S00 0 0 0

S2S1

Func

tion

00

Opc

ode

Fetc

h0

1M

emor

y R

ead

10

11

Mem

ory

Wri

tePa

ssiv

e

S01 1 1 1

Syst

ems

Des

ign

& P

rogr

amm

ing

8086

/88

Chi

p Se

tC

MPE

310

5(F

eb. 2

0, 2

002)

UM

BC

U M

B C

UNIVERSITY OF M

AR

YL

AN

D B

ALTIM

ORE COUNTY

1 9

6 6

8086

/88

Pin

out

Pin

func

tion

s: IN

TR

Whe

n 1

and

IF=1

, mic

ropr

oces

sor

prep

ares

to s

ervi

ce in

terr

upt.

INTA

beco

mes

act

ive

afte

r cu

rren

t ins

truc

tion

com

plet

es.

INTA In

terr

uptA

ckno

wle

dge

gene

rate

dby

the

mic

ropr

oces

sor

inre

spon

seto

INTR

. Cau

ses

the

inte

rrup

t vec

tor

to b

e pu

t ont

o th

e da

ta b

us.

NM

IN

on-m

aska

ble

inte

rrup

t. Si

mila

r to

INTR

exc

ept I

F fla

g bi

t is

not c

on-

sult

ed a

nd in

terr

upt i

s ve

ctor

2.

CLK C

lock

inpu

t mus

t hav

e a

duty

cyc

le o

f 33%

(hig

h fo

r 1/

3 an

d lo

w fo

r 2/

3s)

VC

C/G

ND

Pow

er s

uppl

y (5

V) a

nd G

ND

(0V

).

Syst

ems

Des

ign

& P

rogr

amm

ing

8086

/88

Chi

p Se

tC

MPE

310

6(F

eb. 2

0, 2

002)

UM

BC

U M

B C

UNIVERSITY OF M

AR

YL

AN

D B

ALTIM

ORE COUNTY

1 9

6 6

8086

/88

Pin

out

Pin

func

tion

s: M

N/M

XSe

lect

min

imum

(5V

) or

max

imum

mod

e (0

V) o

f ope

rati

on.

BHE Bu

s H

igh

Enab

le. E

nabl

es th

e m

ost s

igni

fican

t dat

a bu

s bi

ts (D

15-D

8)

duri

ng a

rea

d or

wri

te o

pera

tion

.

REA

DY

Use

d to

inse

rt w

ait s

tate

s (c

ontr

olle

d by

mem

ory

and

IO fo

r re

ads/

wri

tes)

into

the

mic

ropr

oces

sor.

RES

ETM

icro

proc

esso

r re

sets

if th

is p

in is

hel

d hi

gh fo

r 4

cloc

k pe

riod

s.In

stru

ctio

n ex

ecut

ion

begi

ns a

t FFF

F0H

and

IF fl

ag is

cle

ared

.

TEST A

n in

put t

hat i

s te

sted

by

the

WA

IT in

stru

ctio

n.C

omm

only

con

nect

ed to

the

8087

cop

roce

ssor

.

Syst

ems

Des

ign

& P

rogr

amm

ing

8086

/88

Chi

p Se

tC

MPE

310

7(F

eb. 2

0, 2

002)

UM

BC

U M

B C

UNIVERSITY OF M

AR

YL

AN

D B

ALTIM

ORE COUNTY

1 9

6 6

8086

/88

Pin

out

Pin

func

tion

s: H

OLD Req

uest

s a

dire

ct m

emor

y ac

cess

(DM

A).

Whe

n 1,

mic

ropr

oces

sor

stop

san

d pl

aces

add

ress

, dat

a an

d co

ntro

l bus

in h

igh-

impe

danc

e st

ate.

HLD

A (H

old

Ack

now

ledg

e)In

dica

tes

that

the

mic

ropr

oces

sor

has

ente

red

the

hold

sta

te.

RO

/GT1

and

RO

/GT0

Req

uest

/gra

nt p

ins

requ

est/

gran

t dir

ect m

emor

y ac

cess

es (D

MA

) dur

-in

g m

axim

um m

ode

oper

atio

n.

LOC

KLo

ck o

utpu

t is

used

to lo

ck p

erip

hera

ls o

ff th

e sy

stem

. Act

ivat

ed b

yus

ing

the

LOC

K: p

refix

on

any

inst

ruct

ion.

QS1

and

QS0

The

que

ue s

tatu

s bi

ts s

how

sta

tus

of in

tern

al in

stru

ctio

n qu

eue.

Pro

-vi

ded

for

acce

ss b

y th

e nu

mer

ic c

opro

cess

or (8

087)

.

Syst

ems

Des

ign

& P

rogr

amm

ing

8086

/88

Chi

p Se

tC

MPE

310

8(F

eb. 2

0, 2

002)

UM

BC

U M

B C

UNIVERSITY OF M

AR

YL

AN

D B

ALTIM

ORE COUNTY

1 9

6 6

8284

A C

lock

Gen

erat

orBa

sic

func

tion

s: C

lock

gen

erat

ion.

RES

ET s

ynch

roni

zati

on.

REA

DY

syn

chro

niza

tion

. P

erip

hera

l clo

ck s

igna

l.

Con

nect

ion

of th

e 82

84 a

nd th

e 80

86.

1 2 3 4 5 6 7 8 9

18 17 16 15 14 13 12 11 10

8284AC

LK

CSY

NC

RE

SET

F/C

X2

X1

�������

Cry

stal

OSC

15M

Hz

8086

CL

KR

ESE

T

Syst

ems

Des

ign

& P

rogr

amm

ing

8086

/88

Chi

p Se

tC

MPE

310

9(F

eb. 2

0, 2

002)

UM

BC

U M

B C

UNIVERSITY OF M

AR

YL

AN

D B

ALTIM

ORE COUNTY

1 9

6 6

8284

A C

lock

Gen

erat

or

GN

DC

LK

AE

N2

RD

Y2

RE

AD

YR

DY

1A

EN

1P

CL

KC

SYN

C

RE

SET

RE

SO

SCF

/ CE

FI

ASY

NC

X2

X1

VC

C1 2 3 4 5 6 7 8 9

18 17 16 15 14 13 12 11 108284A

DQ

RES

ETR

ES

OSC

XTA

LO

SC

X1

X2

+2PC

LK

F/C

EFI

+3

CSY

NC

CLK

DQ

REA

DY

DQ

RD

Y1

AEN

1

AEN

2

RD

Y2

ASY

NC

Schm

itt

trig

ger

(EFI

inpu

tto

oth

er82

84A

s)

div-

by-3

cnte

r

div-

by-2

cnte

r2-

to-1

mux

Syst

ems

Des

ign

& P

rogr

amm

ing

8086

/88

Chi

p Se

tC

MPE

310

10(F

eb. 2

0, 2

002)

UM

BC

U M

B C

UNIVERSITY OF M

AR

YL

AN

D B

ALTIM

ORE COUNTY

1 9

6 6

8284

A C

lock

Gen

erat

orC

lock

gen

erat

ion:

Cry

stal

is c

onne

cted

to X

1 an

d X

2.X

TAL

OSC

gen

erat

es s

quar

e w

ave

sign

al a

t cry

stal

’s fr

eque

ncy

whi

chfe

eds:

An

inve

rtin

g bu

ffer

(out

put O

SC) w

hich

is u

sed

to d

rive

the

EFI i

nput

of o

ther

828

4As.

2-t

o-1

MU

XF/

C s

elec

ts X

TAL

or E

FI e

xter

nal i

nput

.

The

MU

X d

rive

s a

divi

de-b

y-3

coun

ter

(15M

Hz

to 5

MH

z).

This

dri

ves:

The

REA

DY

flip

flop

(REA

DY

syn

chro

niza

tion

). A

sec

ond

divi

de-b

y-2

coun

ter

(2.5

MH

z cl

k fo

r pe

riph

eral

com

pone

nts)

. T

heR

ESET

flip

flop.

CLK

whi

ch d

rive

s th

e 80

86 C

LK in

put.

Syst

ems

Des

ign

& P

rogr

amm

ing

8086

/88

Chi

p Se

tC

MPE

310

11(F

eb. 2

0, 2

002)

UM

BC

U M

B C

UNIVERSITY OF M

AR

YL

AN

D B

ALTIM

ORE COUNTY

1 9

6 6

8284

A C

lock

Gen

erat

orR

ESET

:N

egat

ive

edge

-tri

gger

edflip

flop

appl

ies

the

RES

ETsi

gnal

toth

e80

86on

the

falli

ng e

dge.

The

808

6 sa

mpl

es th

e R

ESET

pin

on

the

risi

ng e

dge.

Cor

rect

rese

ttim

ing

requ

ires

that

the

RES

ETin

putt

oth

em

icro

proc

esso

rbe

com

es a

logi

c 1

NO

LA

TER

than

4 c

lock

s af

ter

pow

er u

p an

d st

ayhi

gh fo

r at

leas

t 50u

s.

1 2 3 4 5 6 7 8 9

18 17 16 15 14 13 12 11 108284A

CL

K

CSY

NC

RE

SET

RE

S

F/C

X2

X1

���������������������

Cry

stal

OSC

15M

Hz

10uF

10K

+5V

Res

etsw

itch

8086

CL

KR

ESE

TR

C =

10K

*10u

F ~=

100

mse

c

CSY

NC

: Use

d w

ith

mul

tipl

e pr

oces

sors

.

Syst

ems

Des

ign

& P

rogr

amm

ing

8086

/88

Chi

p Se

tC

MPE

310

12(F

eb. 2

0, 2

002)

UM

BC

U M

B C

UNIVERSITY OF M

AR

YL

AN

D B

ALTIM

ORE COUNTY

1 9

6 6

BU

S B

uffe

ring

and

Lat

chin

gD

emul

tipl

exin

g th

e Bu

ses:

Com

pute

r sy

stem

s ha

ve th

ree

buse

s: A

ddre

ss D

ata

Con

trol

The

Add

ress

and

Dat

a bu

s ar

e m

ulti

plex

ed (s

hare

d) d

ue to

pin

lim

ita-

tion

s on

the

8086

.Th

e A

LE p

in c

ontr

ols

a se

t of l

atch

es.

All

sign

als

MU

ST b

e bu

ffer

ed.

Latc

hes

buff

er fo

r A

0-A

15.

Con

trol

and

A16

-A19

+BH

E ar

e bu

ffer

ed s

epar

atel

y.

Dat

a bu

s bu

ffer

s m

ust b

e bi

-dir

ecti

onal

buf

fers

(BB)

.

BHE:

Sel

ects

the

high

-ord

er m

emor

y ba

nk.

Syst

ems

Des

ign

& P

rogr

amm

ing

8086

/88

Chi

p Se

tC

MPE

310

13(F

eb. 2

0, 2

002)

UM

BC

U M

B C

UNIVERSITY OF M

AR

YL

AN

D B

ALTIM

ORE COUNTY

1 9

6 6

BU

S B

uffe

ring

and

Lat

chin

g

8086 CPU

GN

DC

LK

INT

RN

MI

AD

0A

D1

AD

2A

D3

AD

4A

D5

AD

6A

D7

AD

8A

D9

AD

10A

D11

AD

12A

D13

AD

14G

ND

RE

SET

RE

AD

YT

EST

RD

MN

/MX

BH

E/S

7A

19/S

6A

18/S

5A

17/S

4A

16/S

3A

D15

VC

C

WR

HL

DA

Hol

d

M/I

OD

T/ R

DE

NA

LE

INT

A

GG

Latc

hes

D15

D0

D7

D8

Con

trol

A0

A7

A8

A15

A19

BHE

A16

Latc

hes

Data Bus

Address Bus

Buff

er Buff

er

GD

GD

BB BB

Syst

ems

Des

ign

& P

rogr

amm

ing

8086

/88

Chi

p Se

tC

MPE

310

14(F

eb. 2

0, 2

002)

UM

BC

U M

B C

UNIVERSITY OF M

AR

YL

AN

D B

ALTIM

ORE COUNTY

1 9

6 6

BU

S T

imin

gW

riti

ng:

Dum

p ad

dres

s on

add

ress

bus

. D

ump

data

on

data

bus

. Is

sue

a w

rite

(WR

) and

set

M/I

O to

1.

T1

T 2T

3T 4

Val

id A

ddre

ss

Dat

a w

ritt

en to

mem

ory

Add

ress

WR

Add

ress

/Dat

a

Add

ress

CLK

Sim

plifi

ed 8

086

Wri

te B

us C

ycle

One

Bus

Cyc

le

Syst

ems

Des

ign

& P

rogr

amm

ing

8086

/88

Chi

p Se

tC

MPE

310

15(F

eb. 2

0, 2

002)

UM

BC

U M

B C

UNIVERSITY OF M

AR

YL

AN

D B

ALTIM

ORE COUNTY

1 9

6 6

BU

S T

imin

gR

eadi

ng:

Dum

p ad

dres

s on

add

ress

bus

. Is

sue

a re

ad (R

D) a

nd s

et M

/IO

to 1

. W

ait f

or m

emor

y ac

cess

cyc

le.

T1

T 2T

3T 4

Val

id A

ddre

ss

Dat

a fr

om m

emor

yA

ddre

ss

RD

Add

ress

/Dat

a

Add

ress

CLK

Sim

plifi

ed 8

086

Rea

d B

us C

ycle

One

Bus

Cyc

le

Syst

ems

Des

ign

& P

rogr

amm

ing

8086

/88

Chi

p Se

tC

MPE

310

16(F

eb. 2

0, 2

002)

UM

BC

U M

B C

UNIVERSITY OF M

AR

YL

AN

D B

ALTIM

ORE COUNTY

1 9

6 6

BU

S T

imin

gBu

s Ti

min

g:

T 1T

2T 3

T4

RD

M/I

O

CLK

Bus

Tim

ing

for

a R

ead

Ope

rati

on

A19

-A16

/S6-

S 3A

19-A

16S 7

-S3

AD

15-A

D0

Floa

tD

ata

InFl

oat

T w

AD

15-A

D0

ALE

DT/

R

DEN

REA

DY

800n

s20

0ns

Dat

aSe

tup

Add

ress

set

up

Syst

ems

Des

ign

& P

rogr

amm

ing

8086

/88

Chi

p Se

tC

MPE

310

17(F

eb. 2

0, 2

002)

UM

BC

U M

B C

UNIVERSITY OF M

AR

YL

AN

D B

ALTIM

ORE COUNTY

1 9

6 6

BU

S T

imin

gD

urin

g T 1

:

The

add

ress

is p

lace

d on

the

Add

ress

/Dat

a bu

s.C

ontr

olsi

gnal

sM

/IO

,ALE

and

DT/

Rsp

ecif

ym

emor

yor

I/O

,lat

chth

ead

dres

s on

to th

e ad

dres

s bu

s an

d se

t the

dir

ecti

on o

f dat

a tr

ansf

er o

nda

ta b

us.

Dur

ing

T 2:

808

6 is

sues

the

RD

or

WR

sig

nal,

DEN

, and

, for

a w

rite

, the

dat

a.D

ENen

able

sth

em

emor

yor

I/O

devi

ceto

rece

ive

the

data

forw

rite

san

d th

e 80

86 to

rec

eive

the

data

for

read

s.D

urin

g T 3

:

Thi

s cy

cle

is p

rovi

ded

to a

llow

mem

ory

to a

cces

s da

ta.

REA

DY

is s

ampl

ed a

t the

end

of T

2.

If lo

w, T

3 be

com

es a

wai

t sta

te.

Oth

erw

ise,

the

data

bus

is s

ampl

ed a

t the

end

of T

3.

Dur

ing

T 4:

All

bus

sign

als

are

deac

tiva

ted,

in p

repa

rati

on fo

r ne

xt b

us c

ycle

. D

ata

is s

ampl

ed fo

r re

ads,

wri

tes

occu

r fo

r w

rite

s.

Syst

ems

Des

ign

& P

rogr

amm

ing

8086

/88

Chi

p Se

tC

MPE

310

18(F

eb. 2

0, 2

002)

UM

BC

U M

B C

UNIVERSITY OF M

AR

YL

AN

D B

ALTIM

ORE COUNTY

1 9

6 6

BU

S T

imin

gTi

min

g: Each

BU

S C

YC

LE o

n th

e 80

86 e

qual

sfo

ursy

stem

clo

ckin

g pe

riod

s (T

stat

es).

The

clo

ck r

ate

is5M

Hz,

ther

efor

e on

e Bu

s C

ycle

is80

0ns.

The

tran

sfer

rat

e is

1.25

MH

z.

Mem

ory

spec

s (m

emor

y ac

cess

tim

e) m

ust m

atch

con

stra

ints

of s

yste

mti

min

g.

For

exam

ple,

bus

tim

ing

for

a re

ad o

pera

tion

sho

ws

alm

ost6

00ns

are

need

ed to

rea

d da

ta.

How

ever

, mem

ory

mus

t acc

ess

fast

er d

ue to

set

up ti

mes

, e.g

.A

ddre

ss s

etup

and

dat

a se

tup.

This

sub

trac

ts o

ff a

bout

150n

s.Th

eref

ore,

mem

ory

mus

t acc

ess

in a

t lea

st45

0ns

min

us a

noth

er30

-40

ns g

uard

ban

d fo

r bu

ffer

s an

d de

code

rs.

420n

s D

RA

M r

equi

red

for

the

8086

.

Syst

ems

Des

ign

& P

rogr

amm

ing

8086

/88

Chi

p Se

tC

MPE

310

19(F

eb. 2

0, 2

002)

UM

BC

U M

B C

UNIVERSITY OF M

AR

YL

AN

D B

ALTIM

ORE COUNTY

1 9

6 6

BU

S T

imin

gR

EAD

Y:A

n in

put t

o th

e 80

86 th

at c

ause

s w

ait s

tate

s fo

r sl

ower

mem

ory

and

I/O

com

pone

nts.

A w

ait s

tate

(TW

) is

an e

xtra

clo

ck p

erio

d in

sert

ed b

etw

een

T2

and

T3

to

leng

then

the

bus

cycl

e.Fo

r ex

ampl

e, th

is e

xten

ds a

460n

s bu

s cy

cle

(at 5

MH

z cl

ock)

to66

0ns.

Text

dis

cuss

es r

ole

of 8

284A

and

tim

ing

requ

irem

ents

for

the

8086

.

T 1T

2T 3

T4

CLK

Wai

t Sta

te ti

min

g

AD

15-A

D0

Floa

tD

ata

InFl

oat

T w

AD

15-A

D0

REA

DY

800n

s20

0ns

OK

Fail

REA

DY

Dat

a In

Sam

pled

aga

in

Syst

ems

Des

ign

& P

rogr

amm

ing

8086

/88

Chi

p Se

tC

MPE

310

20(F

eb. 2

0, 2

002)

UM

BC

U M

B C

UNIVERSITY OF M

AR

YL

AN

D B

ALTIM

ORE COUNTY

1 9

6 6

MIN

and

MA

X M

ode

Con

trol

led

thro

ugh

the

MN

/ MX

pin

.M

inim

um m

ode

is c

heap

er s

ince

all

cont

rol s

igna

ls fo

r m

emor

y an

d I/

O a

re g

ener

ated

by

the

mic

ropr

oces

sor.

Max

imum

mod

e is

des

igne

d to

be

used

whe

n a

copr

oces

sor

(808

7)ex

ists

in th

e sy

stem

.

Som

e of

the

cont

rol s

igna

ls m

ust b

e ge

nera

ted

exte

rnal

ly, d

ue to

red

efini

tion

of c

erta

in c

ontr

ol p

ins

on th

e 80

86.

The

follo

win

g pi

ns a

re lo

st w

hen

the

8086

ope

rate

s in

Max

imum

mod

e. A

LEW

R IO

/M D

T/R

DEN

INTA

This

req

uire

s an

ext

erna

l bus

con

trol

ler:

The

8288

Bus

Con

trol

ler.

Syst

ems

Des

ign

& P

rogr

amm

ing

8086

/88

Chi

p Se

tC

MPE

310

21(F

eb. 2

0, 2

002)

UM

BC

U M

B C

UNIVERSITY OF M

AR

YL

AN

D B

ALTIM

ORE COUNTY

1 9

6 6

8288

Bus

Con

trol

ler

Sepa

rate

sig

nals

are

use

d fo

r I/

O ( I

OR

C a

ndIO

WC

) and

mem

ory

(MR

DC

and

MW

TC).

Als

o pr

ovid

ed a

re a

dvan

ced

mem

ory

(AIO

WC

) and

I/O

(AIO

WC

) wri

test

robe

s pl

usIN

TA.

IOB

CL

KS1 D

T/R

AL

EA

EN

MR

DC

AM

WC

MW

TC

GN

D

VC

C S0 S2M

CE

/PD

ND

EN

CE

NIN

TA

IOR

CA

IOW

CIO

WC

8288

8086

Stat

us

S0 S1 S2 CL

K

AE

N

CE

N

IOB

MR

DC

MW

TC

AM

WC

IOR

CIO

WC

AIO

WC

INT

A

DT

/RD

T/R

DE

NM

CE

/PD

EN

AL

E

Con

trol

Inpu

t

Stat

usD

ecod

erC

omm

and

Sign

alG

ener

-at

or

Con

trol

Sign

alG

ener

-at

or

Con

trol

Log

ic

Syst

ems

Des

ign

& P

rogr

amm

ing

8086

/88

Chi

p Se

tC

MPE

310

22(F

eb. 2

0, 2

002)

UM

BC

U M

B C

UNIVERSITY OF M

AR

YL

AN

D B

ALTIM

ORE COUNTY

1 9

6 6

MA

X M

ode

8086

Sys

tem

GN

D

VC

C RES

CLK

REA

DY

RES

ET

S0 S1 S2

8086

8288

CL

K

DEN

DT/

RA

LEC

PU

AD

0-A

D15

S0 S1 S2

Latc

hes

STB 82

86Tr

ansc

eive

r

T OE

8259

AIn

terr

upt

Con

trol

ler

RA

M

MR

DC

MW

TC

IOR

CIO

WC

INTA

Add

ress

Dat

aIN

T

RD

WR

IRQ

0-7

8284

A