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System Programming
1 1 2 1. 1.2. 2. 1.2.3. 3. 1.2.3.
4.5.6.one pass 4. 1.2.3. 5. 1.2. 6. 1.2.
7 1 2 7. 1.2.
(BeckSystem SoftwareAn Introduction to
Systems Programming 3/E)(/): (/):
: 2010 :
(+)(+) 35% 30% 35% 35%
,
Application
Compiler Loader LinkerDebuggerA bl M P O ti S t AssemblerMacro ProcesserOperating System
,
UNIX (Linux), DOS: MacOS Windows: MacOS, Windows:
,
1 Preprocess #ifdef #define1. Preprocess #ifdef #define
2 Compile 2. Compile 3. Assemble OS
relocatable objrelocatable obj4. Link symbol()(shared
obj) obj(executableobj) obj(executable obj)
(1) (1)
(Source Program in Source Language)(Source Program in Source Language)
Assembler
(Object Program)
(2) (2)
()()
Macro Processor
()()
(3) (3)
Compiler
(4) (4)
Linker
(5) (5)
Loader
(6) (6)
Shell Shell
Application
System Program
Si lifi d i l C Simplified Instructional ComputerSICSIC/XE
Computer based InformationComputer based Information Processing System
11
1 1 1.1 1.2
1.3 Simplified Instructional Computer Simplified Instructional ComputerSIC
1 4 1 5 1.4 1.5
1 1 1.1 system software system software
assembler languageassembler languagemacro instructions
macro processorassemblerassembler
1 2 1.2
:: , ,
(SIC)(SIC) SIC SIC
1 1. 2. 3 3.
4 4. single-passmulti-pass5 5.
1 3 SIC1.3 SIC
XE XE
1 3 1 SIC 1.3.1 SIC
bytesword24 word 24
byte address y
32,768215
1 3 1 SIC 1.3.1 SIC
1 3 1 SIC 1.3.1 SIC
24
8 ASCII B SIC SIC
24
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2
1 3 1 SIC 1.3.1 SIC SIC SIC
SIC24
xopcode x address
8 1 15
SIC
x=0 =
1 (X) x=1 =+(X)
opcode x address
8 1 15
1.3.1 SIC
LDALDXSTASTX ADDSUBMULDIV ADDSUBMULDIV COMPA JLTJEQJGT JLT JEQ JGT JSUB RSUBLRSUBL
1 3 1 SIC 1.3.1 SIC
SICA
SICI/OSICI/O Test Device, TD Read Data, RD Write Data, WD
1 3 2 SIC/XE1.3.2 SIC/XE
1 M220
B 3
S 4
T 5
F 6 48
1 3 2 SIC/XE1.3.2 SIC/XE
1 3 2 SIC/XE1.3.2 SIC/XE
O d O (Operand): (Operator)
: : : : :
1 3 2 SIC/XE1.3.2 SIC/XE
1 3 2 SIC/XE1.3.2 SIC/XE
Base Relative Program-Counter (PC) Relative Program Counter (PC) Relative
1 3 2 SIC/XE1.3.2 SIC/XE
1 F t 4 I t ti e = 1Format 4 Instruction e = 0Format 3 Instruction
(b ) (0 0)Di t Add i (b, p) = (0, 0)Direct Addressing x = 1Indexed Addressing
(i n) (1 0)Immediate Addressing (i, n) = (1, 0)Immediate Addressing (i, n) = (0, 1)Indirect Addressing i = nSimple Addressing i = nSimple Addressing
1 3 2 SIC/XE1.3.2 SIC/XE
1 3 2 SIC/XE1.3.2 SIC/XE
LDBSTB ADDFSUBFMULFADDF SUBF MULFDIVF
ADDRSUBR MULRD1VR
supervisor call, SVC
1 3 2 SIC/XE1.3.2 SIC/XE
SICI/OSIC/XE CPUI/O CPU I/OI/O channels
SIOTIOHIOI/OSIO TIOHIO I/O
(I t ti S t) (1)(Instruction Set) (1)
(18) ADD m A
(I t ti S t) (2)(Instruction Set) (2)
(40) AND m A
(I t ti S t) (3)(Instruction Set) (3)
(00) LDA (00) LDA m A
(I t ti S t) (4)(Instruction Set) (4)
(E0) TD m device device
(D8) RD m device
(DC) WD m device
(I t ti S t) (5)(Instruction Set) (5)
(3C) J m (30) JEQ m (30) JEQ m (48) JSUB m
(4C) RSUB
(I t ti S t) (6)(Instruction Set) (6)
(2C) TIX m X
SIC SIC TD TD ,
CC, < , =
, RD () WD () ) WD ()
SIC SIC
WORD () RESW ( RESW (
) BYTE, RESB , BYTE, RESB ,
1 3 3 SIC1.3.3 SIC
SIC SIC (1 2a) C (1.2a) C
i t ALPHA 5int ALPHA = 5;char C1 = Z;
1 3 3 SIC1.3.3 SIC
SIC SIC ADD SUB MUL DIV ADD, SUB, MUL, DIV
ADD A SUB A SUB A MUL A DIV A DIV A
1 3 3 SIC1.3.3 SIC
SIC SIC (1 3a) C (1.3a) C
i t ONE ALPHA BETA GAMMAint ONE, ALPHA, BETA, GAMMA,DELTA, INCR;
BETA = ALPHA + INCR ONE;DELTA = GAMMA + INCR ONE;
SIC (1 4a)SIC (1.4a)LDX ZEROLDX ZERO
MOVECH LDCH STR1,XSTCH STR2,X,TIX ELEVENJLT MOVECH
STR1 BYTE CTEST STRINGSTR2 RESB 11ZERO WORD 0ELEVEN WORD 11
SIC (1 4a) C (1.4a) C
char *STR1 TEST STRING;char *STR1 = TEST STRING;char STR2[11];strcpy(STR2, STR1);
SIC SIC
COMP A , () CC () CC
CC,CC (JLT JEQ JGT) (JLT, JEQ, JGT)
ACOMP SW
COMP SW CC:
JLT, JEQ, JGT
SIC SIC SIC : SIC , , :
LDA ALPHA LDA ALPHA ;LABEL1 LDA ALPHA ;
1 3 3 SIC1.3.3 SIC
1 3 3 SIC1.3.3 SIC
1 3 3 SIC1.3.3 SIC
SIC SIC JSUB JSUB ,
L; RSUBL
1 3 3 SIC1.3.3 SIC
1 3 3 SIC1.3.3 SIC
1 4 CISC1.4 CISC Complex Instruction Set Computers(CISC) Complex Instruction Set Computers(CISC)
VAX Intel x86 Intel x86
1 4 1 VAX1.4.1 VAX
word wordlongwordquadword quadwordoctaword
VAX2^32VAX2 32virtual address space
1 4 1 VAX1.4.1 VAX
VAX16general-purpose registersR0R15registers R0R15
32R15R15 R14stack pointer, SPR13frame pointer, FP p ,R12argument pointer, APR6R11: R0R5:/
1 4 1 VAX1.4.1 VAX
8ASCII 8ASCII floating-point416416
packed decimal queuesvariable-q
length bit strings
1 4 1 VAX1.4.1 VAX
operand specifiersp
1 4 1 VAX1.4.1 VAX
::index
registerg
1 4 1 VAX1.4.1 VAX
prefix suffix suffix modifier
1 4 1 VAX1.4.1 VAX
I/Odevice controller
/physical address space p y p I/OI/O space
1 4 2 P ti P 1.4.2 Pentium Pro
double-wordd ddword
x86segmentssegments offset
1 4 1 VAX1.4.1 VAX
:EAXEBXECXEDXESIEDIEBPESP(32)EDI EBP ESP (32)
EAXEBXECXEDXFLAGS32FLAGS 32
segment registersg gCS
SSSSDSESFSGS
1 4 1 VAX1.4.1 VAX
x86
FPU64 x86x86 single-precision32 double-precision64 extended-precision80
1 4 1 VAX1.4.1 VAX
x86 prefixprefix opcode
1 4 1 VAX1.4.1 VAX
TA =+*+
1 4 1 VAX1.4.1 VAX
1 4 1 VAX1.4.1 VAX
I/OEAXEAX
EAXI/O
1 5 RISC1.5 RISC Reduced Instruction Set Computers Reduced Instruction Set Computers
i l l single-cycle
1 5 1 Ult SPARC1.5.1 UltraSPARC
halfword halfword
UltraSPARC264
1 5 1 Ult SPARC1.5.1 UltraSPARC
register file 100 100 32r0r31r31 r0r7global
1 5 1 Ult SPARC1.5.1 UltraSPARC
8163264 8163264 single-precision32single precision32 double-precision64 quad-precision63 1515
1 5 1 Ult SPARC1.5.1 UltraSPARC
32 1call 1call 2branch 3 3
1 5 1 Ult SPARC1.5.1 UltraSPARC
1 5 1 Ult SPARC1.5.1 UltraSPARC
100
pipelined pipelined
1 5 1 Ult SPARC1.5.1 UltraSPARC
I/O
I/O I/O
1 5 2 P PC 1.5.2 PowerPC
PowerPC264PowerPC2
1 5 2 P PC 1.5.2 PowerPC
PowerPC32GPR0GPR31GPR31
64
326432Link Register, LRCount Register, CR
1 5 2 P PC 1.5.2 PowerPC
81632648163264
single-precision32double-precision64
ASCII
1 5 2 P PC 1.5.2 PowerPC
PowerPCsubformssubforms
32
extended opcode
1 5 2 P PC 1.5.2 PowerPC
1 5 2 P PC 1.5.2 PowerPC
200 pipeline pipeline branch prediction
1 5 2 P PC 1.5.2 PowerPC
virtual address spacesegmentssegments
1 5 3 C T3E1.5.3 Cray T3E
1 5 3 C T3E1.5.3 Cray T3E
64M2G64M2G
system memoryPE
1 5 3 C T3E1.5.3 Cray T3E
Alpha32R0R31R310R310
64 32F0F31F3132 F0F31 F31064
64
1 5 3 C T3E1.5.3 Cray T3E
1 5 3 C T3E1.5.3 Cray T3E
32 32
function function field
1 5 3 C T3E1.5.3 Cray T3E
1 5 3 C T3E1.5.3 Cray T3E
130
shift-and-maskand mask
1 5 3 C T3E1.5.3 Cray T3E
I/OI/O channelsI/O
I/Oprocessing nodes p g
I/OPE draPE
SIC SIC, , SIC/XE, ,
CISC / RISC
SIC () () SIC, SIC/XE, CISC / RISC