Introduction

System-on-Chip

Pietro AndreaniDept. of Electrical and Information Technology

Lund University, Sweden

Overview

• Modern MOS processes• High-k + metal gate 45nm CMOS process from Intel

• Moore’s law

• Interconnects

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• International Technology Semiconductor Roadmap (ITRS)• more Moore and more than Moore

• Packaging

The march of materials

(potential)

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• CMOS is not simple any more• CMOS is not cheap any more (but, maybe/hopefully, cheaper?)

MOS with polysilicon gate

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• Depleted region in polysilicon gate decreased “on” current, increased “off” current

• SiO2 dielectric cannot be too thin, otherwise tunneling current through the gate becomes unacceptably large

This and most following slides from Intel documents

MOS with polysilicon gate - problems

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• SiON scaling running out of atoms!• Dielectric cannot be too thin, otherwise tunneling current through the gate

becomes unacceptably large

• Polysilicon depletion limits inversion

New HK+MG MOS device

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Advantages of HK+MG

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Polysilicon removed after annealing

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• A problem with metal gates is that they would melt during annealing (however, there is intense research to avoid the so-called “gate last” process)

Some process details

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• Hafnium-based high-k dielectric, dual-metal gate, strained silicon• High-k first, metal-gate last (metal gate deposition after high-T anneals)• Strained silicon process; transistor mask count same as 65nm• Gate leakage reduce 1000x for PMOS, 25x for NMOS

Strained silicon

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• Photos from 65nm CMOS • Strained silicon improves mobility of charge carriers

Device photo (45nm CMOS)

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• 35nm minimum gate length• 160nm contacted gate pitch• 20% Ge in SiGe

Comparison

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At an earlier stage (HK dielectric)

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From G. Moore, ISSCC ‘02

Device scaling – keeping Moore’s law alive and well

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• Contacted gate pitch of 160nm 0.7x scaling continues

Moore’s law – transistors per die

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From G. Moore, ISSCC ‘02

Minimum insulator thickness

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From G. Moore, ISSCC ‘02

Transistors shipped per year

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From G. Moore, ISSCC ‘02

Average transistor price by year

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From G. Moore, ISSCC ‘02

MIPS by computer generation

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From G. Moore, ISSCC ‘02

SRAM

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• SRAM density doubles every two years

Next Intel generations

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Interconnects

• Low-k ILD (organic inter-level dielectrics)

• CDO = carbon doped oxide

• Reduces capacitance

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• Reduces capacitance reduces delay increases speed

• M1-M3 pitches match MOS pitch

Metal 9 + PAD (no lead any more)

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• M9: ReDistribution layer (RDL) 7μm!!• Polymer ILD• Improved on-chip power distribution

Signal delay / integrity

• 10km of wiring crammed into a space smaller than a postage stamp• Signal lag not caused by transistors (they are very fast

nowadays) but to RC time constant in wirings, where C is the inter-wire capacitances

• This capacitance causes extra lag and possibly signal corruption• Better insulation between wires carbon-doped silicon dioxide

good, but nothing can beat vacuum!

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• Natural glass: k=4.2; fluorinated SiO2: k≈3.5; highly carbonated SiO2: k≈2.7; vacuum: k=1(minimum possible)

• Problem with vacuum: does not provide structural support; hardly compatible with standard chip production steps

• IMB makes use of a self-assembling two-dimensional copolymer, forming a mesh of 20nm cylindrical holes

• IBM: k≈1.9 10-15% improvement of RC time constant• Structural integrity is still an important issue

The ultimate inter-wire dielectric – nothing

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• IBM’s air-gap technology nanoscale holes into the insulation between copper wires in production in 2009

Functions per chip – Moore’s law

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International Technology Roadmap for Semiconductors, ITRS

Moore’s law (from 1970)

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Size reduction

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More Moore and more than Moore

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More Moore and more than Moore – II

• Scaling (more Moore)1. Geometrical scaling continued shrinking of horizontal/vertical

feature size2. Equivalent scaling new devices and/or new materials

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• Functional diversification (more than Moore)1. New devices/functionalities not necessarily scaling with Moore

provide added value to end customer2. Typically, non-digital functions such as RF communications, power

control, passive components, sensors, actuators, etc3. Migrate from board level to SiP or even SoC level

Future: tri-gate FET / FinFET?

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Packaging

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From ITRS

PoPs and PiPs

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Examples of stacked-die packages

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Wafer-level SiP with inter-chip vias

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