System Generator DSP1

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DSP-A Practical Approach

2

Agenda

Need for DSPTraditional DSP alternativesExample of FIR filterSERENDIP ProjectDesign FlowIntroduction to System GeneratorInstallation of System GeneratorDesign Example Using System GeneratorPhysical VerificationSummary

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Need For DSP?

DSP is every Where - Communications, Entertainment, Controls, Defense, Space … etc, you name it.

Need for DSP techniques arises from the requirement of extracting maximum information from the input signals and manipulating them.

The systems are incorporated with lot of intelligence for givingthe best possible results and performance.

Now a days DSP systems are Characterized by theirHigh Speeds of Operation. Data IntensivenessComplexityand these – 3 make extracting the parallelism in algorithms a very important part of system design.

4

The DSP Design Challenges

Increasing performanceAlgorithms are becoming more data intensive with increase in sampling speeds and data rates of the systems. Latency of traditional systems is large, hence making them slow and incompatible for real time application.

Increasing ComplexityWe have more and more data to process, and another challenge is to extract as much information as we can from output. Both these factors makes designs more and more complex.

Input OutputDSP Algorithmsn n

Latency

Less time for product developmentAnd last but not the least, the time to market is the main driving force for getting an edge over competitors and getting the most of the product during its rising market.

5

A DSP System

DSPInput 1..01 0..10

ADC DAC

DSP µP ASICsDiscrete

Logic

Antialiasingfilter

Reconstruction Filter

Output

FPGA

6

DSP APPLICATIONS

DSP

SPACE

MEDICAL

COMMERCIAL

TELEPHONE

MILITARY

INDUSTRIAL

SCIENTIFIC

MEDICAL

COMMERCIAL

Space Photograph EnhancementData compression

Echo ReductionVoice and Data compression

Radar and SonarOrdinance Guidance

Oil and Mineral ProspectingProcess Monitoring and control

Earthquake Recording AnalysisSpectral Analysis

Diagnostic ImagingElectrocardiogram Analysis

Video Conference CallingMovie Special Effect

7

Traditional DSP Alternatives

DSP Processors

Asics

PC based Implementation

8

DSP Processors

DisadvantagesRelatively low performance

Are limited in functionality by the instruction set so may require multiple machine cycles for executing a task.

Requires additional componentsCan’t work as stand alone systems require additional components to run the complete system.

AdvantagesQuick turnaround

Software can be easily changed and functionality modified.Reconfigure

Same hardware resources can be Reused for different designs

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ASICs

AdvantagesHigh-performance

Speed can be easily achieved using customized fabrication.One-chip solutions

Complete systems can be built on a single chip, making it a stand alone system.

DisadvantagesLong turnaround

Any change in the design requires altering the complete layout of the chip

Cannot be changed afterwardsNo up-gradations possible in same chip.

Expensive NRELot of money and time has to be spent in designing the chip.

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AdvantagesMore familiar coding tools( BASIC,C,C++ etc.)Mathematical expression can easily be implemented .

DisadvantagesTime consuming and difficult to Debug.Real time analysis is difficult using C,C++ etc.

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AdvantagesMore familiar coding tools( BASIC,C,C++ etc.)Mathematical expression can easily be implemented .

DisadvantagesTime consuming and difficult to Debug.Real time analysis is difficult using C,C++ etc.

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PC based Implementation (Matlab)

AdvantagesSimulation tools such as Matlab can are best suited to simulate and verify any DSP Algorithm.Easy to debug and implement (Graphical user interface)Takes less time in comparison to programming languages such as C,C++etc.

DisadvantagesReal time analysis is difficult.

We will see later that how this only disadvantage of Matlab wasovercome by interfacing it with EDA tools like System Generator

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Advantages of FPGA’s

FPGA offers combined advantages of DSP processors & ASICs.

Advantages:

Quick turnaround

Reconfigurable

High-performance

One-chip solutions

Real time analysis is easy.

No Disadvantages

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Y(n)= k=0ΣM-1h(k)x(n-k)

Example of FIR Filter

An FIR filter can be implemented by using the convolution Equation

Z-1Z-1 Z-1

x x x x

+

h(0) h(1) h(2) h(3)

X(3) X(0)X(1)X(2)

Y(n)

For n = 3 the convolution equation expands to:-Y(3)=h(0)x(3)+h(1)x(2)+h(2)x(1)+h(3)x(0)

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Example Of FIR Filter

Delay elements functionality is to introduce delay of one samplebetween the coefficients.Digitally it is represented by a register.

Multiplier blocks are used for multiplication of coefficients and data.

Adder blocks are used for accumulating the results obtained by multiplication of coefficients and data.

Z-1

+

x

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Example Of FIR Filter

All transforms in DSP have constants to be multiplied with inputThis operation is what is called as a MAC (Multiply and Accumulate) in DSP terms.For example here the filter is implemented by convolution. The operation of convolution can be replaced by a hardware MAC.The hardware required by a MAC is a multiplier and an accumulator (adder).

Multiply & Accumulate.(MAC)

Delay ElementZ-1

x x

+

Adder

Multiplier

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Traditional FIR Performance

Microprocessors have fixed hardware architectural resources.Traditionally have one Multiplier

Latency for this architecture is

n*(Time taken for one cycle)+

time taken for storing results after each cycle (Housekeeping ).

So for implementing data intensive operations like convolution, lack of the hardware resources on the microprocessor reduces the overall system speed

* mac - Multiply and Accumulate

Fixed hardware resources,have to be

used sequentially.rep n

mac*

n Tap FIR Filter

Loop Algorithmn times

Register

Register

Output

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FPGA based FIR Performance

Z-1Z-1 Z-1

x x x x

+

h(0) h(1) h(2) h(3)

X(3) X(0)X(1)X(2)

Y(n)

What is the time required for this operation?

Just one clock cycle!

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Where is the difference?

Von Neumann architectureThis architecture was among the first architecture used for

microprocessor. This architecture have single bus for data as well as instruction hence it takes large number of cycles to implement DSP applications. Harvard architecture based DSP Processor

The basic idea behind this architecture to use separate buses to fetch data as well as instruction simultaneously. In this architecture one MAC takes one cycle.n MAC operation takes n cycles to execute.FPGA architecture

The architecture of FPGA is a parallel architecture which allows to perform n MAC operations in a Single cycle. Hence FPGAs can be n times faster then the Harvard architecture based DSP processors.

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Virtex-II

SwitchMatrix

SwitchMatrix

CLB,IOB,DCM

CLB,IOB,DCM

Active Interconnect ™

Fully bufferedFast, predictable

18b x 18b multiplier200+ MHz pipelined

Multipliers

BRAM

18KBit True Dual PortUp to 3 Mbits / device

Block RAM

SwitchMatrix

Slice S0

Slice S1

Slice S2

Slice S3

Powerful CLB

8 LUTs128b distributed RAMWide input functions (32:1)Support for slices basedmultipliers

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Virtex-II

XCITE™

On-chip terminationGuaranteed signal integrityEliminates 100s of resistors

Zero delay clockPrecision phase shiftFrequency synthesisDuty cycle correctionClock multiply and divide

DCM

16 Global Clocks8 clocks to any quadrantSwitch glitch-free between clocks

16 Clocks

22

Virtex-II Memory Hierarchy

QDR SRAM

16x116x1

16x116x1

16x116x1

16x116x1

Distributed RAM

True-Dual Port™Synchronous Block RAM

16k x 18k x 24k x 42k x 91k x 18

512 x 36

High-PerformanceExternal Memory Interfaces

DDR SDRAM

ZBT®SRAM

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CIN

SwitchMatrix

TBUFTBUF

COUTCOUT

Slice S0

Slice S1

Fast Connects

Slice S2

Slice S3

CIN

SHIFT

Virtex-II CLB

Flexible resourcesWide-input functions

16:1 multiplexer in 1 CLBFast arithmetic functions

2 dedicated carry chains Cascadable shift registers in LUT

128-b shift register in 1 CLB Ease of Performance

Direct routing enabling high speed

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Virtex-II Slice

Each slice contains two:4 inputs lookup tables16-bit distributed SelectRAM16-bit shift register

Each register:D flip-flopLatch

Dedicated logic:MuxesArithmetic logicMult-ANDLUT

Register

Register

LUT CY

CY

SRL16

RAM16

G

F

MUXF5

Arithmetic Logic

MUXFx

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LUTs used as memory inside the fabricFlexible, can be used as RAM, ROM, or shift register

Distributed memory with fast access time

Cascadable with built-in CLB routingApplications

– Linear feedback shift register– Distributed arithmetic– Time-shared registers– Small FIFO– Digital delay lines (Z-1)

Unique Distributed RAM

LUT

SRL16

RAM1616b

128b

1 CLB

Single PortRAM

64b64b

1 CLB

Dual PortRAM

16b

Shift register

1 CLB

128b

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Multiplier Unit

Embedded 18-bit x 18-bit multiplierQuantity:

XC2V1000 : 40XC2V3000 : 96XC2V8000 : 168

2s complement signed operation4- to 18-bit operandsCombinational & pipelined options

18 x 18 < 7 ns8 x 8 < 5 ns

Operates with block RAM and fabric to implement MAC function

FIR & IIR digital filters

18 Bit

18 Bit

36 Bit

8 x 8 210MHz4 x 4 255MHz

12 x 12 170MHz18 x 18 140MHz

Signed Multiply Performance

Preliminary V1.60 Speeds File

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What is common in these algorithms?

FFT

Walsh transform

Discrete Cosine Transform

Convolution

Y(n) =n=0Σ N-1 x(n) WNkn

Xk = 1/N i=0ΣN-1 xi WAL(k,i)

Xc(k )= n=0ΣN-1 xn Cos(2KΠn/N)

Y(n) = k=0ΣN-1h(k)x(n-k)

Think Implementation!All these transforms use MAC as there Basic building block

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How to implement DSP in FPGA?

Till now we have discussed pros and cons of different implementation of DSP algorithms .We have concluded that FPGA architecture is best suited for implementing DSP AlgorithmsNext question which comes in mind is :-How to implement DSP algorithms on FPGA while taking care of all DSP design challenges?

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Different Implementation Techniques on FPGA

EDA tools can be used to implement DSP algorithms. Most of these tools require sound knowledge ofVHDL/ Verilog.

Another approach is to use Embedded Tools. These tools require a deep knowledge of C and tool itself.

Simplest approach to handle this problem is to use SYSTEM GENERATOR (MATLAB).

Best part of using this tool is that you don’t need to have deep knowledge of any hardware or software programming language and design complexity .

30

Algorithms verification and implementation Design Flow

Designing a application / system requires thatFirst the algorithms be verified, and then Implemented in system.

Algorithms can be easily verified by using tools like - MATLAB

Implementation can be handled by Using tools like XILINX ISE / Alliance for synthesing the system on an FPGA.

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Algorithms verification and implementation Design Flow

System DesignDomain FPGA Design

Domain

GAP

Manual design entry in HDL

Hardware simulation

Synthesis, place and route

Timing verification

Foundation/Alliance

Algorithm design

System verification (floating point)

Optimization and re-verification

Conversion tofixed point

MATLAB and Simulink

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Linking The System And FPGA Design Domains

System DesignDomain

FPGA DesignDomain

Algorithm design

System verification (floating point)

Optimization and re-verification

Conversion tofixed point

Automaticgeneration of HDL

Hardware simulation

Synthesis, place and route

Timing verification

MATLAB and Simulink Foundation/Alliance

Xilinx System Generator & LogiCOREs

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Introduction to System Generator for DSP

System Generator for DSP is a software tool for modeling and designing FPGA-based signal processing systems in Simulink.

The tool presents a high level abstract view of a DSP system, yet nevertheless automatically maps the system to a faithful hardware implementation.

What is most significant is that System Generator provides these services without substantially compromising either the quality of the abstract view or the performance of the hardware implementation

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Introduction to System Generator for DSP

Simulink provides a powerful high level modeling environment for DSP systems, and consequently is widely used for algorithmdevelopment and verification.

The implementation is made efficient through the instantiation of intellectual property (IP) blocks that provide a range of functionality from arithmetic operations to complex DSP functions.

User-defined IP blocks can be incorporated into a System Generator model as black boxes which will be embedded by the tool into the HDL implementation of the design.

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Sys Gen Installation

1) Unzip a System Generator Software file in work foldere.g. C:\matlab\work

2) Open Command Window in Matlab

Type setup and press Enter Key

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Sys Gen Installation

Now installation of System Generator will be StartedAfter installation of Sys Gen restart matlab.

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Design Example of Filter

Low Pass FIR Filter Specifications:

1) 11 Tap Filter2) Sampling Frequency (Fs) = 31250 Hz.3) Pass Band Frequency (Fpass) = 2000 Hz4) Stop Band Frequency (Fstop) = 5000 Hz5) Pass Band Gain (Apass) = 1 dB6) Stop Band Gain (Astop) = 80 dB

38

FIR Filter Design

Generate the coefficient from FDATool (Filter Design and Analysis)Type FDATool in matlab command window.

39

Filter Design

Sampling Frequency

Pass Freq.

Stop Freq.

40

Filter Design

Goto File -> Export to export the coefficient for FIR filter

Coeff. Are generated &

stored in Num file.

41

Filter Design

We can select full view analysis icon to analyze Filter responses as per your input specifications.-Magnitude response .-Phase response.-Magnitude and phase response .-Group delay response .-Impulse response-Step response .-Pole /zero plot.-Filter coefficient .-Noise loading method.-Turn quantization on.

42

Filter analysis

Filter specification.

43

Filter analysis

Magnitude response

44

Filter analysis

Phase response

45

Filter analysis

Magnitude and phase response

46

Filter analysis

Impulse response.

47

Filter analysis

Step response.

48

Filter analysis

Pole/zero plot.

49

Filter analysis

Filter coefficient .

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Filter analysis

Noise loading method .

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Simulink

Close FDA tool Open MATLAB editor .

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Simulink

You can open SIMULINK using launch pad

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Simulink

Otherwise type simulink on matlab command window to enter into the simulink environment.

54

Creating a System Generator Design

Open Xilinx Block-set listed in Simulink Library Browser

Create Design by Dragging and Dropping components from the Xilinx Block-set onto your new sheet to create design

55

Finding Blocks

Use the Find feature to search through ALL Simulink librariesXilinx blockset has seven major sections

Basic elementsCounters, delays

CommunicationError correction blocks

DSPFilters, FFT

MathMultiply, add, compare

MATLAB IODouble to fixed pt conversion

MemoryState machines

56

Scope

Drag scope icon into a modal to insert a scope block from sink.

57

Signal generator

Double click on source .Insert signal generator to give input signal to filter .

58

System generator

Interfacing to the xilinx system generator to generate HDL code for the sub system hierarchy in which the block resides.

59

Gateway in and gatway out block

Gateway in block is used to convert double to xilinx fixed point.Gateway out block is used to convert xilinx fixpoint inputs into outputs of the type double.

60

Creating a system generator design

Below a Block Diagram of FIR filter is shown

Simulinksources

IO blocks used as interface between the Xilinx blockset and other Simulink blocks

Simulink sinks & library functionsSysGen blocks realizable in Hardware

61

Configure signal generator block

Double click on Signal Generator block to set its parameter

Write amplitude of input signal

Ratio of inputFreq and Sampling freq

Select type of wave form

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Configure Gateway in block

Double click on Gateway In Block to set its parameter

• Indicate i/pdata width

• Choose type of

overflow

?

• Choose O/p data type

• Choose type ofQuantization

Select fraction digit

63

Simulink uses a “double” to represent numbers in a simulation.

Xilinx blockset uses n-bit fixed point number (2s comp optional)

The Numbers Game

1-22

021

120

12-1

02-2

12-3

12-4

12-5

12-6

02-7

12-8

02-9

02-10

12-11

02-12

12-13

Integer Fraction

• A conversion is required when communicating Xilinx blocks with Simulink blocks (Xilinx blockset -> MATLAB I/O -> Gateway In/Out)

Value = -2.261108…

Format = Fix_16_13

(Sign: Fix = Signed Value UFix = Unsigned value) Format = Sign_Width_Decimal point from the LSB

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What About All Those Other Bits?

. . . .

DOUBLE

1-22

021

120

12-1

02-2

12-3

12-4

12-5

12-6

02-7

12-8

02-9

FIX_12_9

122

021

120

12-1

02-2

12-3

12-4

12-5

12-6

02-7

12-8

02-9

02-10

12-11

02-12

12-13

1 1 1 1 . . . .232425-26

QUANTIZATIONOVERFLOW

- Truncate- Round

- Wrap- Saturate- Flag Error

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Important Concept Sample Period

Every SysGen signal must be ‘sampled’, i.e., transitions occur at equidistant discrete points in time called sample timesEach block in a Simulink design has a “Sample Period” and it corresponds to how often that block’s function is calculated and the results outputted This sample period must be set explicitly for:

Gateway inBlocks w/o inputs (note: constants are idiosyncratic)

Sample period can be “derived” from input sample times for other blocks

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Important Concept Sample Period

The units of the sample period can be thought of as arbitrary, BUT a lot of Simulink source blocks do have an essence time

E.g., sample period of 1/44100 means the block’s function will be executed every 1/44100 of a sec

Remember Nyquist Theorem (Fs ≥ 2fmax) when setting sample periods

The sample period of a block DIRECTLY relates to how that block will be clocked in the actual hardware. More on this go to help type gateway in

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Features Of Simulink XILINX Blocksets

• Coefficients generated from FDA tool.

• Latency is required since FIR is a synthesizable xilinx block.

• Easy generation of cores.

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Simulation

To simulate the block click on Simulation icon.Select simulation time (i.e 1000).Click on start simulation.Double click on scopes.

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Using the Scope

Click properties to change the number of axis displayed and the time range value (X-axis)

Use Data history to control how many values are stored and displayed on the scope

Click autoscale to quickly let the tools configure the display to the correct axis values

Right click on the Y-axis to set its value

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FIR Filter

ReadymadeXilinx

Blocksets for standard

functionalities.

71

Easy System Synthesis

Hassle free Implementation of the system on Xilinx FPGA’susing SYSTEM GENERATOR

Design core will be saves in

this location

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Automatic file creation by systengenerator

When a System Generator project is created, the software produces design VHDL and cores from the Xilinx CORE Generator. In addition, many other project files are created. Following is a description of the files you can expect to find in your System Generator generated project directory. For this example, we will assume your top-level project name is fir_filter , and that this project contains one multiplier core.

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Easy Code Generation

Automatic generation of synthesizable VHDL code for the systemlibrary IEEE;use IEEE.std_logic_1164.all;use work.conv_pkg.all;entity filter is port (I_Channel_in : in std_logic_vector (7 downto 0);I_Channel_valid : in std_logic;Phase_Out : out std_logic_vector (18 downto 0);Phase_Out_valid : out std_logic;Phase_Out1 : out std_logic_vector (7 downto 0);Phase_Out1_valid : out std_logic;clk : in std_logic;clr : in std_logic

);

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Files automatically created by system generator

Fir_filter.vhd - the top level VHDL file for your project. There are additional VHDL files included when your design has more hierarchy. Fir_filter_xlmult_core1 - files associated with the generated multiplier core, such as the behavioral simulation models and EDIF file.corework - subdirectory containing the CORE Generator log file.Fir_filter.xcf - generated constraints file when XST synthesis is

chosen in the System Generator block. Buses in this file are denoted with angle brackets. Fir_filter.ncf - generated constraints file when Synplify or Leonardo Spectrum is chosen as the synthesis tool. Buses are denoted with parentheses.

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Fir_filter.npl - project file for opening the design in Xilinx ISE 6.2i Project Navigator, using your chosen synthesis compiler and ModelSim simulator.Fir_filter_testbench.vhd - the top level VHDL testbench file,

associated with the top level VHDL source file in the projectFir_filter_<gateways>.dat - stimulus files for inputs to testbenches, or predicted outputs of testbenches. The .dat files are generated by Simulink simulation and saved for running in Xilinx testbenches to verify design behavior. In this example, <gateways> refers to the names of the Xilinx gateway blocks, which collect and save the data.

VhdlFiles - a list of VHDL files, and their dependency order, needed for synthesis projects. System Generator's Perl scripts read from this file when creating project files.

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Globals - a file containing the characteristics of the design needed by downstream software tools in order to synthesize and implement.Synplify_fir_filtert.prj - a project file for running this design in

Synplify (synthesis tools from Synplicity) if you have chosen it as your synthesis tool in the System Generator block. XST_fir_filtert.prj - a project file for running this design in XST if you have chosen it as your synthesis tool in the System Generator block.Spectrum_fir_filtert.tcl - a project file for running this design in

Leonardo Spectrum (synthesis tools from Mentor Graphics).

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Pn_behavioral.do, pn_posttranslate.do, pn_postmap.do, Pn_postpar.do - compilation and simulation do files for running this design through simulation at different stages. These 4 files are associated with ModelSim simulation through the Xilinx ISE 6.2i Project Navigator. Vcom.do, vsim.do - default behavioral simulation files for use with ModelSim.Sysgen.log - log file. xlRunScripts.log - logfileshowing status of post-processing scripts run by System Generator.

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Xilinx foundation design flow

Open xilinx project navigator.Double click on the fir_filter.npl

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All files are in project window .Insert coreWrite click on

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Select core from corework folder(.xco )

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Add your top level entity with .ucf file.Instantiate top level entity fir_filter.vhd file of filter in your design top level entity.

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Right click on synthesis option in project navigator window . Run synthesis

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Launch model sim simulator to run simulation.

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Run implementation design.

85


Run iMPACT .Configure the device using .bit file that is saved in project folder

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Physical Verification

Convenient downloading in the XILINX Spartan III FPGA, easily accessible on Mechatronics DSP kit with on board ADC-DAC,for real time verification of the design.

FUNCTION GENERATOR

8 CHANNEL ADC-500KSPS

STEREO JACK

4 DACs

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Summary

Now we are able to answer following questions.(1)What is the System Generator .(2)How to use install System Generator(3)How it can help us in design solutions of various domains .(4)How to use different blocks of System Generator .(5)How to simulate a design in Matlab environment .(6)How System Generator will export design core in VHDL .(7)How to instantiate System Generator design into existing

design in Xilinx ISE software.(8) Xilinx ISE design flow .(9)Physical verification.

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Summary

Need for data intensive DSP based systems in modern day applications.

SYSTEM GENERATOR is a seamless interface between the DSP System Designer and the FPGA Architecture expert.

Our Skill setDevelopment of customized DSP IP cores for all PLD vendors.Ability to develop propriety cores and algorithms easily using the System Generator / MATLAB Environment.Provide a platform for Physical Verification of DSP Algorithms and systems.

www.bitmapper.com

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THANK YOU

Documents

System Generator DSP1