Survey of HDL Compiler Optimization Techniques

M.Josepha ∗, Narasimha B.Bhatb and K.Chandra Sekarana

aDepartment of Computer Engineering, National Institute of Technology,Srinivas Nagar (Post), Mangalore, Karnataka, India - 575025.

bManipal Dot Net P. Ltd, 37. Ananth Nagar,Manipal, Karnataka, India - 576104,

This paper presents a detailed survey of Hardware Description Language (HDL) compiler optimization tech-niques available in the research literature. Applicability of High Level Language compiler optimization techniquesto Hardware Description Language compilers is exhaustively presented.

1. INTRODUCTION

The optimal design of hardware with lowpower, faster performance and less chip area is theprime requirement for the digital systems. Due tolow power requirements in many portable applica-tions such as mobile phones, as well as packagingcost consideration, low power design is imperative[16]. Low power implies better cooling (avoidinghigh system cost of fans), portability (extendedbattery life), reliability (reduced electron migra-tion), lower cost (power is expensive) and friendlyenvironment (power has negative impact). Tech-nical feasibility of high performance computationis due to heat extraction and is determined bytotal number of control steps (clock cycles) a sys-tem takes, which is the clock period of the slow-est logic stage in the system. Minimization ofchip area reduces the amount of silicon used andalso increases yield since the causes of failure likecrystal defects, defects in the masks, defects dueto contact with dust particles, etc are less likely toaffect a chip when area is smaller. The use of anHardware Description Language (HDL) based de-sign flow therefore becomes a defacto standard forany digital system designer, and an understand-ing of optimization techniques at the HDL levelof abstraction helps write better design descrip-tions, eventually leading to higher performance,lower area and lower power designs.

∗This work is funded by MHRD, Government of India.

1.1. HDL compiler

The HDL Compiler takes the code in a HDLand converts into RTL structures. The frontend consists of scanner, parser and intermedi-ate code generator and the usual functions areperformed by these. But the intermediate repre-sentation is Control/Data Flow Graph (CDFG),which is a variant of the syntax tree represen-tation along with the control information. Theback end consists of the optimizer and hardwaregeneration circuits. The optimizer applies com-piler optimization techniques on CDFG to im-prove it. Then hardware generation functions areapplied on the optimized CDFG to generate RTLstructure, which are are scheduling, and alloca-tion. Scheduling assigns operations to the controlsteps and allocation assigns operations to func-tional units like ALU, multiplexer and storage el-ements. The HDL compilation process is pop-ularly called as High Level Synthesis (HLS) [6],[13], [21]. Popularly used HDLs are VHDL, Ver-ilog, and SystemC, which are used to describe thehardware system.

1.2. HDL compiler optimization

In the classical sense, code optimization refersto the process of modifying the working code intomore optimal code based on a particular goal.The goal may be reducing execution time or re-ducing memory space. But in case of HDL com-pilers, code optimization has a different perspec-

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International Journal of Information ProcessingVol. 1, No. 1, March/April 2007, Pages(51-62)

Survey of HDL Compiler Optimization Techniques 61

criterion to be optimized. The influence of perfor-mance optimization techniques on system energyhave been studied by Kandemir et al [14]. Theinferences are 1. Memory consumes more energythan the un-optimized codes, 2. Though Perfor-mance optimizations reduce the power consump-tion, they increase the data path energy consump-tion, 3. Increase in cache size leads to increase indata cache energy, but it reduces the energy byminimizing the number of accesses to main mem-ory.2. TestabilityThe chips fabricated have to be tested before be-ing used in a product. It is important that a chipshould be easily testable as testing equipment isexpensive. This necessitates the minimization ofthe time spent to test a single chip. If the chiparea is more, testability is improved [18]. So opti-mization of area may have negative effect on thetestability.

5. OPEN ISSUES

1. Semantic gapThe hardware description languages adhere toa simple, sequential programming style, whichmimics the HLL programming model. They arenot capable of expressing the synchronous, con-current processing nature of the hardware cir-cuits. This gap between the HDLs and hardwarecircuitry is called semantic gap. This problemleads to sub optimal design of digital systems [5].2. Order of optimizationThe order in which the optimization techniquesto be applied is not clear because application ofone optimization will open avenues for other opti-mizations. E.g: constant propagation gives scopefor constant folding [8]. Some optimizations areinteractive, so the user has to decide the orderin which order optimizations to be applied andshould be aware of the details [18]. The orderfor applying the optimization techniques for HLLcompilers is discussed by Steven S. Muchnick [19]and the applicability of that order can be studied.3. Design timeA chip satisfying the specifications should be de-signed and made available as soon as possible. Agood CAD tool should help to reduce the runtime

(design time) considerably [18]. This is actually adifferent issue; however it has implication in theoptimization issues.

6. CONCLUSION

This paper presents HDL compiler optimiza-tion techniques comprehensively and also someopen issues. It does not address the implementa-tion issues of these techniques. Influence of opti-mization techniques on a system power perspec-tive is only done and addressed in the paper andinfluence on other parameters can be further ex-tended. VLSI design as a whole can be thought asan optimization problem but this paper presentsonly compiler transformations not the other is-sues like gap between the CAD tools and tar-get technologies, which is a major cause for sub-optimal hardware generation.

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