Temple University

Summer Research Progress:

Week 2 – DSP vs FPGA

Ross Keyes, Ajo MaretDepartment of Electrical and Computer Engineering

Temple University

URL:

Temple University: Slide 2

FPGA Specifications

Spartan - 3A Family:

• Very low cost, high-performance logic solution for high-volume consumer-oriented applications.

• Up to 519 I/O pins. 622+ Mb/s data transfer rate per I/O.

• DDR/DDR2 SDRAM support up to 400 Mb/s

• Programmable input delays for finer timing control.

• Up to 373 Kbits of efficient distributed RAM

• IEEE1149.1/1532JTAG programming/debug port

• Wide frequency range (5 MHz to over 300 MHz)

• Complete Xilinx ISE and WebPACK development system support

•Fully compliant 32-/64-bit 66 MHz PCI support

Temple University: Slide 3

Design Flow (FPGA)

Binary Data

MATLAB

Simulink & SysGen FPGA

Binary Data

MATLAB

Simulink & SysGen

Hardware in the loop

Temple University: Slide 4

FPGA software

Xilinx ISE Design Suit 11.1

• The ISE Design Suite 11.1 sets new industry standard for delivering FPGA design tools and intellectual property to embedded, DSP and logic designers.

• In our case we use a specific Xilinx Design Tool-kit known as the DSP Tool-kit which comprises of the System Generator (Simulink)

• The XtremeDSP Starter Kit – Spartan 3A DSP Edition cost from $600-$2000+

Temple University: Slide 5

Sample Code (Matlab Code):

Temple University: Slide 6

System Generator (Simulink) Flow-Diagram:

Temple University: Slide 7

DSP Specifications

Board:

• Embedded USB XDS100 JTAG emulator

• TI TLV320AIC3204C Stereo Codec (stereo in, headphone out)

• 512K-bit EEPROM

Chip:

• Fabricated on 0.09 µm technology.

• Can operate at up to 120 MHz

• Can use as low as 0.14 mW/MHz

• 320 KB RAM built in

• Pins: 196

Temple University: Slide 8

Design Flow (DSP)

Binary Data

C Code

Binary Data

DSP

Process is similar to running on a microprocessor.

Temple University: Slide 9

DSP software

TI Code Composer Studio v4

• Based on the Eclipse IDE

• Built in C compiler

• Full version is free as long a board with the USB XDS100 JTAG emulator is being used (software would normally cost $1895)

• Can single step through DSP assembly code as well as C code.

Temple University: Slide 10

Software Issues

• The Xilinx ISE software that includes System Generator is very bulky.

• Downloading and extracting the software takes hours.

• Installing software also takes hours.

• Each version of System Generator will only work with two or three versions of MATLAB

• Fortunately Dr. Silage had extra Xilinx licenses that he was willing to spare.