Suitability of Dynamic Latches for Sub-VT Operation

Suitability of Dynamic Latches for Sub-VTOperation

SINA BORHANIMASTER´S THESISDEPARTMENT OF ELECTRICAL AND INFORMATION TECHNOLOGYFACULTY OF ENGINEERING | LTH | LUND UNIVERSITY

Printed by Tryckeriet i E-huset, Lund 2018

SINA

BO

RH

AN

ISuitability of D

ynamic Latches for Sub-V

T O

perationLU

ND

2018

Series of Master’s thesesDepartment of Electrical and Information Technology

LU/LTH-EIT 2018-677http://www.eit.lth.se

Suitability of Dynamic Latches for Sub-VT

Operation

Sina Borhani

[email protected]

Department of Electrical and Information Technology

Lund University

Supervisor: Joachim Rodrigues

Examiner: Pietro Andreani

November 14, 2018

c© 2018Printed in SwedenTryckeriet i E-huset, Lund

Abstract

This project explores investigation on di�erent dynamic latches in 65 nm CMOStechnology. Low power has become the most signi�cant parameter of circuit designtoday and in this speci�c study reducing the power supply is the main purpose.The goal of this project is to estimate the minimum reliable supply voltage forthe selected topologies. Storage elements are the fundamental parts of VLSI sys-tems and controlling their power consumption can lead to decrease in total energydissipation of an electronic device. Unfortunately the standard cells that conven-tionally being used in electronic designs are not optimized for low supply voltages;hence it is necessary to create custom cells for the scaled voltages. In this thesisvarious simulations on di�erent latches are executed and after comparison of theresults, one of them is selected as a desired topology in order to customization.

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Acknowledgement

I would like to take this opportunity to express my sincere gratitude to my su-pervisor, Professor Joachim Rodrigues who supported and encouraged me duringmy master study and particularly for this project. His o�ce was always open forguiding and advising me. I could never �nish this master without his help andsupport.

Besides my supervisor, I would like to thank my former adviser Peter Nilsson,who created this project and today he is not among us. Rest in Peace Peter. Iwould also like to thanks to former Ph.D students in ASIC group of EIT depart-ment Rakesh and Babak who shared their useful knowledge and experiences withme.

Last but not the least, I want to express my profound gratitude to my familyfor their unconditional love and supportt.

Sina BorhaniLund, August 2018

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Table of Contents

List of Figures vii

List of Tables ix

1 Introduction 1

2 Sources of Power Consumption 3

3 Implementation and Analysis of Topologies 73.1 Worst-case determination . . . . . . . . . . . . . . . . . . . . . . . 73.2 Process variations . . . . . . . . . . . . . . . . . . . . . . . . . . . 73.3 Supply voltage investigation . . . . . . . . . . . . . . . . . . . . . . 9

3.3.1 Pass transistor 9

3.3.2 Transmission gate 12

3.3.3 True Single Phase Clocked (TSPC) Latch 14

3.3.4 Tri State Gate D-latch 17

3.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4 Comparative Analysis 214.1 Final Topology and Conclusion . . . . . . . . . . . . . . . . . . . . . 23

5 Customization 295.1 Minimizing Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 295.2 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6 Layout 336.1 Post-layout Simulation . . . . . . . . . . . . . . . . . . . . . . . . . 33

7 Conclusion 377.1 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

References 39

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vi

List of Figures

1.1 Power distribution in microprocessors [7] . . . . . . . . . . . . . . . 2

3.1 interested topologies . . . . . . . . . . . . . . . . . . . . . . . . . . 83.2 Schematic of test bench . . . . . . . . . . . . . . . . . . . . . . . . 93.3 Performance of pass transistor at 300mV . . . . . . . . . . . . . . . 103.4 Monte Carlo simulation with 10,000 runs for pass transistor latch at

Vdd = 500mV . Output behavior (a) Butterfly curve (b) . . . . . . . . 113.5 Performance of pass transistor at 500mV . . . . . . . . . . . . . . . 123.6 Monte Carlo simulation with 10,000 runs for Transmission gate latch

at Vdd = 280mV . Output behavior (a) Butterfly curve (b) . . . . . . . 143.7 Performance of transmission gate latch at 280mV . . . . . . . . . . 153.8 Monte Carlo simulation with 10,000 runs for TSPC latch at Vdd =

280mV . Output behavior (a) Butterfly curve (b) . . . . . . . . . . . . 163.9 Performance of TSPC latch at 280mV . . . . . . . . . . . . . . . . . 173.10 Monte Carlo simulation with 10,000 runs for Tri-state-gate latch at

Vdd = 290mV . Output behavior(a) Butterfly curve(b) . . . . . . . . . 183.11 Time properties of Tri-state gate latch . . . . . . . . . . . . . . . . . 19

4.1 Minimum voltage and the worst SNM for different topologies . . . . . 214.2 Average leakage current for different topologies . . . . . . . . . . . . 224.3 delay variation normalized to mean value at minimum obtained volt-

age for investigated topologies . . . . . . . . . . . . . . . . . . . . . 254.4 Delay variation at minimum obtained voltage for Pass transistor (a)

Transmission gate (b) TSPC (c) Tri-state-gate (d) . . . . . . . . . . . 27

5.1 Butterfly curve when all transistor LVT type (a) and combination ofHVT and LVT (b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.2 Delay variation of TSPC latch when all transistors are LVT family (a)and combination of HVT and LVT type (b) . . . . . . . . . . . . . . . 32

6.1 Layout of customized TSPC . . . . . . . . . . . . . . . . . . . . . . 336.2 Post layout simulation. Data and clock signals (a) and output of schematic

and Calibre view extraction (b) . . . . . . . . . . . . . . . . . . . . . 34

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viii

List of Tables

3.1 leakage current amounts for pass-transistor latch under four conditions 123.2 leakage current amounts for transmission gate latch under four con-

ditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.3 leakage amounts for TSPC D-latch under four conditions . . . . . . . 173.4 leakage current amounts for Tri-state gate D-latch under four conditions 19

4.1 sum of current leakage in standby mode for different topologies . . . 224.2 propagation delay comparison among the topologies . . . . . . . . . 234.3 Number of transistors in different topologies . . . . . . . . . . . . . . 234.4 Topologies specifications . . . . . . . . . . . . . . . . . . . . . . . . 244.5 Specification of different latches at 500mV . . . . . . . . . . . . . . 26

5.1 average leakage current for different architecture of TSPC . . . . . . 31

6.1 leakage amounts after post layout simulation at 4 conditions . . . . . 35

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Chapter1Introduction

Power dissipation has become critical parameter of VLSI design today. Popular-ity of using portable and wearable devices such as tablets, smart phones, smartwatches, Google glass, and etc and their ability for multitasking, makes thempower hungry. According to the context of these applications it is vital to ex-tend the battery life and it makes power consumption a highly important factorfor circuit designers [3][6][7]. Increasing the gap between the energy demand andbattery lifetime (battery technology improvement is slow) has convinced the VLSIdesigners to optimize conventional blocks and also to apply low energy methodsto decrease the prede�ned gap. To achieve this aim it is necessary to apply lowpower techniques in all steps of circuit design from transistor implementation toreduction technique used in operating systems. By a simple search in the internetlooking for low power technology, one can �nd hundreds of studies that explaindi�erent methods of low power techniques and much more numbers of articles andpapers that show how these methods can be applied in VLSI designs and illustratetheir e�ects on power dissipation. According to many studies, like [6][9], supplyvoltage reduction is one of the most e�ective ways to reduce total power. Storageelements, like Flip-Flop and latches are the main parts of many electronic circuitsand both lifetime and area are constrained by these elements and the node con-sumption [8]. Today in many of designs �ip-�op and latches are involved in thedata and control paths and reducing the power consumption of these elementscan help the whole design to save more energy. According to the study [2], 30%to 70% of total energy in a chip is consumed by clock distribution network. Anintegrated circuit is composed by sequential and combinational parts, memoriesand I/O devices. Figure 1.1 shows the approximation of power distribution inmicroprocessors:

Minimizing supply voltage is certainly a very e�cient way to decrease totalpower dissipation. Voltage scaling can lead to reducing active energy quadraticallyper operation, and also minimizing leakage power exponentially [9]. Indeed, re-ducing supply voltage to sub-threshold voltage improves energy e�ciency and thisadvantage motivates the circuit designers to investigate di�erent topologies andcustomize them for utilizing in circuits with lower supply voltage. Scaling volt-age reduces frequency and leads to reduction in performance linearly and it forcesSoC designers to have caution for using this technique where the fast implementa-tion is needed. To compensate for this disadvantage designers should apply other

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2 Introduction

Figure 1.1: Power distribution in microprocessors [7]

methods to improve circuit's performance. The objective of this thesis project isinvestigation on di�erent dynamic latches, to �nd the minimum reliable supplyvoltage for each design and also to analyze these circuits in case of area and per-formance. The leakage current as a crucial factor in power dissipation, especiallywhen the design is in standby mode, is considered in this project in order to controlthe total power consumption. Anyhow the main goal of the project is implement-ing selected latches in sub or near sub-threshold voltages and investigating theirbehavior and comparing them to determine a desired latch as a suitable topologyfor this aim and continuing to optimize the selected ones to achieve better results.The report is structured as follows. In chapter 2, the power dissipation sourcesare introduced. Chapter 3 is about implementation and analyses all the topolo-gies that are selected for this master thesis. In chapter 4 all the results that areachieved from the previous simulations will be compared by each other for select-ing the best latch based on minimum Vdd and lower energy consumption. Chapter5 illustrates how it is possible to improve the design, in both energy e�ciencyand performance, and also determines the optimum design. All the simulations inthese chapters executed in transistor level but in order to see the parasitic e�ectsthe metal layer of circuit should be taken into account. Chapter 6 is dedicated tothis issue and the layout of the desired latch is investigated in this section and alsothe obtained results from the layout and transistor level is compared. Conclusionand future works are included in the last part of this topic in chapter 7.

Chapter2Sources of Power Consumption

Total power dissipation (2.1) in CMOS circuits is determined by two componentsthat are called static power and dynamic power:

Ptot = Pstat + Pdyn (2.1)

Where the static power is produced by the device leakage and supply voltage. Theequation related to static power dissipation is shown in following equation:

Pstat = Vdd.Ileak (2.2)

In this equation Vdd is supply voltage and Ileak represents the device total leakagecurrent. The amount of transistor leakage current is mainly determined by CMOSfabrication process technology [8]. Scaling CMOS technology makes leakage cur-rent as a main factor in power dissipation discussions and it contains two parts:�rst one and most signi�cant part is the current through the gate and the sub-strate of transistor and it is caused by decrease in the gate oxide thickness [10].The second part of the leakage is the current between the source and the drain andit could be decreased by increasing the gate length. The other source of wastingpower in digital IC is dynamic power and is de�ned as a following equation:

Pdyn = ClV2ddfclk + IscVdd (2.3)

According to (2.3) the dynamic power contains two terms, where in the �rst com-ponent Cl is total capacitance, Vdd is supply voltage and fclk represents clockfrequency of circuit. The second part of the dynamic power happens when bothpull-up and pull-down network of the circuit are in active mode and a direct pathshort circuit from Vdd to ground will be created [8]. With regard to (2.2) and (2.3)the footprint of supply voltage as a signi�cant factor in total power consumptionis obvious. In static power, decreasing supply voltage have a direct e�ect on re-sults but using supply voltage in sub-threshold region even near threshold regionin below 90nm technology could lead to increase in leakage current and accordingto Moore's law [11] increasing the number of transistors in microprocessors willmake the large amount of leakage current. Controlling leakage is not the aim ofthis study but because of its major role in low power performance it could not beignored. Some of the e�ective techniques to prevent increasing leakage current arementioned as follow:

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4 Sources of Power Consumption

• Multi threshold CMOS: This is the e�cient technique to reduce powerdissipation generated by leakage. In this method the transistor with highVth will be placed in non critical path and in series with the supply voltage tocontrol the leakage path from Vdd to ground and the other type of transistorwith low Vth and higher switching speed are used in critical delay paths oftopologies to maintain the performance of circuit [1][10].

• Chanel length: The sub-threshold current that is written in following formhas the reverse relation with e�ective length:

Isubthreshol = IoW

Leffe

Vgs−Vthnvt (1− e

−Vdsvt ) (2.4)

From this equation keeping the gate length greater than minimum lengthwill help to reduce sub-threshold leakage [6][7][12].

• Stacking: A series connecting transistors can lead to decrease in sub-threshold leakage current if more than one transistor in the stack is in theo� mode [7].

• Power gating: This technique could be applied in complex designs, in thismethod the power supply of each inactive block must be switched o�.

As it can be seen in (2.3) the �rst term of the equation has much more e�ecton power consumption compared to the second part. Reducing power supply hasa quadratic e�ect on dynamic power. It is essential to consider that reducing thesupply voltage results in a large performance penalty and this technique can beused only where the performance of the design is not the major point and allthe focus is about making a low power circuit. Using low power supply increasesdelay time and causes harmful e�ect on energy consumption. Energy delay product(EDP) is an adequate metric to measure energy and performance in a well-designedcircuit. EDP is de�ned by following equation:

EDP =ClV

2ddtp2

(2.5)

From (2.5), tp represents propagation delay and is de�ned as a time that it takesfor the change at the input to be generated at the output and lower propagationdelay means faster design. Following equation shows how propagation delay canbe calculated:

tp =tplh + tphl

2(2.6)

This expression calculates the average delay of low-to-high and high-to-low trans-mission as propagation delay. Comparing the equations (2.5) and (2.3) shows theEDP has a quadratic relationship to the supply voltage like dynamic power Theother important metric parameter for ultra low power designs is the amount ofenergy dissipation per task [13]. Energy dissipation, like power consumption, in-cludes dynamic and static. The static and dynamic energy dissipations are derivedfrom (2.2) and (2.3) and the equations are:

Estat =Pstat

f=

VddIleakf

(2.7)

Sources of Power Consumption 5

Edyn =Pdyn

f= ClV

2dd (2.8)

From study [4] the short circuit energy could be ignored in sub threshold voltageregion. In summary, this chapter explains the background of power consumptionand also introduces the di�erent power sources and practical techniques for con-trolling the total power dissipation. Next chapter is about analyzing the di�erenttopologies and investigating on them.

6 Sources of Power Consumption

Chapter3Implementation and Analysis of

Topologies

Figure 3.1 shows the architectures of 4 dynamic latches which are investigated inthis project. Dynamic latches are used in many cases, for example as a storage nodein memories, comparator in Analog-to-digital converter, etc. These topologieswere selected because of their functionality at sub-threshold region. In simulationprocess, input and output bu�ers are used but they are removed here to simplifyingthe architectures. The test-bench that is used for the implementation is illustratedin �gure 3.2. In order to have more realistic simulation, the bu�ers are added todesigns. All the Devices Under Test (DUT) are created with the same transistortype, that is Low power High Vt (LP HVT) family. The reason for selecting thistype of transistor is because of its ability to control of leakage [1].

3.1 Worst-case determination

In order to have more practical results, all the simulations are executed in worst-case scenario. Determining the worst-case is related to many possible parameters.However the design is analyzed for a constraint number of settings that are men-tioned as corners. There are four di�erent corners that are named as `Fast-Fast'(FF), `Slow-Slow' (SS), `Fast-Slow' (FS), and `Slow-Fast' (SF). All the latches areimplemented for all corners separately and `FS' corner is considered as a worst-casefor pass transistor latch and `SS' corner is �gured out as a worst-corner for otherthree topologies. The reasons of selecting worst-case scenario for each circuit areexplained in following parts.

3.2 Process variations

Scaled down technology leads to increase in process variations and scaling the Vdd

makes these variations more distinguished [4]. One of the important elements thatis impacted by process variations is the Vth of transistors. The Vth variations resultin variations in SNM, delay, etc.

7

8 Implementation and Analysis of Topologies

(a) Pass transistor

(b) Transmission gate

(c) True single phase

(d) Tri-state gate

Figure 3.1: Interested topologies

Implementation and Analysis of Topologies 9

In this study Monte Carlo simulation with 10,000 samples is applied in orderto put in account as much as possible variations to �gure out more reliable results.All the simulations are implemented in the worst case corner at 27◦C.

Figure 3.2: Schematic of test bench

3.3 Supply voltage investigation

In this section all the latches are investigated to �nd minimum voltage level. Itshows for which supply voltage, the circuitries are still reliable. Furthermore, in-vestigation on performance, area, and leakage are interesting too. For this purposethe topologies are considered separately and later on will be compared together.To �nd the minimum supply voltage a transient simulation is performed. In orderto do this, the supply voltage is decreased as much as possible and output nodeis studied to show if the design is still in working range or not. Working in subVth and near threshold voltage causes decrease in static noise margin (SNM) andmakes the circuits more sensitive to SNM. The method that is used here to calcu-late the static noise margin was suggested in [5]. By connecting back to back gateof two instances of the investigated topology and plotting the two voltage transfercharacteristics (VTC), a butter�y curve could be plotted. On the eyes of butter�ycurves two squares could be placed and the value of SNM is determined as theside of smallest square, and the reliable amount should be more than the thermalnoise voltage at 27◦C and it is about 26mV.

3.3.1 Pass transistor

Figure 3.1a shows the architecture of pass transistor D-latch using NMOS deviceas a pass transistor. The main reason for using this topology is the low complexityand also no separate clock generator is needed. The pass transistor latch withpull down network at the �rst stage is weak to pass high value and it is becauseof losing voltage over NMOS transistor at the input. For example if Vdd applied


as an input the remained voltage after pass transistor is `Vdd − Vth'. Figure 3.3illustrates the weakness of this topology for transmitting high value. As it can beseen the unbalanced setup time of pass transistor makes it an unreliable circuitfor working at ultra low voltage region.

Figure 3.3: Performance of pass transistor at 300mV

Regardless of this weakness of pass transistor latch, still it is interesting to�gure out the minimum reliable supply voltage for this topology. Before runningsimulation it is crucial to know at which corner the worst case scenario happens. Asit is mentioned in 3.1 `slow-fast' corner determined as a worst probability for thisspeci�c design. Slow corner means highest threshold voltage and the bottle neckof pass transistor latch is transmitting high value, according to these conditionsselecting slow corner for pull down network causes more voltage drop over �rststage of the design and makes this transistor more critical. Selecting fast cornerfor pull up network makes the design even more unpredictable for inverting highvalue. A PMOS transistor switches o� when Vsource − Vgate < Vth and choosingfast corner makes the simulation executing with the lowest threshold for PMOStransistor and it makes it hard to anticipate if the Vth is bigger than the amountof prede�ned subtraction to force the pull up network to switch o�. By sweepingthe supply voltage and running the Monte-Carlo simulation for 10,000 points theminimum voltage is �ned for this architecture.


(a)

(b)

Figure 3.4: Monte Carlo simulation with 10,000 runs for pass tran-sistor latch at Vdd = 500mV . Output behavior (a) Butterflycurve (b)

Figure 3.4 shows the output result of pass transistor and also the butter�ycurve to measure the SNM. As illustrated the minimum supply voltage that assuresthe working region of circuit is 500mV with the clock pulse of 400us and theminimum amount of static noise margin for this circuit at this voltage is 65mVand is above margin. Current leakage is the other interesting and crucial factor inlow power technology. To �nd the leakage, four conditions should be consideredand these are the combination of input and clock in two states of low and high.


The leakage path is the direction between Vdd and ground, and this direction isinvestigated as leakage path for the other architectures in this master work. Table3.1 shows the current leakage amounts for this circuit at 500mV.

Table 3.1: Leakage current amounts for pass-transistor latch underfour conditions

Clk On On O� O�

In 1 0 0 1

Leakage 16pA 3.4pA 12pA 35pA

As the table shows the worst case occurs when the input is logic �1� andalso the sum of leakage at the standby mode is more than 2x higher this amountwhen the clock is on. Figure 3.5 represents the performance of the pass transistorlatch at 500 mV. Comparing this �gure to Figure 3.3 demonstrates that increasingthe minimum supply voltage makes the setup time more symmetric and the timeneeded for writing high value gets so close to the one writing `0' logic.

Figure 3.5: Performance of pass transistor at 500mV

3.3.2 Transmission gate

Figure 3.1b represents transmission gate latch and as it can be seen the onlydi�erence between this topology and pass transistor type is existence of an extraPMOS transistor in sequential part of the transmission gate. According to theFigure 3.3 ,it could be understood that the pass transistor is weak to transmit highvalue and good to transfer the low value. In order to improve the performancein high value the transmission gate is used. In this case di�erent clock phases


are needed, and to generate di�erent phases an overlapping clock generator isrequired. To determine minimum voltage the same process is going to be doneas an explained in pass transistor section. For this topology the crucial corneroccurs when the circuit operates at `SS' corner and it is because of utilizing HVTtransistor at the design specially at the �rst stage of the latch, where the transistorsare controlled by enable signal. Working at sub threshold voltage becomes harmfuland operating under the slow corner where the circuit is constructed by slowtype transistors makes the situation even worse. Figure 3.6 shows the outputbehavior of transmission gate latch and butter�y curves which are achieved fromMonte-Carlo simulation based on 10,000-points at slow corner for both pull upand pull down networks. Minimum reliable voltage for this case is 280mV withthe clock frequency of 2.5KHz . The minimum SNM obtained from VTC analysisfor this supply voltage is 50mV. The crucial leakage current path is the samedirection as mentioned previously, and it is the path between `Vdd' and `gnd' andin order to measure this, the minimum possible voltage is set to 280mv and thesimulation starts in `transient' mode. Table 3.2 lists the measurement in 4 statesfor this case. With regard to this table the amounts of leakage in standby mode is

Table 3.2: Leakage current amounts for transmission gate latch un-der four conditions

Clk On On O� O�

In 1 0 0 1

Leakage 1.4pA 1.9pA 5.5pA 5pA

preeminent and this a�ects static power and total power consumption negatively.Timing properties of this architecture is illustrated in Figure 3.7 and the averageof propagation delay for rising and falling edge is 6us.


(a)

(b)

Figure 3.6: Monte Carlo simulation with 10,000 runs for Transmis-sion gate latch at Vdd = 280mV . Output behavior (a) Butterflycurve (b)

3.3.3 True Single Phase Clocked (TSPC) Latch

True single phase clocked (TSPC) D-latch is commonly used in low power andhigh speed circuits as a storage element. The TSPC latch uses just one clockphase, as architecture shows in Figure 3.1c. The length and the width of all 6transistors are 65nm and 270nm respectively and the rest of selected transistors


Figure 3.7: Performance of transmission gate latch at 280mV

are LP HVT. In order to have smooth performance the width of PMOS transistoris selected at least 2x more than minimum width. For this schematic, as it is illus-trated, 2 NMOS transistors are utilized in pull down network for each stage andin order to decrease the resistance the width of NMOS transistors are increased.All the simulations which were implemented for two previous topologies, in sec-tions 3.2.1 and 3.2.2 are applied for this circuit too. With regard to the schematicof design and the interest of the project for working at sub threshold region theslow-slow corner is employed for this simulation. Figure 3.8a shows the output di-agram at the minimum reliable voltage for keeping the circuitry in working regionand Figure 3.8b demonstrates the voltage transfer characteristic information usingbutter�y curves. The minimum supply voltage for this architecture, with deter-mined features, is 280mV and the minimum static noise margin (SNM) is 62mV.The maximum clock frequency for this particular topology, under the introducedcondition is 10KHz.


(a)

(b)

Figure 3.8: Monte Carlo simulation with 10,000 runs for TSPC latchat Vdd = 280mV . Output behavior (a) Butterfly curve (b)

Following Table shows the result of current leakage measurement for combi-nation of four states. 235mv is applied as a supply voltage:

According to the table the size of leakage in standby mode compared to ac-tive mode for this architecture is lower and the signi�cant improvement could berecognized by comparing these results to table 3.2. Stacking one more transistorin series line for both stages, in TSPC latch, results in advantage of controllingcurrent leakage at the o� state. Therefore this circuit could be a good option forutilizing in low power microprocessor. Figure 3.9 displays TSPC performance at


Table 3.3: Leakage amounts for TSPC D-latch under four conditions

Clk On On O� O�

In 1 0 0 1

Leakage 1.7pA 1.7pA 1pA 700fA

the desired supply voltage. For this particular design the propagation delay isequal to 3.2us and this value is obtained from the average of 4us for tplh (low tohigh propagation delay) and 2.4us for tphl (high to low propagation delay).

Figure 3.9: Performance of TSPC latch at 280mV

3.3.4 Tri State Gate D-latch

A dynamic latch based on clocked inverter, also called tri-state gate, is shown inFigure 3.1d. As it can be seen the �rst stage of the topology is stacked by two moretransistors compared to pass transistor D-latch and transmission gate D-latch andone more PMOS compared to TSPC D-latch. The length for all transistors is thesame and it is 65nm but, for the �rst stage of the topology, the width of PMOStransistors is 540nm and this number for the NMOS devices is 270nm. Widthof transistors for the second stage is 270nm and 135nm for PMOS and NMOSrespectively. The worst case scenario for this circuit, for �nding minimum reliablevoltage, is happening at `SS' corner as the same as TSPC latch and with the samemotivation. Figure 3.10 displays the results of Monte Carlo simulation with 10,000samples at the Slow-Slow corner:


(a)

(b)

Figure 3.10: Monte Carlo simulation with 10,000 runs for Tri-state-gate latch at Vdd = 290mV . Output behavior(a) Butterflycurve(b)

290mV is achieved as a minimum supply voltage, from transient analysis, andaccording to the butter�y curve the worst SNM amount for this voltage level is stillabove margin. The maximum speed for this circuit, regarding to the determinedfeatures, is 5.5 KHz and increasing the clock pulse does not help anymore todecrease the voltage amount. Same as other topologies in order to have betterestimation about power wasting by this circuit, measuring the leakage currentwould be essential. Table 3.4 represents the leakage amount of di�erent states for


tri-state gate latch: The sum of leakage when the switch is on is around 3.5pA

Table 3.4: Leakage current amounts for Tri-state gate D-latch underfour conditions

Clk On On O� O�

In 1 0 0 1

Leakage 1.9pA 1.7pA 4.5pA 3.5pA

and this value is so close to the on state current leakages that obtained for twoprevious latches. It is expected that the leakage for o� state, because of stackingtwo transistors at the �rst stage of the design, decreases. Comparing this table totable 3.2 shows that this decrease happens but is not as much as the reduction thatcame to TSPC latch. The reason for this lack of decline is that the architectureof design in stage 2 where the circuit is formed by the inverter which consists oftwo transistors stack compare to 4 devices stack at the �rst stage. Propagationdelay as the other interested element was investigated and the related results arepossible to evaluate from Figure 3.11:

Figure 3.11: Time properties of Tri-state gate latch

Utilizing equation (2.6) gives the propagation delay as 3.7us. The size of tplhand tphl for this implementation are, 3us and 4.4us, respectively.


3.4 Summary

This chapter analyzes di�erent latches in terms of low power consumption andinvestigates them in various prospects. These considerations can help system onchip designers to have better understanding of the attitudes and characteristics ofthose selected latches and can give better vision for choosing proper latches forparticular circuits.

Chapter4Comparative Analysis

In order to �nd the desired topology, compatible to low power supply, comparingthe collected results from previous chapter is necessary. This chapter is completelydedicated for this purpose. For the �rst step of evaluation, minimum reliable sup-ply voltage for each of latches are compared with each other and as Figure 4.1demonstrates except pass-transistor latch other investigated latches work with thesupply voltage lower than 300mV. As we can see, the minimum voltage level for

Figure 4.1: Minimum voltage and the worst SNM for different topolo-gies

both transmission-gate and TSPC latch is the same but the amount of SNM thatis obtained for these circuits are di�erent and TSPC has better situation com-pared to transmission gate with the same supply voltage. In low power technique,decreasing the voltage is not the only important factor for reducing the power con-sumption. As it is discussed in chapter 2, current leakage is the other determinantelement for this goal. In low power concept the current leakage in inactive modeis more interesting and table 4.1 explores the summation of leakage in o� statemode for these architectures:

21

22 Comparative Analysis

Table 4.1: Sum of current leakage in standby mode for differenttopologies

Topologies Pass transistor Transmission gate TSPC Tri state gate

Leakage 47pA 10.5pA 1.7pA 8pA

According to this table the size of total leakage in inactive state for TSPC latchis much lower than three other designs and it is because of transistors stacking.Figure 4.2 shows the average of leakage for each of the considered blocks. Fromthe �gure, the average leakage of pass-transistor is signi�cantly higher than otherarchitectures and the lowest amount belongs to TSPC:

Figure 4.2: Average leakage current for different topologies

Propagation delay tp and its e�ect on the power consumption and digitalcircuits performance is not the focus of this text, but in order to choose e�cienttopology it is good to explore that. With regard to equation (2.5), propagationdelay has a direct in�uence on energy delay products in digital circuits. Have ahigh voltage as a supply leads to reduction in the delay but it harms the energyand on the other hand decreasing voltage pushes propagation delay to increase.Hence, to choose proper latch that is suitable in sub-threshold region �nding thedevice with lower delay is interesting. Table 4.2 compared the propagation delayof these four topologies under minimum reliable voltages according to data fromchapter3.

As it can be seen the pass-transistor's delay is much lower than others andit is because of its highest supply voltage (500mV). Between three other latchesTSPC has lowest propagation delay and this value can makes it good candidatefor �nal design. Area is money; it means the smaller the design the cheaper theprice becomes. An embedded system designer should be more careful for the size

Comparative Analysis 23

Table 4.2: Propagation delay comparison among the topologies


tp(us) 2.4 6 3.7 3.2

of the circuit. Number of transistors could be a good criterion measurement forevaluating the size of a digital storage element and other digital circuits. Nexttable 4.3 compares the studied latches in terms of number of transistors:

Table 4.3: Number of transistors in different topologies


Number of PMOS 2 3 3 3

Number of NMOS 3 3 4 3

Total 5 6 6 6

According to table 4.3 the total number of transistors for pass-transistor latchis 5 and it is one less compared to other latches. The remained topologies havethe same number of transistors, but in TSPC just 2 PMOS transistors are utilizedcompared to 3 employed PMOSes for both transmission-gate and tri-state gate,in addition because of these two topology architectures in order to generate nonoverlapping clock at least one inverter is required and it means that two moretransistors are required for the building of these two designs. Ultimate topologywill determine in next section.

4.1 Final Topology and Conclusion

Study on dynamic latches, which are suitable for working in sub threshold voltage,is the aim of this project and all the important factors which are e�ective in powerdissipation area were studied. Each of circuits according to their results, whichare gained from several analyses, has some advantages and disadvantages. Forexample, if the �nal design has area constraint and the power consumption is notthe main issue, pass transistor D-Latch with maximum 5 transistors could be agood option to utilize in the design, but the performance of the circuit, especiallyfor transmitting the data in high value, is the bottleneck of this latch. Transmis-sion gate is the other topology that generally has a good execution in low supplyvoltage, and has an acceptable average leakage, but in case of timing speci�cationand design performance this topology is handicapped. Also the numbers of usedPMOS in this latch and need for an extra inverter to create two di�erent phasesmakes this design area-hungry. Two remained topologies presented good perfor-mance in low voltage and have close timing speci�cation results, but the leakageof Tri-state gate D-latch, especially in o� state, is more than TSPC (True single


phase clocked) latch. Comparing the number of transistors of both latches ex-plained that Tri-state gate needs an extra inverter, to provide the non overlappingclock generator, which leads to larger layout size compared to TSPC. Table 4.4demonstrates the di�erent features which belong to investigated latches during thesimulations. This table gives possibility for easy comparison of di�erent topologiescharacteristics.

Table 4.4: Topologies specifications

Topologies Pass-transistor Transmission-gate TSPC Tri-state gate

Minimum voltage(mV) 500 280 280 290

Maximum frequency(KHz) 2.5 2.5 10 5.5

Total leakage current(pA) 66.4 13.8 5.1 11.6

Propagation delay(us) 2.4 6 3.2 3.7

Number of transistors 5 6+2 6 6+2

SNM(mV) 65 50 62 70

Energy per operation (fJ) 21 1.7 1 1.45

Along all the results that were explained previously, this table contains theinformation of energy per operation for each topology and as it can be seen thetotal energy dissipation for TSPC latch is lower than others. As it is explained in3.3 voltage scaling has signi�cant e�ect on process variation and one of elementsthat su�er from this variation is process delay. This delay variation could beharmful for time sensitive designs, especially where the number of gates connectedtogether. To see this variation for these four topologies the Monte Carlo simulationfor 10,000 point was executed at the minimum reliable voltage that is achieved fordi�erent circuits. Figure 4.3 shows the histogram graph of delay variation forrepresented latches:


(a) Pass Transistor

(b) Transmission gate

(c) TSPC

(d) Tri-state gate

Figure 4.3: delay variation normalized to mean value at minimumobtained voltage for investigated topologies


As it is displayed in Figure 4.3 the delay variation around mean value does notcorrespond with Gaussian distribution and the delay variation for pass transistor,transmission gate, TSPC and tri-state-gate is 55%, 40%, 45% and 53% respec-tively.With regard to these histogram graphs the probability of delay shorter thanthe average is more than longer delay but the amount of longer delay is moreconsiderable and it is several times longer than the average. The original delaythat obtained from the simulation can be seen in Figure 4.4.

The graph which represented the delay variation of pass-transistor latch showsthe faster performance among the other latches and it is because of higher sup-ply voltage (500mV). Increasing voltage supply to near threshold voltage resultsto improve performance of latches but in the other hand it leads to increase inpower consumption. The next table 4.5 explains the results of di�erent featuresof these prede�ned latches at 500mV (the results related to pass transistor dupli-cated here): This evaluation shows that except pass transistor other three devices

Table 4.5: Specification of different latches at 500mV

Topologies Pass-transistor Transmission-gate TSPC Tri-state gate

Minimum voltage(mV) 500 500 500 500

Maximum frequency 2.5KHz 1MHz 1.4MHz 1MHz

Total leakage current(pA) 66.4 15.8 8.9 16.3

Propagation delay 2.4us 36ns 28ns 30ns

Number of transistors 5 6+2 6 6+2

SNM(mV) 65 135 140 150

Energy per operation (fJ) 21 3.2 2.8 3.3

have progressed on performance and also have improved on hold failure margin.Increasing the supply voltage, as it was expected, has negative e�ects on currentleakage and energy dissipation. This chapter tries to evaluate and compare someof latches with each other in di�erent aspects and some negative and positive per-spectives of these circuits were discussed and �nally TSPC D-latch is selected asthe targeted topology in this project. Based on all information and results thathas been achieved a TSPC latch is an e�cient circuit for creating a low powercircuit and also has better performance compared to those other latches. In thenext chapter it will be tried to optimize TSPC in case of leakage and performanceand further customize it to minimize the supply voltage even more.


(a)

(b)

(c)

(d)

Figure 4.4: Delay variation at minimum obtained voltage for Passtransistor (a) Transmission gate (b) TSPC (c) Tri-state-gate (d)


Chapter5Customization

After selecting the desired topology now is time to manipulate the design in orderto optimize it in case of power consumption and performance. The �rst priority istrying to push down the minimum voltage level and the next step is applying theleakage reduction mechanisms.

5.1 Minimizing Supply Voltage

One of the major ways to decrease supply voltage is utilizing transistor with lowestthreshold voltage. Replacing HVT devices in TSPC architecture with LVT helpsthe circuit work at 240mV which is 40mV lower than when the device created byHVT type and maximum clock frequency for new block is 100x faster i.e. 1MHz,but the point is to apply transistor with low threshold which leads to enormousincrease in the current leakage. This increment makes the design power hungryand not reasonable for employing in ultra low power application. LVT transistorsare used in a design where performance and timing are of critical value, but in thisproject the goal is controlling power dissipation. Although using low thresholdvoltage transistors can be charged by lowest power supply but in fact it does notreduce the total power consumption. The total energy per task for this conditionis 1.15fJ and it is 15% higher when all transistors selected as high-Vth. ApplyingMulti-Vth technique in circuit architecture can help solve this issue. To controlthe leakage, it is critical to build up the pull up network with high-Vth deviceswhich is due to the proximity of PMOS network to the Vdd supply. In order to�nd out which transistors should be replaced by LVT, it is necessary to recognizethe device bottleneck. In this latch the transistors which control the enable signalare the weak part of the topology and they can be replaced by low-Vth transistors.However this change results in an increase in the leakage but on the other hand theTSPC can work at a lower voltage level compared to the unchanged architecture.The new voltage level is 250mV and the amount of energy dissipation per taskis 850aJ. The following �gure shows the reliability of TSPC latch for minimumobtained voltage from 10,000 samples of Monte Carlo simulation:

29

30 Customization

(a)

(b)

Figure 5.1: Butterfly curve when all transistor LVT type (a) and com-bination of HVT and LVT (b)

The minimum static noise margin for the design made by low threshold volt-age transistors at 240mV is 30mV and this number for the device built by thecombination of low-Vth and high-Vth is 43mV. Temperature for all simulations hasset 27◦C and thermal noise at this degree is 26mV. Table 5.1 presents the averagecurrent leakage for TSPC latch with di�erent architecture at minimum reliablevoltage:

From the table it can be discovered that the leakage increases dramaticallyaround hundred times when all the transistors are selected as LVT type and this

Customization 31

Table 5.1: Average leakage current for different architecture ofTSPC

Architecture HVT LVT Combination

Vdd(mV) 280 240 250

Leakage(pa) 1.3 125 1.7

amount could be controlled by applying multi threshold voltage technique. As it ismentioned in previous chapter, delay variation is one of the incomes from operationat sub threshold voltage region. Although using Low-Vth transistor improves thecircuit performance at higher frequency but is not an e�ective way to decreasedelay variation and this is unavoidable until the execution voltage for circuits islower than the threshold voltage of LVT transistor which is higher than 300mV.As Figure 5.2 shows the delay variation around mean value when the TSPC latchdesigned by LVT family being used is 41% and this is only 6%lower than whenall transistors come from HVT family. Delay variation is 45% for the design usingcombination of these two types of transistors at its schematic.

5.2 Summary

This chapter explains the process of developing a design in order to force it towork with lower supply voltage than what is gained from chapter 3 and also keepthe leakage amount as low as possible. This aim is achieved by customizing theselected topology in regard to the technique that is discussed in chapter 2 whichis multi threshold voltage method. By recognizing critical pass and replacing itwith low threshold voltage transistor and keeping the other transistor as high Vth,the supply voltage could be decreased around 11% and it is 30mV lower than ofthe determined value for power supply before customization. With regard to thisexplanation and according to the results that are obtained in this chapter theTSPC latch constructed with di�erent threshold voltage transistors has chosen asa device for performing in lower voltage with acceptable reliability.

32 Customization

(a)

(b)

Figure 5.2: Delay variation of TSPC latch when all transistors areLVT family (a) and combination of HVT and LVT type (b)

Chapter6Layout

In order to have better understanding about the circuit behavior after manufactur-ing, the parasitic extraction model is required and creating the design layout andimplementing post layout simulation will show us the e�ect of this phenomenonon the circuit and also gives more reliable result to compare with schematic sim-ulation.

Scaling technology to micrometer and nanometer makes the wires as consider-able electronic elements. In order to have low parasitic e�ects it is really importantto avoid long wiring and interconnection should be as short as possible and thistechnique helps to create a layout with less parasitic series.

6.1 Post-layout Simulation

The layout of customized topology is designed in order to generate calibre modeland �gure out the parasitic e�ect on ultimate design through applying this calibre-view on schematic model. Figure 6.1 demonstrates the layout of customized versionof true single phase that is obtained from chapter 5.

Figure 6.1: Layout of customized TSPC

33

34 Layout

After creating the layout and executing DRC (Design Rule Test) and LVS(Layout VS Schematic) and solving all the errors the calibre view was generated.In order to discover probable e�ect on output, because of parasitic e�ects, the postlayout simulation is required and also comparing this result with the outcome thatis reached by schematic simulation can give us a better perception of parasitice�ects on electronic circuits.

Next �gure is showing an error between the results achieved from schematicand post layout simulation:

(a)

(b)

Figure 6.2: Post layout simulation. Data and clock signals (a) andoutput of schematic and Calibre view extraction (b)

The current leakage also is a�ected negatively by the parasitic issue. Table6.1 explores the new leakage amount after post layout simulation: According tothis table the average leakage of TSPC latch from post layout simulation is about

Layout 35

Table 6.1: Leakage amounts after post layout simulation at 4 condi-tions

Clk On On O� O�

In 1 0 0 1

Leakage(pA) 1.9 1.9 2.2 2

2pa and this is a small increasing compared to the average leakage values thatwas collected from schematic view (table 5.1). The energy consumption per taskfor post layout simulation is measured and the amount is upraised 8% and this islifted to 920aJ. By considering the post layout investigation on upgraded topologyit is clear that the parasitic e�ect, that mainly occurs because of capacitanceand resistance interconnection, can decrease the capability of electronic circuitsespecially when they are implemented at ultra low supply voltage.

36 Layout

Chapter7Conclusion

Power usage of electronic devices, particularly the portable ones, became an im-portant parameter to focus on. To decrease the power dissipation and energyconsumption it is necessary to have a practical road map to show us correct direc-tions for achieving acceptable results. During these years many of researchers indigital area worked on di�erent methods to �nd a useful solution for reaching thisaim. These techniques could be included in both software and hardware area. Butin practice in order to have optimum output it is critical to �nd the bottleneckof each circuit and discover which parts of the device are more power consumingand choose the best method for developing that particular part to improve wholedevice functionality in scaled voltage region. Memories and storage elements areinteresting parts to investigate in order to save power. With regard to 1.1 �gure 1around 40% of power in electronic devices is utilized by storage components andthis size of energy usage in these elements convinced system on chip designers to�nd solutions for decreasing memories power consumption. In this master work,scaling supply voltage is investigated as a main technique to control the powerconsumption and this method is applied for di�erent latches to �nd the topologythat is proper for working in sub-threshold region. In this way it was essential thatthe other determined parameters such as propagation delay and current leakageamount be considered. Decreasing the transistors length to nanometer makes thecurrent leakage as one of the most important sources of power consuming andignoring this component can lead to worse results. The ultimate topology foroptimization was selected after numbers of simulations and investigations fromdi�erent prospects on di�erent latches and it was true single phase latch. Utilizinglatches instead of �ip �ops have some advantages like they are faster and they havebetter performance in low power designs. Among those advantages TSPC o�ersan extra bene�t and it is the possibility of embedding logic functionality into thistype of latches [14]. The results, those are collected from the both transistor leveland post layout simulation, are credible evidence that the TSPC latch is a suitabletopology for employing in low power circuits.

7.1 Future Work

The results that obtained in this master project show that in order to have a suit-able design for working in sub-threshold region it is necessary to customize the

37

38 Conclusion

standard cells. Standard cell customization would lead to gain in power consump-tion, area and performance. Most of standard cells are not optimized for utilizingin ultra low power devices and creating a special sub-threshold library is veryessential. In this project some of dynamic latches were investigated and the mini-mum reliable supply voltage for each of them was recorded and also one of themwas customized with basic improvements. Working in sub-threshold region causeto process variation and investigating on di�erent cell to �nd optimum voltage inorder minimizing power consumption could be pursued as a future work.

References

[1] Rajesh Mehra and Priyanka Sharma, True Single Phase Clocking Flip-Flop

Design using Multi Threshold CMOS Technique, International Journal ofComputer Applications (0975 � 8887) Volume 96� No. 11, June 2014.

[2] Kunwar Singh, Satish Chandra Tiwari and Maneesha Gupta, A Modi�ed Im-

plementation of Tristate Inverter Based Static Master-Slave Flip-Flop with

Improved Power-Delay-Area Product, The Scienti�c World Journal Volume2014.

[3] Kaushik Roy, Leakage Power Reduction in Low-Voltage CMOS Designs, Elec-trical and Computer Engineering, Purdue University W. Lafayette, IN 47907,USA.

[4] E. Vittoz, Weak Inversion for Ultimate Low- Power Logic In Low- Power

Electronics Design, CRC Press, Dec. 2009, pp. 16-1-16-18

[5] J. Lohstroh, E. Seevinck, and J. de Groot, Worst-case Static Noise Mar-

gin Criteria for Logic Circuit s and Their Mathematical Equivalence. IEEEJournal of Solid-State Circuits, vol. 18, no. 6, pp. 803-807, 2012.

[6] Massimo Alioto, Senior Member Ultra-Low Power VLSI Circuit Design De-

mysti�ed and Explained: A Tutorial. IEEE TRANSACTIONS ON CIR-CUITS AND SYSTEM-I: REGULAR PAPERS, VOL. 59, NO. 1, JANUARY2012.

[7] Paulo Francisco Butzen and Renato Perez Ribas, Leakage Current in Sub-

Micrometer CMOS Gates. Universidade Federal do Rio Grande do Sul.

[8] Ahmed Sayed, Hussain Al-Assad, Survey AND EVALUATION OF LOW-

POWER FLIP-FLOPS. Department of Electrical and Computer EngineeringUniversity of California Davis, CA, U.S.A.

[9] Near Threshold Computing, Technology, Methods and Application. Springer.

[10] A. Rjoub and A. Ajlouni, An E�cient Approach to Calculate Leakage Current

Based on SPICEs Parameters at CMOS Transistors. Computer EngineeringDept. Jordan University of Science and Technology Irbid P. O. Box 3030 �Jordan

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[11] S. Mukhopadhyay and K. Roy, Accurate Modeling of Transistor Stacks to

E�ectively Reduce Total Standby Leakage in Nano-scale CMOS Circuits. VLSICircuits, Dig. of Tech. Papers, 2003, pp 53-56.

[12] UDSM sub-threshold leakage model for NMOS transistor stacks..

[13] Oskar Andersson. Ultra-low Voltage Embedded Memories - Design Aspects and

a Biomedical Use-case. Department of Electrical and Information Technology,Lund University, 2016.

[14] JAN M. RABAEY, ANANTHA CHANDRAKASAN and BORIVOJENIKOLIC, Digital Integrated Circuits, A Design Perspective, Second Edition.

Suitability of Dynamic Latches for Sub-VTOperation

SINA BORHANIMASTER´S THESISDEPARTMENT OF ELECTRICAL AND INFORMATION TECHNOLOGYFACULTY OF ENGINEERING | LTH | LUND UNIVERSITY

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Suitability of Dynamic Latches for Sub-VT Operation