Submission 1003Baranski 1

Reliability Studies on Aeroflex’s RadHard ViaLinkTM PROM

Brian Baranski, Anthony Jordan, and Craig HaferAeroflex Colorado Springs

(719) 594-8081 brian.baranski@aeroflex.com

Submission 1003Baranski 2

Product Overview

• 32k x 8 asynchronous 256Kbit PROM

• 3.3v and 5v operation

• Total Ionizing Dose (TID) hard up to 1Mrad(Si)

• Single event latch-up (SEL) immune > 110MeV-cm2/mg

• Single event upset (SEU) - At 3.0v operation, onset LET of 40 MeV-cm2/mg, and error rate of 6.5E-12 errors/device-day. At 4.5 the onset is 57 MeV-cm2/mg, and the error rate is 5.3E-15 errors/device-day

• Built on 0.35m commercial process using QuickLogic’s ViaLinkTM programming element

Submission 1003Baranski 3

ABSTRACT

• Antifuse reliability has recently become a hot topic in the aerospace industry. Aeroflex Colorado Springs has recently completed development of a RadHard 256K PROM utilizing QuickLogic’s ViaLinkTM technology as the programmable element. QuickLogic has performed many ViaLink reliability studies, Aeroflex performed additional tests to determine the reliability of the ViaLink under different programming and stress conditions. This paper will discuss Aeroflex’s reliability studies, test results, and design considerations done to maximize ViaLink reliability

Submission 1003Baranski 4

Wafer Level Test Structures

• Test structures on the wafer allow a great deal of flexibility to program and stress individual ViaLinks under multiple conditions that are not always feasible in an actual part. Wafer level testing provides a wide range of information about the most reliable ways to program and use the ViaLink

• Aeroflex programmed and stressed ViaLink test structures varying several parameters including programming current, number of programming pulses, and stress current

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Wafer Level Tests

• Most tests performed had a much higher stress current than can be accomplished in actual parts. This allowed us to accelerate the failures and plot the mean time to failure (MTTF) for different conditions

• Others have shown that a higher current density through a ViaLink accelerates the MTTF. Since the PROM ViaLink programming and use conditions differ from QuickLogic’s ViaLink conditions in their FPGA’s, Aeroflex evaluated the effect of different current densities on the ViaLink

Submission 1003Baranski 6

MTTF for typical programming conditionMTTF vs Current Density

0.000

5.000

10.000

15.000

20.000

25.000

30.000

35.000

40.000

45.000

20 30 40 50 60 70

Stress Jmax

ln(M

TT

F)

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Device Testing - Test Mode

• Based on QuickLogic’s reliability data showing a very low ViaLink failure rate, a test mode was implemented in the PROM design to increase the stress upon the ViaLink’s.

• During normal operation the ViaLink’s are only stressed for a short period of time. When this test mode is enabled, stress is placed upon the ViaLink’s for the duration that they are selected. This greatly increases the stress for both ViaLink failure modes

• For an unprogrammed ViaLink, this places a higher voltage across the ViaLink to see if it will program unintentionally

• For a programmed ViaLink, this mode increases the duration of the current stress allowing a higher joule heating of the filament than would be available during normal operation

Submission 1003Baranski 8

Device Testing - Overview

• Aeroflex performed three main device level life-tests on the PROM. – High Temperature Operating Life (HTOL) - This is a high

temperature, high voltage life test. This places a higher voltage stress on unprogrammed ViaLink’s as well as stressing CMOS. It also places a high current through programmed ViaLink’s along with the ambient high temperature to increase any heating effects

– Low Temperature Operating Life (LTOL) - This is a low temperature life test, designed to place the highest amount of current density stress upon programmed ViaLink’s

– Standard Life Test - This life test is mainly a control group against which we can compare the above accelerated life tests

Submission 1003Baranski 9

Design Considerations

• Several design decisions were made based upon the reliability information available.

– For the unprogrammed ViaLink, the voltage across it was limited during operation

– For the programmed ViaLink, the read current to program current ratio was minimized in order to enhance ViaLink reliability by minimizing JMAX

– The pulsed read technique minimizes the amount of time the ViaLinks see any current or voltage stress

Submission 1003Baranski 10

Conclusion

• Aeroflex has completed qualification of a RadHard 256K PROM utilizing QuickLogic’s ViaLink technology as the programmable element

• Utilizing information gathered at Aeroflex and elsewhere, ViaLink reliability can be maximized through design techniques

• The PROM has been through several life tests utilizing test modes that increase the stress on the ViaLink more than is possible during normal operation