Strips trigger rate Issues & Can the strips achieve the following proposed trigger parameters

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Strips trigger rate Issues & Can the strips achieve the following proposed trigger parameters

(proposed following Stanford AUW)?

L0 accept rate: 500 kHz

L0 latency: ~ 5-6 ms

L1 accept rate: 200 kHz

L1 latency: 20 ms

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L1 trigger rate capability will depend crucially on expected pileup

In fact system design in terms of front-end data formatting depends critically upon this number.

What is inelastic cross-section at sqrt(s) = 14 TeV?

Is design luminosity = 7 x 1034 cm-2 s-1 ?

Also bunch crossing at 25 ns or 50 ns plays a role

What are machine parameters to be used for LOI ?

Need these numbers in the LOI parameters document

For this preliminary trigger analysis we will use between 150-200 pileup events at 25 ns bunch crossing.

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Array of Pileup Numbers

• Simulation used for trigger calculations is for 200 events/bunch crossing

• We have occupancies for 200 events

• We connect L1 trigger rates to occupancies

• But need to understand this table to connect trigger rates to luminosity

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Upgrade Architecture for Short StaveProposed Readout

Hyb

rid 1

0 AB

CN13

0, 1

HCC

Sensor M

odule

5120 Strips

GBT

Hyb

rid 1

0 AB

CN13

0, 1

HCC

•HCC is the “Hybrid Controller Chip”

• Serves as interface for TTC/Data between ABC130 ASICs and Service Bus

• 12 Modules (Utopia layout) are shown in drawing. May be 13 modules in Cartigny layout

• Each HCC maps readouts out 10 ABC130 in two parallel streams. Thus HCC readouts out 2560 strips

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Upgrade Architecture for Short Stave

Note: Each data line is associated with an “e-link” in GBT terminology

Important points to note are:• A short strip cartigny stave needs 26 readout lines (maps poorly to GBT).• The data rates on each data line are only available at three discrete values.• The HCC in the strips detector (petals & barrels) with the most average hit data to read

out will determine readout and thus trigger rates.

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ABC130 Buffers and Implications for Trigger Parameters

• L0 accept rate = 500 kHz ?Yes, L0 Accept rate my be higher. Simply determined by tradoff between L0 accept rate and L1 Latency

• L0 Latency ~ 5-6 ms?Determined simply by L0 Pipeline Depth/25 MHz = 256/ 25 MHz = 6.4 ms

• L1 Accept rate 200 kHz?This will require more detailed calculation in subsequent slides

• L1 Latency : 20 ms?L1 latency = Depth of L1/R3 buffer/L0 accept rate = 256/500 kHz = 512 ms ! More than sufficient latency. Can trade off latency for higher L0 accept rate if desired.

3 out of 4 trigger parameters trivially satisfied due to ABC130 dual 2 x 256 dual buffer architecture

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L0_3BC Packet L0_1BC Packet R3 Packet

Start Bit Start Bit Start Bit

Chip_ID[3:0] Chip_ID[3:0] Chip_ID[3:0]

Type [3:0] Type [3:0] Type [3:0]

L0ID [7:0] L0ID [7:0] L0ID [7:0]

BCID [7:0] BCID [7:0] BCID [7:0]

clst1_ch[7:0] clst1_ch[7:0] clst1_pos[7:0]

clst1_hit0[2:0] nxtch[2:0] clst2_pos[7:0]

clst1_hit1[2:0] clst2_ch[7:0] clst3_pos[7:0]

clst1_hit2[2:0] nxtch[2:0] clst4_pos[7:0]

clst1_hit3[2:0] clst3_ch2[7:0] OvlF

SPARE[12:0] nxtch[2:0] STOP bit

STOP bit STOP bit

4 clusters central hit position

3 clusters geom. patterns

Even

t ID

ABC130 Data Format59 bits per data packet. For L1 Accept calculation we require that only L0_1BC Packet and R3 Packet data be sent. L0_3BC Packet send data for 3 consecutive bunch crossings; there is not sufficient bandwidth for this.

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• To get a reasonable L1 rate, we must use L0_1BC data format where data from adjacent bunch crossings is not used.

• What does the current ABCD chip use for physics data taking?

• Is there any reason during physics data taking why adjacent bunch crossing will be desired? Presumably adjacent bunch crossings are useful for initial calibrations and timing setup.

ABC130 Data Format

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Utopia Layout

L1 accept rate “appears” to be determined by this region of innermost short strip layer. Note simulation was for 10 cm long strips. Occupancy is halfed for 5 cm strips

Strip Occupancy 200 Pileup Events

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Strip Occupancy Summary

Divide by 2 for 5 cm stripsInner Short Strip Barrel

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Disk Cluster Widths

There is a strong radial cluster width dependence

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Barrel Cluster Widths

Cluster width values and z dependence very similar all layers

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Comments on Simulation

• Simulation data provide by Karoline Selbach and Nick Styles. Andre Schaelicke provide information below on simulation and interaction cross section

• 200 event pileup sample

• Sample represents 5 x 1034 cm-2 s-1 at 50 ns corresponding to 80 mb cross section

• Sample is an ND + SD + DD Pythia 8 mix with some pt cut (A. Schaelicke)

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• Occupancy previously shown was strip occupancy, not hit (or cluster) occupancy.

• What is relevant for the readout rate is hit occupancy due to ABC130 data packet formatting (it reads out clusters)

• Need to correct “strip occupancy” plots with average width per cluster to get “hit occupancy” plots.

• Hit occupancy = (Number of hits/detector-event)/(Number strips/detector )= number of hits/strip-event

Hit vs Strip Occupancy

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Hit Occupancy Approximated from Previous Plots(and long strips now ~ 5 cm long)

• Occupancy is now relatively independent of z position

• Long Strips (layers 3 and 4) occupancy very low now (≤ 0.5%)

• Inner short strip detector only needs to be considered to calculate trigger rates

• However, ends of short strips have slightly wider clusters and should still determine the overall trigger rate. Will use max 0.9% hit occupancy

Hit Occupancy for Barrel Layers

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L1/R3 Trigger Rate Calculation

• Key numbers to calculation for L1 are the mean number of bits per event per HCC are needed for the HCC in the detector system with the maximum average data

• Similar number is needed for R3

• Additionally, we need to know what event rate is needed for R3. If we assume we want to generate a R3 trigger for every event in L0, and that at most the ROI will point back to geometrically no more than 5% of the detector, than R3 rate = 5% x L0 rate.

• Important question is do we expect ROI will be uniformly distributed?

Then,

L1 elink rate = 200 kHz x N bits/HCC-event

R3 elink rate = 500 kHz x 5% x M bits/HCC-event

Total elink rate = L1 elink rate + R3 elink rate

Note: for barrel 1 HCC corresponds to one hybrid or 10 ABC130 chips

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Calculation of L1 Nbits/HCC-event and R3 Mbits/HCC-event

• These numbers are best generated from proper simulation. They must take into account the ABC130 hit formatting for both types of data

• Here I present an approximate calculation derived from occupancy and cluster widths plots supplied by K. Selbach

1. Use hit occupancy to generate poisson distributed hit distribution (A)

2. Use cluster width distribution (B) for that hybrid (HCC) to generate cluster size probability distribution. Split clusters with width > 4 into two clusters

(A)

(C)

(B)

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Num clusters (W <5) Probability N bits Mean Nbitsnone 0.099858609 0 0.01 to 3 0.640860866 59 37.84-6 0.235279929 118 27.87-9 0.02297636 177 4.1>9 0.001024236 236 0.2

Total 1 69.9

3. Group clusters according ABC130 data format to determine average number of bits/event-HCC

Calculation of L1 Nbits/HCC-event and R3 Mbits/HCC-event

(69.9 bits/event-HCC) corresponds to 1.18 L1 packets)

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L1 Readout Rates

4. Use different hit occupancies to generate N bits/event-HCC (if want to see rates at different luminosities)

5. Use similar approach (but different algorithm) for R3 rates.

Close to M. Warren’s more sophisticated calculation (154 Mb/s)

L0 [kHz] 500 500L1 [kHz] 200 200fraction R3 0.05 0.05m [interactions/bc] 200 150Max barrel occupancy 0.90% 0.68%L1 bits/chip-event 70 57R3 bits/chip-event 49 43L1 e-link rate [Mb/s] 140 114R3 elink rate [Mb/s] 12 11Total elink rate [Mb/s] 152 125

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GBT Issues

Current GBT has three different data packet or “frame formats”.

Most robust (uses Forward Error Code Detection) is “GBT” frame format. Has lowest data bandwidth (detector to daq)

Least robust (i.e. no error code detection) is “wide frame mode”. Has highest data bandwidth (via extra available inputs)

data rate [Mbps] GBT Wide Frame80 40 56

160 20 28320 10 14

Data Format

Number of HCC to GBT inputs available

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GBT Issues

•At 160 Mbps, there are only 20 inputs available in GBT mode. This is ok for long strips (13 inputs needed), but not for short strips (26 inputs needed)

•Potentially outer short strip could be run at 80 Mbps and there are then 40 inputs available (needs closer examination).

• Inner short strip needs either

A. Two GBTs running at 160 Mbps, or

B. One GBT running in wide frame mode at 160 Mbps(28 inputs)

C. An Atlas specific GBT with a few more inputs. However, this GBT would need an increase in the overall serial bandwidth that is currently specified at 4.8 Gb/s

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Conclusions

• The HCC with the highest average occupancy determines maximum L1 Accept Rate.

• Appears we are close to being able to satisfy L1 +R3 rates for barrel. Need to pin down actual pileup vs luminosity.

• GBTWide frame mode needs consideration.

• Data bitsMay be able to save some bandwidth by using only 51 bits for L01_1BC ABC130 packet data (M. Newcomer)

• Petals Need to apply calculations to petals. But first three backup slides show much higher hit occupancies (up to 3.5%) without a corresponding reduction in the number of chips/HCC. This would seem to imply that the petals as geometrically laid out will significantly limit bandwidth

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Backup slides

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News from DESY

Meshing problems solved Failure at 3D-Model surface Change mesh element and size

Now in progress• Drawings for:

• DESY PETAL• Gluing jigs• Supports

• Gluing stand in preparation

• Tool for cooling pipe bending

• In a few months: work shop for composite materials start up

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News from NIKHEF

xy

z

Main change is that we re-routed the cooling pipes to come out at the top of the petal, see drawing. Previously they exited at the ears. Now (invisible in the picture) they make a loop out to theears and back in.

Main reason is to make the petal prototype fit in our cold box; also in the endcap when the pipescome out sideways they make insertion of the petal difficult and risky

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Utopia

Utopia in Athena(simulation) Relative placement

1024

1024

896

896

Nstrips

768

768

768

768

Nstrips

Ring Number

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none 0.000462 0 0.01 to 3 0.050373 59 3.04-6 0.290565 118 34.37-9 0.396838 177 70.210-12 0.20402 236 48.113-15 0.050247 295 14.8>15 0.007496 354 2.7

Total 1 173.1

3% occupancy

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Inner ring endcap bits/asic-event as function of occupancy


Previous slide and this would seem to imply that due to saturation we will often miss the hits of interest for the ROI (unless precision on the level of the width of a chip are sufficient

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Short Strip Barrel Ring 0 (3% occupancy, 6 chips/hcc)

Comparison Barrel and Endcap

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Proposed Upgrade Readout TimelineEv

ent T

ime

Sync

rono

us L

0

Asyn

cron

ous

R3

Asyn

cron

ous

L1

2-6u

S fi

xed

Late

ncy

~50u

S la

test

R3

~500

uS la

test

L1

•L0 Delay Fixed at Initial Setup•R3 Must precede L1•R3 readout highest priority

•L1 initiates Off Detector Readout

Simple Rules for Maximal Flexibility

Non Sequential Readout Requires Self describing Data Blocks

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ATLAS Upgrade week October 2011

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End of Stave (GBT controlled) Signals

L0_ CMD @80Mbps Elink TX1

R3_L1 @80Mbps

Bussed Outputs

Elink RX1

Elink TX2Elink TX3

Elink RX2

Elink RX24

Point to point Data Lines - one per HybridOnly possible with 80Mbps for present GBT technology.

Hybrid 1Hybrid 2

Hybrid 24 ? ??? current GBT design provides only 20 @160Mbps

………

GBT

TX

RX

Vers

atile

Lin

k

Optical LinkTosa Rosa

Note that for a longer stave we would be forced to go to 2 GBT’s per Stave.

Stave_BC (40 MHz Data Clock)

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ABC130 Data Flow

Event Address

Pipeline(SRAM)

L1 buffer (SRAM)

DCLL1

RR

Data Flow Control

BC

WA RA WA RA

At L0: RA=WA-L0Lat

WAgen RAgen

At BC : WA=WA+1

L0 latency (6.4us) L1 latency (up to 256us)

R3W

R3L0ID

R

L0ID

Event AddressL1

W

L1L0ID

R

256 256

DCLR3

25653

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Local FiFO

Local FiFO

Readout

RR

Command DecoderCLK

L0-COM

R3-L1BC

Documents

Strips trigger rate Issues & Can the strips achieve the following proposed trigger parameters