Storage Elements, Busses, Integer Arithmetic

Storage Elements, Busses, Integer Arithmetic

Computer Science 104 Lecture 10

2 © Alvin R. Lebeck CPS 104

•  Homework #3 Assigned •  Project: Groups of 3 (may need a couple 2 member) •  Project Specification(s) on Web, Due April 17 (written

document and demonstration) •  Set meeting with me if you want to discuss your

project (come with an initial plan though)

Admin

3 © Alvin R. Lebeck

Admin

Outline •  Logic for Storage •  Register File •  Busses •  Integer Multiply and Divide Reading

Appendix C.1-C.3, C.5, C.7-C.8, Ch 3 Then on to Chapter 4.

CPS 104


Review: A 1-bit Full Adder

a b Cin Sum Cout 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1

01101100

01101101 +00101100 10011001

a

b

Cin

Cout

Sum


Add/sub

C in

C ou t

Add/sub F

2

0

1

2

3

a

b

Q

A F Q 0 0 a + b 1 0 a - b - 1 NOT b - 2 a OR b - 3 a AND b

Review: The new ALU Slice


Review: Abstraction--The ALU

•  General structure Input •  Two operands •  Control Output •  Result •  Overflow •  Zero

Input A

Input B

ALU Operation

Carry Out

Result Overflow

Zero ALU


Memory Elements

•  All the circuits we looked at so far are combinational circuits: the output is a Boolean function of the inputs.

•  We need circuits that can remember values. (registers)

•  The output of the circuit is a function of the input AND a function of a stored value (state) .

•  Circuits with memory are called sequential circuits.


Set-Reset Latch

R

S

Q

Q

0 1 0

1 0 0

R

S

Q

Q

0 0 1

0 1 0

R S Q 0 0 Q 0 1 1 1 0 0 1 1 -


R

S

Q

Q

0 1 0

1 0 0

R

S

Q

Q

0 0 1

0 1 1

Set-Reset Latch (Continued)

Time

S 0 1

R 0 1

Q 0 1


Data Latch (D Latch)

Data

Enable Q

Q

D E Q 0 1 0 1 1 1 - 0 Q

Time

D 0 1

E 0 1

Q 0 1

Does not affect Output


  On C D is transferred to the first D latch and the second is stable.

  On C the output of the first stage is transferred to the second (output), and the first stage is stable.

  Output changes only on the edge of a clock

D Flip-Flop

D latch

D Q

E

D latch

D Q

E Q Q

Q D

C


Register File

•  Register File = the set of locations for register values  E.g., 32 32-bit registers

•  How do I build a Register File using D Flip-Flops? •  What other components do I need?


Register File

•  Circuit to determine which of 32 registers? •  Circuit to get just the data from one of 32 registers?

CPS 104


D E Q 0 1 0 1 1 1 - 0 Z

Z :- High Impedance

D Q

E

  The Tri-State driver is like a (one directional) switch:   When the Enable is on (E=1) it transfers the input to the output.   When the Enable is off (E=0) it disconnects the output.

D Q

E

Tri-State Driver


  The Bus: Many to many connections.   Mutual exclusion: At most one Enable is on!   Control must ensure this!  Note: Bus sometimes used to denote multiple parallel wires

Bus Connections


Register Cells on a bus

One can “source” and “sink” from any cell on the bus by activating the right controls, IE--input enable, and OE--output enable.

D

E

Q

Q

D latch

IE OE

D

E

Q

Q

D latch

IE OE

D

E

Q

Q

D latch

IE OE

D

E

Q

Q

D latch

IE OE


3-Port Register Cell

Q

Q

D ata-In

D in E nable OutA OutB

Bus-B

Bus-A

Bus-C

Complement Q

•  Stores one bit of a register •  Can Read onto Bus-A & Bus-B and Write from Bus-C Simultaneously


Q

Q

Bus-B

Bus-A

Bus-C

Q

Q

Bus-B

Bus-A

Bus-C

Bit-0

Bit-1

EA EB EC

3-Port Register File


Address Decode Circuit

A0

A1 EA

B0

B1

EB C0

C1 EC

Q

Q

Data-in

OutA OutB DEnable Bus-A

Bus-B Bus-C

Register address: 01


Reg-0 Reg-1 Reg-2 Reg-3

One-bit Cell

One-bit Cell

One-bit Cell

One-bit Cell

One-bit Cell

One-bit Cell

One-bit Cell

One-bit Cell

One-bit Cell

One-bit Cell

One-bit Cell

One-bit Cell

One-bit Cell

One-bit Cell

One-bit Cell

One-bit Cell

A3 B3 C3

A-En Add-A1 Add-A0 B -En Add-B 1 Add-B 0

C -En Add-C 1 Add-C 0

A1 B1 C1

A2 B2 C2

A0 B0 C0

Register File (Four 4-bit Registers)


Quartus Note

•  Logic blocks (MEGA functions) for •  MUX •  Memory block •  ALU (can’t use this one for homework though)

•  Aside  Can create hierarchical designs

» Add pins to input and output of circuit

CPS 104


Digital Logic Summary

•  Given Boolean function, generate a circuit to “realize” the function.

•  Constructed circuits that can add and subtract. •  The ALU: a circuit that can add, subtract, detect

overflow, compare, and do bit-wise operations (AND, OR, NOT)

•  Shifter •  Memory Elements: SR-Latch, D Latch, D Flip-Flop •  Tri-state drivers & Bus Communication vs. MUX •  Register Files •  Control Signals modify what circuit does with inputs

 ALU, Shift, Register Read/Write


Arithmetic

•  Integer Addition---Done •  Integer Multiplication •  Integer Division •  Floating Point Addition •  Floating Point Multiplication


Integer Multiplication

•  Product = Multiplicand x Multiplier

•  Example: 0011ten x 0101ten


Multiplication Algorithm #1

•  From Right-Left:  If multiplier digit = 1: add (shifted) copy of multiplicand to result.  If multiplier digit = 0: add 0 to result.

•  32 steps when multiplier is 32-bit number.

•  Example: 310 x 510 or 00112 x 01012 Product = 000011112



Figure Copyright Morgan Kaufmann


Multiplication Hardware #1

•  Multiplicand starts in right half of register •  MIPS: 64-bit product in Hi & Lo Regs

 Move from Lo (mflo) to get 32-bit product  Move from hi (mfhi) to get upper 32-bits & test for overflow



Multiplication Hardware #2

•  Shift Multiplicand Left ~ Shift Product Right •  Only need 32 bits for multiplicand

•  Possible to combine multiplier and product registers Figure Copyright Morgan Kaufmann





Booth Encoding

•  Observation:  Can write number as difference of two numbers.  In particular: Can replace a string of 1s with initial subtract when we

see a 1, and then an add when we see the bit (which will be a zero) AFTER the last 1

•  Example 1: 710  710 = -110 + 810  01112 = -00012 + 10002

•  Example 2: 11010 = 011011102  11010 = (-210 + 1610) + (-3210 + 12810)  011011102 = (-000000102 + 000100002) + (-001000002 + 100000002)

•  Works for signed numbers as well!


Booth’s Algorithm

•  Similar to previous multiply algorithm.

•  (Current, Previous) bits of Multiplier:  0,0: middle of string of 0s; do nothing  0,1: end of a string of 1s; add multiplicand  1,0; start of string of 1s; subtract multiplicand  1,1: middle of string of 1s; do nothing

•  Shift Product/Multiplier right 1 bit (as before)


Signed Multiplication

•  Convert negative numbers to positive and remember the original signs.

•  In 2s-complement, can multiply directly using Booth’s Algorithm.  Sign extend when shifting.  Try 3 x -5


Compute using Booth’s algorithm

•  11000111 x 01101110 •  (8-bit 2’s complement numbers)

•  Remember leading 1’s for negative numbers, leading 0’s for positive numbers

•  Example: 4- bit 3*-5


Integer Division

•  Dividend = Quotient x Divisor + Remainder •  Example: 1,001,010ten / 1000ten


Division Hardware #1


•  Divisor starts in left half of divisor register •  Remainder initialized to dividend

1.  Subtract divisor from dividend

2.  If result positive - shift in 1 to

Quotient right bit else

- restore value by adding divisor to

Remainder - Shift in 0 t

o Quotient right bit 3.  Shift divisor right 1 bit 4.  If 33rd iteration stop else

goto 1


Division (contd.)

•  Similar to multiplication  Shift remainder left instead of shifting divisor right  Combine quotient register with right half of remainder register  MIPS: Hi contains remainder, Lo contains quotient

•  Signed Division  Remember the signs and negate quotient if different.  Make sign of remainder match the dividend

•  Same hardware can be used for both multiply and divide.  Need 64-bit register that can shift left and right  ALU that adds or subtracts  Optimizations possible


Numbers are represented by:

X = (-1)s × 2E-127 × 1. M

S := 1-bit field ; Sign bit E := 8-bit field; Exponent: Biased integer, 0 ≤ E ≤ 255. M:= 23-bit field; Mantissa: Normalized fraction with

hidden 1 (don’t actually store it)

0 22 30

23-bit 8-bit

Mantissa exp s

Single precision floating point number uses 32-bits for representation

Review: FP Representation

31


Floating Point Representation

•  The mantissa represents a fraction using binary notation: M = . s1, s2, s3 . . . = 1.0 + s1*2-1 + s2*2-2 + s3*2-3 + . . .

•  Example: X = -0.7510 in single precision (-(1/2 + 1/4))

-0.7510 = -0.112 = (-1) x 1.12 x 2-1 = (-1) x 1.12 x 2126-127

S = 1 ; Exp = 12610 = 0111 11102 ; M = 100 0000 0000 0000 0000 00002

1 0111 1110 100 0000 0000 0000 0000 0000 X = 0 22 23 30 31

s E M


FP Addition

•  Example: Assume only 4 digits  1.610 x 10-1 + 9.999 x 101

•  Step 1:  Align decimal point: 0.016 x 101 + 9.999 x 101

•  Step 2:  Add: 10.015 x 101

•  Step 3:  Normalize: 1.0015 x 102

•  Step 4:  Round: 1.002 x 102

•  May need to repeat steps 3 and 4 if result not normal after rounding. (renormalization)


Floating Point Addition

Copyright Morgan Kaufmann


Arithmetic Unit for FP Addition



FP Multiplication

1.  Add biased exponents, subtract bias 2.  Multiply significands 3.  Normalize product 4.  Round significand 5.  Compute sign of product

•  .5 x -.75 => 1.000x2-1 x 1.100x2-2


Example FP Multiply

•  .5 x -.75 => 1.000x2-1 x 1.100x2-1

•  With Bias 1.000x2126 x 1.100x2126

1.  126+126-127 = 125 2.  1.000

1.100 0000 0000 1000 1000 1.100000

3.  Normalize product: 1.1000000x2125 4.  Round: 1.100x2125 5.  Compute Sign: different so result is neg

- 1.100x2125 (biased) = - 1.100x2-2 = -.375


FP Multiplication



Accuracy

•  Is (x+y)+z = x + (y+z)? •  Computer numbers have limited size => limited

precision. •  Rounding Errors

•  Example: 2.56 x 100 + 2.34 x 102, using 3 significant digits

•  Align decimal points (exponents, shift smaller) 2.34 0.0256 2.36


Rounding

•  Rounding with Guard & Round bits •  Example:

2.56 x 100 + 2.34 x 102, using 3 significant digits •  Align decimal points (exponents, shift smaller)

2.34 0.0256 Guard 5, Round 6 2.3656

•  Round: 2.37 x 100 •  Without guard & round bits, result: 2.36 x 100 •  Error of 1 Unit in the least significant position •  Why 2 bits?

 Product could have leading 0, so shift left when normalizing


Arithmetic Exceptions

•  Conditions  Overflow  Underflow  Division by zero

•  Special floating point values  +infinity (e.g. 1/0)  -infinity (e.g. -1/0)  NaN (Not A Number) (e.g. 0/0, infinity/infinity, sq. root of -1)


Computer Arithmetic Summary

•  Integer Multiplication •  Integer Division •  Floating Point Addition •  Floating Point Multiplication •  Accuracy (Guard and Round Bits)

Next •  Review storage elements •  Datapath, Reading Chapter 4…

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Storage Elements, Busses, Integer Arithmetic