Storage and User Interface for Digital Turntable - amoBBSd1.amobbs.com/bbs_upload782111/files_6/armok01133277.pdf · Storage and User Interface For Digital Turntable Submitted for

Storage and User Interface For Digital Turntable

Submitted for the degree of

Bachelor of Engineering (Electrical) (Honours)

By William Wong

Department of Information Technology and Electrical Engineering,

The University of Queensland

October 2003 ©

2003 Thesis Report - Storage and User Interface for Digital Turntable

William Wong ii

29 October 2003

Head of School

Information Technology and Electrical Engineering

The University of Queensland

St Lucia, QLD 4072

Dear Professor Kaplan

In accordance with the requirements of the degree of Bachelor of Engineering (Honours) in

the division of Electrical Engineering, I present the following thesis entitled “Storage and

User Interface for Digital Turntable”. This work was performed under the supervision of

Dr Peter Sutton, and is related to another thesis project entitled “The Digital Turntable” by

another student, Mr Garth Williams.

I declare that the work submitted for this thesis is my own, except as acknowledged in the

text and footnotes, and has not been previously submitted for a degree at the University of

Queensland or any other institution.

Yours sincerely

William Wong


William Wong iii

ACKNOWLEDGEMENTS

I would like to take this opportunity to thank the following people for their support and

assistance throughout my thesis work this year.

Dr Peter Sutton for his supervisory role, guidance and patience

Garth Williams for his friendship and the opportunity of working on this fun project

Keith Bell for his guidance and help on the PCB construction, while keeping the electronic

workshop, a safe and friendly environment

Michael Woo for helping me troubleshoot and debug the Atmel AVR when it stopped

functioning.

Fellow students at the thesis laboratory (Axon building room 401) for their companies,

support and humour during my stay at the labs

My family and God for guiding me through every step during the marathon course of my

university study.


William Wong iv

ABSTRACT

Vinyl turntables are popular and essential equipment used by professional disc jockeys (DJs)

due to their versatility in music playback. These turntables allow music to be played at

variable speed, while its rotating platter provides the most intimate control in any part of the

music. It is these two main functions that allow DJs to scratch and beat-mix different tracks

together to create their own unique sound.

However, the disadvantage of using such device is the fact that music must be recorded on

vinyls. As our modern society emphasise on digital technologies, it is apparent that most

music are produced and stored in digital form, namely in data file formats such as WAV,

MP3 and WMA. Hence, the focus on future development of turntables is pointing towards

this direction.

What if a turntable system can be engineered to allow DJs the vinyl way of scratching digital

audio files? This thesis in conjunction with another thesis entitled “The Digital Turntable” by

another student, Mr Garth Williams are set out to investigate, design, and implement such a

system. This grand project was divided into two separate theses with Mr Garth Williams

handling the turntable and music playback department, while the author is in charge of the

storage management of audio files and its user interface. For the turntable and signal

processing part of the project, please refer to Mr Garth Williams’ thesis.

The final product achieved the following:

1. Audio file extraction from HDD

2. Maintain user display of the file system on HDD

3. Provide file system navigation of the HDD

It was unfortunate that the two theses defined above could not be integrated into one project.

However, the final product can be further developed in the future to implement this. Other

possible development includes the interface with other storage sources such as serial ATA

devices, CD/CD-R/CD-RW discs, compact flash cards, and USB flash drives.


William Wong v

TABLE OF CONTENTS LIST OF FIGURES ...............................................................................................................vii LIST OF TABLES................................................................................................................viii LIST OF ABBREVIATIONS.................................................................................................ix DJ TERMINOLOGY................................................................................................................x 1.0 INTRODUCTION ..............................................................................................................1

1.1 Turntablism .................................................................................................................. 1 1.2 The Problem................................................................................................................. 2

1.2.1 Storage Medium for Turntables ..................................................................................... 2 1.3 Solution........................................................................................................................ 3

1.3.1 Coverage ..................................................................................................................... 3 1.3.2 Goals........................................................................................................................... 4

1.4 Actual Solution ............................................................................................................. 4 1.5 Thesis Structure ........................................................................................................... 5

2.0 PREVIOUS WORK ..........................................................................................................7

2.1 Keeping a “vinyl feel” on Digital Turntables .................................................................... 7 2.2 Similar Products .......................................................................................................... 7 2.3 CD Turntables ............................................................................................................. 8

2.3.1 Pioneer CDJ Series ...................................................................................................... 8 2.4 Stanton Final Scratch................................................................................................... 8 2.5 Digital Turntables ......................................................................................................... 9

2.5.1 Denon SN-S5000 ......................................................................................................... 9 2.5.2 Pioneer DMP-555 ......................................................................................................... 9 2.5.3 Numark CDX ................................................................................................................ 9 2.5.4 Technics SL-DZ1200.................................................................................................. 10

2.6 Comparison............................................................................................................... 10 2.7 Summary .................................................................................................................. 11

3.0 PRODUCT SPECIFICATIONS ................................................................................... 13

3.1 Subsystems ............................................................................................................... 13 3.2 Final Product .............................................................................................................. 13 3.3 Functional Definition ................................................................................................... 14 3.3 Storage...................................................................................................................... 14

3.3.1 Storage Medium ......................................................................................................... 14 3.3.2 File Formats............................................................................................................... 14 3.3.3 Data Transfer Rate..................................................................................................... 15 3.3.4 File System Management ........................................................................................... 15

3.4 User Interface............................................................................................................. 15 3.4.1 User Display .............................................................................................................. 15 3.4.2 User Control............................................................................................................... 15

3.5 Controller ................................................................................................................... 16 3.5.1 Memory ..................................................................................................................... 16 3.5.2 Speed........................................................................................................................ 16 3.5.3 I/O Ports .................................................................................................................... 17

3.6 Project Integration with Mr Garth Williams’ System ....................................................... 18 3.7 Firmware.................................................................................................................... 18

3.7.1 Functions ................................................................................................................... 18 3.7.2 Language .................................................................................................................. 19

4.0 HARDWARE IMPLEMENTATION ............................................................................. 21

4.1 Plan ................................................................................................................................. 21 4.2 Controller.......................................................................................................................... 21

4.2.1 Component Decision .................................................................................................. 21 4.2.2 Programming Interface ............................................................................................... 23


William Wong vi

4.2.3 Voltage Supervisory ................................................................................................... 23 4.2.4 RS232 Terminal ......................................................................................................... 24 4.2.4 External Memory ........................................................................................................ 25

4.3 Storage ............................................................................................................................ 26 4.3.1 ATA/IDE Interface ...................................................................................................... 26 4.3.2 File System Management ........................................................................................... 28

4.4 User Interface ................................................................................................................... 29 4.4.1 User Display .............................................................................................................. 29 4.4.2 User Control............................................................................................................... 30

4.5 Project Integration with Mr Garth Williams........................................................................... 31 4.6 Overall System Design ...................................................................................................... 31 4.7 PCB Design and Manufacture............................................................................................ 32 4.8 PCB Soldering and Testing ................................................................................................ 32 4.9 Product Enclosure ............................................................................................................. 33

5.0 FIRMWARE IMPLEMENTATION............................................................................... 35

5.1 Development Software ...................................................................................................... 35 5.2 Early Developments .......................................................................................................... 35 5.3 User Interface ................................................................................................................... 36

5.3.1 User Display .............................................................................................................. 36 5.3.2 User Control............................................................................................................... 36

5.4 HDD Interface................................................................................................................... 37 5.5 FAT32 File System............................................................................................................ 38

6.0 PRODUCT EVALUATION........................................................................................... 40

6.1 File System Limitations ...................................................................................................... 40 6.2 Remote Storage Access .................................................................................................... 40 6.3 Personal Reflections ......................................................................................................... 41

7.0 FUTURE DEVELOPMENTS ....................................................................................... 43 8.0 CONCLUSION............................................................................................................... 45 9.0 APPENDICES................................................................................................................ 47

Appendix A: ATmega128 Microcontroller .................................................................................. 47 Appendix B: AS7C31026A SRAM ............................................................................................ 48 Appendix C: Full Hardware Schematic ..................................................................................... 49 Appendix D: PCB (Protel View)................................................................................................ 50 Appendix E: PCB (3D View) .................................................................................................... 51 Appendix F: PCB Soldering ..................................................................................................... 52 Appendix G: Photos of the Final Product .................................................................................. 53

Appendix G.1 Top view without cover................................................................................... 53 Appendix G.2 Front view ..................................................................................................... 53 Appendix G.3 Rear view...................................................................................................... 54 Appendix G.4 The LCD user display with LED backlight on ................................................... 54

Appendix H: Firmware (thesis.h) .............................................................................................. 55 Appendix I: Firmware (thesis15.c)............................................................................................ 59 Appendix J: Firmware (ide.h)................................................................................................... 69 Appendix K: Firmware (ide.c)................................................................................................... 71 Appendix K: Firmware (ide.c)................................................................................................... 71 Appendix L1: Firmware (keypad.h)........................................................................................... 77 Appendix L2: Firmware (keypad.c)........................................................................................... 77

10.0 REFERENCES............................................................................................................ 79

Bibliography ........................................................................................................................... 80


William Wong vii

LIST OF FIGURES Figure 1-1: A typical DJ system setup ___________________________________________1

Figure 1-2: Project divided into 2 theses _________________________________________3

Figure 2-1: Pioneer CDJ-1000 _________________________________________________8

Figure 2-2: Stanton Final Scratch _______________________________________________8

Figure 2-3: Denon SN-S5000 __________________________________________________9

Figure 2-4: Pioneer DMP-555 _________________________________________________9

Figure 2-5: Numark CDX _____________________________________________________9

Figure 2-6: Technics SL-DZ1200______________________________________________10

Figure 3-1: Project subsystems ________________________________________________13

Figure 3-2: CompactFLASH card______________________________________________14

Figure 3-3: Controller memory________________________________________________16

Figure 4-1: ATmega128 pin-outs ______________________________________________22

Figure 4-2: STK200 programming header _______________________________________23

Figure 4-3: ATmega128 voltage supervisory circuit _______________________________24

Figure 4-4: ATmega128 RS232 terminal ________________________________________24

Figure 4-5: External memory _________________________________________________26

Figure 4-6: HDD control pins _________________________________________________28

Figure 4-7: HDD data bus____________________________________________________28

Figure 4-8: User display _____________________________________________________29

Figure 4-9: User control _____________________________________________________30

Figure 4-10: Integration with Mr Garth Williams' System___________________________31

Figure 6-1: USB remote storage detection _______________________________________41


William Wong viii

LIST OF TABLES

Table 1-1: Typical maximum minutes of audio stored on various mediums ______________2

Table 2-1: Market comparison ________________________________________________10

Table 3-1: Approximate total of I/O pins for controller _____________________________17

Table 4-1: 40-pin IDE connector signals ________________________________________27

Table 4-2: HDD register selections_____________________________________________27

Table 4-3: Maximum current consumption of overall design ________________________31

Table 5-1: Firmware version control ___________________________________________35


William Wong ix

LIST OF ABBREVIATIONS

ASCII American Standard Code for Information Exchange

ATA Advanced Technology Attachment

FAT32 32-bits File Allocation Table file system

IDE Integrated Drive Electronics

CD Compact disc

DJ Disc jockey

DMA Direct memory access

GND Ground

HDD Hard disk drive

I/O Input/Output

KB/s Kilo-bytes (thousand bytes) per second

Kbps Kilo-bits (thousand bits) per second

LCD Liquid crystal display

mA milli-Amperes

MB Mega-bytes (million bytes)

MHz Mega-hertz

MIPS Million instructions per cycle

MPEG Moving Picture Experts Group

MP3 MPEG Audio Layer-3 file format

PCB Printed circuit board

PCM Pulse code modulation

SD Secure Digital

SPI Serial-parallel interface

UDMA Ultra DMA

USART Universal Synchronous/Asynchronous Receiver/Transmitter

UQ The University of Queensland

WAV Wave PCM file format

WMA Windows Media Audio file format


William Wong x

DJ TERMINOLOGY

Beat-mix or beat-mixing

The beats per minutes on a track are matched and mixed with other track/s to

so that the beats on each track is synchronised with each other to create music

harmony.

Cue or cueing

A track is paused at a desired position waiting for the right time to resume

playing. This is usually the method used for cross-fading one track onto the

next track.

Cross-fade or cross-fading

A track is slowly muted while another track that was muted is played on top of

the old track with increasing volume.

Scratch or scratching

While a vinyl is playing on a turntable, a hand is placed on top of the vinyl to

alter the position of a track when the platter is slid forward or backwards. This

creates a unique “scratching” sound which can be used to add special effects

to their music. This is also a technique used for beat-mixing whereby the

beats of a track is synchronous with other tracks.

CHAPTER 1:

Introduction


William Wong 1

1.0 INTRODUCTION

Before describing the problem area, a brief explanation on the use of turntables by DJs must

be understood.

1.1 Turntablism

Vinyl turntables are the most important equipment used by professional DJs due to the

intimate playback control over any section of the music recorded on vinyl. A vinyl can be

played at variable speed by adjusting the pitch control slider (located on the bottom right

corner of the turntable), which changes the speed of the motor driving the platter of the

turntable.

In addition, music can be scratched or cued by placing a hand on top of the vinyl to directly

control the position of the track when the platter is slid forward and backward. These two

main methods allow a DJ to beat-mix different tracks on top of each other to create their own

style of music, while ensuring the music flow in harmony with no pauses during a live

performance. Tracks are mixed into one channel using an audio channel mixer. Figure 1-1

showcases a typical DJ sys tem setup with an audio mixer in between two vinyl turntables.

Figure 1-1: A typical DJ system setup


William Wong 2

1.2 The Problem

Now that you have an idea on the use of vinyl turntables, you must be wondering what the

problem is. The simple answer is that music must be recorded on vinyl records, an analogue

medium. As we are living in a modern innovative world, the majority of music produced are

recorded in digital form, namely on audio CDs or encoded in audio data formats such as

WAV, MP3 and WMA.

With that in mind, turntable manufacturers have focused their attention towards digital design.

Pioneer was one of the first companies to produce CD turntables, the CDJ series [1]. It was a

huge success with many new DJs plying their trade in the art of CD turntable scratching due

to the fact that a lot of people have their music collection on audio CDs, and almost all music

produced today are recorded on CDs. However, these CD turntables are not picture perfect,

and have their limitations as described below.

1.2.1 Storage Medium for Turntables

A typical audio CD can store around 80 minutes worth of music, and although this is

significantly better than what a vinyl record can store, it is quite insignificant when compared

with a CD filled with compressed audio file formats like MP3, or even a larger storage

medium like the HDD. A typical MP3 file (encoded to near CD quality of 128Kbps bit rate)

requires 1MB to represent a minute of audio data, while a typical CD can hold a maximum of

700MB of data. Hence, a CD filled with MP3 files contains approximately 700 minutes of

audio, which is more than 8 times the amount of audio stored in an audio CD. For even

better capacity, a typical 10GB HDD filled with MP3 files can store approximately 5,500

minutes of audio. Table 1 compares the storage medium and the file format stored in them.

Storage medium

File format Typical maximum minutes of audio stored (mins)

Vinyl N/A 20 – 30 CD CD audio 80 CD MP3 700

10GB HDD WAVE 1000 10GB HDD MP3 5500

Table 1-1: Typical maximum minutes of audio stored on various mediums


William Wong 3

1.3 Solution

The solution to the storage restriction dilemma in CD turntables is to develop a digital

turntable system capable of playing most popular audio file formats from a large capacity

storage medium. The target audience range from amateur DJs to music producers and even

professional DJs if the product functions well.

The initial aim of the project is to scratch digital WAV files in the vinyl way. The project can

later be extended to allow scratching of compressed audio like MP3. The reason for this

approach is to minimise the complexity that compressed audio data can add to the project

(like MP3 decoding and timing issues associated with it).

1.3.1 Coverage

Due to the magnitude of this project, it was divided into two separate theses with Mr Garth

Williams handling the turntable and music playback department, while the author is in charge

of the storage management of audio files and its user interface, as illustrated in Figure 1-2.

Please refer to Mr Garth Williams’ thesis for the turntable and music playback design.

Figure 1-2: Project divided into 2 theses

Storage and User Interface for Digital Turntable

By William Wong The Digital Turntable By Garth Williams


William Wong 4

1.3.2 Goals

The goals of this thesis are defined below:

4. Extract and buffer aud io data from the storage medium

5. Maintain user display of the file system on storage medium

6. Provide file system navigation of the storage medium

Other goals when implemented with Mr Garth Williams’ system:

1. Stream the retrieved audio data across to Mr Garth Williams’ turntable system for

signal processing and sound playback

2. Communication with Garth Williams’ turntable system

1.4 Actual Solution

The storage medium chosen for this project was the HDD. Reasons for this are detailed in

Chapter 3.3 in Project Specifications. A spare HDD was obtained from Mr Garth Williams

for implement ing this thesis.

It was unfortunate that we did not get the chance to integrate our two theses together into one

project. The reasons for this were:

• Not enough time was leftover near the end of thesis for integrating the two theses.

It was decided that the remaining time was better spent on improving our own thesis.

• Mr Garth Williams had been feeding in live stream of audio CD data as the music

source for conducting his thesis work, and it would have taken considerable time to

integrate this thesis as his music source. There was also a risk of jeopardising each

thesis.

Therefore to demonstrate the final working product, this thesis will extract the audio files of

the user’s choice and output the data to an external PC via the serial USART interface. The

retrieved data will be captured and saved back to its audio file format for music playback.


William Wong 5

1.5 Thesis Structure

This section summarises the structure of this thesis

• This chapter as discussed before describes the problem area and its solution. Some

goals of the thesis were defined.

• Chapter 2 reviews previous work conducted, including the comparison of similar

products that are currently available to the DJ market.

• Chapter 3 derives the design specifications of the thesis which characterises the final

product and what the thesis aim to complete.

• The engineering process involved in the implementation stage in terms of hardware

and firmware are detailed in Chapter 4 and 5 respectively.

• Chapter 6 evaluates the final product against the specifications set out in Chapter 3.

The author performance was also examined.

• The future developments and improvements of the project were noted in Chapter 7.

• To conclude this thesis, Chapter 8 takes an overview of the project.

CHAPTER 2:

Previous Work


William Wong 7

2.0 PREVIOUS WORK

This chapter will describe some similar products to the thesis that are available to the DJ

market. Before we begin, an important characteristic of a turntable is noted in Chapter 2.1.

2.1 Keeping a “vinyl feel” on Digital Turntables

Some vinyl DJs have criticised the CD turntables for the use of a jog wheel to emulate the

feel of vinyl turntable scratching. The jog wheel (illustrated on the Pioneer CDJ-1000 in

Figure 2-1) is a touch sensitive dial that performs the exact functions of a vinyl turntable

when scratched, with the exception that it does not rotate when music are played, unlike the

platter of a vinyl turntable.

The critics claimed using such devices will loose the feel of scratching music the old vinyl

way. This is especially true for professional DJs who have been lifelong vinyl users. Hence,

the turntable platter is a crucial design criterion of a digital turntable, to ensure there is no

compromise for professional DJs when it comes to working with digital audio, while also

desiring the feel of vinyl turntable scratching.

2.2 Similar Products

Before starting this thesis work in March 2003, there were only two recognisable types of

digital turntables: CD turntables, and Stanton’s Final Scratch. These products are further

described in Chapter 2.3 and 2.4.

However by the middle of this year, news of standalone digital turntable systems that can

play audio CD as well as MP3 has surfaced. The reviews of these new turntables are

described later in Chapter 2.5.

Comparison between these digital turntables is summarised in Table 2-1 on Chapter 2.5.


William Wong 8

2.3 CD Turntables

2.3.1 Pioneer CDJ Series

The first serious attempt at bringing vinyl

control to a digital turntable was the Pioneer

CDJ turntable series [1]. When released in

2001 [2], it sent shockwaves around the world

as only before, the thought of scratching on a

CD deck was thought to be an impossible task.

The Pioneer CDJ-1000 became the industry

standard for this CD category, with many top

nightclubs and DJs purchasing this innovation.

However there are a few downsides to this

product as described earlier in Chapter 1.2 and

Chapter 2.1; scratching audio CDs only, while

using a jog wheel had limited this device.

Figure 2-1: Pioneer CDJ-1000

2.4 Stanton Final Scratch

Final Scratch [3] developed by Stanton takes a

different approach in scratching digital audio.

It utilises existing vinyl turntables to scratch

audio files stored on a PC. Timing information

recorded on vinyls were created for playback

on the turntables, in which the Final Scratch

product (pictured in Figure 2-2) process and in

turn, control the playback of the selected audio

file according to the vinyl’s timing information.

Audio file formats supported are audio CD,

WAV, AIFF, and MP3.

Figure 2-2: Stanton Final Scratch

As can be seen, there is no longer a compromise for professional DJs when using Final

Scratch because the music is still controlled by vinyl turntables.


William Wong 9

2.5 Digital Turntables

2.5.1 Denon SN-S5000

The Denon SN-S5000 [4] is the world's first digital

turntable that incorporates a motor driven active

platter to emulate the platter of a vinyl turntable.

Playback is from CDs with the format audio CD and

MP3 supported. The disadvantages of this product

are the smaller rotating platter design than its 12”

vinyl counterpart, and the limitation on playback

from CDs only.

Figure 2-3: Denon SN-S5000

2.5.2 Pioneer DMP-555

Pioneer’s solution in manufacturing a digital turntable

with MP3 capability is the DMP-555 [5]. Playback from

both CD and SD card are supported. The SD card is a

new removable digital media about the size of a postage

stamp and come in sizes up to 64MB [6].

A jog wheel similar to its CDJ series was once again

utilised to emulate the feel of vinyl scratching. This could

deter vinyl DJs from using this product.

Figure 2-4: Pioneer DMP-555

2.5.3 Numark CDX

Details of this turntable were announced back in July

and should be on sale near the end of the year [7]. The

Numark CDX has most of the features that a vinyl DJ

craves for in a digital turntable. It is a tabletop MP3

compatible CD player with an ultra-high torque

motorized 12” platter that holds an actual vinyl record

for the ultimate in vinyl scratch feel.

Figure 2-5: Numark CDX


William Wong 10

2.5.4 Technics SL-DZ1200

This product was only announced recently

and could be the dream digital turntable that

could signal the end of vinyl scratching.

The Technics SL-DZ1200 [8] is designed

from its SL-1200 vinyl turntable and plays

audio CD as well as MP3 formats stored on

CD and SD card. The real weighted platter

is of exact design from its vinyl cousin, and

hence should give the ultimate vinyl feel as

of the SL-1200 vinyl turntable. Technics

have obviously thought hard in converting

vinyl DJs into the digital world.

Figure 2-6: Technics SL-DZ1200

2.6 Comparison

All products are compared in Table 2-1 below.

Products Medium File format

Turntable platter

Cost Advantages Disadvantages

Pioneer CDJ-1000

CD Audio CD Jog wheel US$ 1000

Industry standard for CD turntable

Limited to playback from audio CD only, jog wheel for platter emulation

Stanton Final Scratch

HDD on PC

Most audio formats

Uses existing vinyl turntables

US$ 700

Support most audio formats, vinyl turntables for scratching

Requires PC and existing vinyl turntables

Denon SN-S5000

CD Audio CD, MP3

7”motor driven platter

US$ 1200

MP3 capability, motor driven platter

Limited to playback from CD, platter size not standard vinyl 12” , high cost

Pioneer DMP-555

CD, SD card

Audio CD, MP3

Jog wheel US$ 1100

MP3 capability, playback from 2 mediums

Jog wheel for platter simulation

Numark CDX

CD Audio CD, MP3

12”motor driven platter

Awaiting release

MP3 capability, motor driven platter

Limited to playback from CD, high cost expected

Technics SL-DZ1200

CD, SD card

Audio CD, MP3

Platter from vinyl cousin SL-1200

Awaiting release

MP3 capability, playback from 2 mediums, platter is same design of SL-1200

High cost expected

Table 2-1: Market comparison


William Wong 11

2.7 Summary

From Table 2-1, it can be seen that plain CD turntables like the Pioneer CDJ-1000 is limited

to playing from audio CD while lacking the vinyl feel of scratching. The Final Scratch by

Stanton is not designed as a stand alone digital turntable system, requiring a PC and existing

vinyl turntables.

The digital turntables by Denon, Pioneer, Numark, and Technics are capable of MP3

playback but are costly in price. The Denon and Pioneer digital turntables lacks the real vinyl

scratch feel while the Numark and Technics have not yet been released.

In addition, although a lot of music can be stored in one CD, it is insignificant when

compared with a high capacity storage device like the HDD.

CHAPTER 3:

Product Specifications


William Wong 13

3.0 PRODUCT SPECIFICATIONS

3.1 Subsystems

Embarking on a project like this is easier managed when broken down into subsystems,

which can be further divided into smaller sections if necessary. The subsystems can be

recognised as:

1. Storage

2. User Interface

3. Controller

4. Data Output and Communication with Mr Garth Williams’ system

5. Firmware

Figure 3-1 illustrates the relationship between the subsystems.

Figure 3-1: Project subsystems

3.2 Final Product

The project is aimed to be implemented as a polished product with all subsystems integrated

onto once PCB covered enclosed by a professional casing. This casing should be robust,

while providing friendly access to user interface. The size of the casing should be large

enough to accommodate for a standard HDD size, while allowing easy fastening and removal

of the HDD to the casing.

Controller

User Interface

StorageFirmware

Project Integration withMr Garth Williams' thesis


William Wong 14

3.3 Functional Definition

The minimum functionality of the user interface is for the HDD file system to be navigated

using user control buttons, while the information is presented on the user display. Some

playback functions might be needed to trigger the extraction of audio data if the project is not

integrated with Mr Garth Williams’ system

3.3 Storage

3.3.1 Storage Medium As described in Chapter 1.2 and compared with the products in Chapter 2, digital turntables

played from CD is limited to the capacity of a CD being 700MB. Storages with larger

capacities than CD includes:

• HDD

• CompactFLASH card

• USB flash drive

Figure 3-2: CompactFLASH card

CompactFLASH cards and USB flash drives with capacities greater than CDs are very

expensive costing in excess of $500, whereas the HDD come in capacities greater than 40GB

that costs less than $200. This is the reason why the HDD is the undoubted choice for

storage in this thesis. For HDD interfacing, the ATA/IDE-3 standard will be followed.

ATA/IDE-4 or higher standard utilises UDMA for file transfers which are designed for PC

interface.

3.3.2 File Formats

Since the choice of storage is a HDD, audio CD formats is no longer possible. However with

many people encoding audio CDs into MP3 formats, due to the 80 minutes audio limit on

audio CDs, audio CDs for music collection is on the decline.

Initially the project aims to extract WAV file format from the HDD as it requires no audio

decoding for playback. However, if the product is not integrated with Mr Garth Williams’

system), the project should be easily extended to extract compressed audio formats like MP3

and WMA. This is because the extracted data are sent to the PC via USART for capture

before playback, hence allowing the product can be easily be programmed to extract data

from any file extensions – in this case: MP3 and WMA.


William Wong 15

3.3.3 Data Transfer Rate

When dealing with WAV, the data transfer rate of the HDD must be high enough so that no

latency results when each sample is extracted. The following calculations can be made on a

typical CD-quality WAV file:

• Sampling rate at 44,100Hz per channel

• For stereo mode (dual channel – left and right), the rate is 88200 samples per seconds.

• Each sample is represented by 16 bits which is equivalent to 2 bytes.

• Bytes per second rate = 400,176288200 =×

Therefore the transfer rate of the hard drive must be greater than 176.4KB/s for WAV files.

The maximum data rate for MP3 is 320Kbps which is equivalent to 40KB/s. If the HDD can

transfer greater than the rate of WAV files, than it is definitely capable of MP3 files encoded

with its maximum rate.

3.3.4 File System Management

The file system of the HDD should be compatible with most PC platforms, which is why the

FAT32 file system was chosen due to its versatility with most Microsoft operation systems –

Windows 95/98/NT/XP. A method is needed for the remote management of the HDD, so

that audio files can be easily transferred without removal and connection with the user’s PC.

The method chosen should have a high transfer rate and a simple interface with standard PCs.

3.4 User Interface

The user interface can be subdivided into two parts – user display, user control.

3.4.1 User Display

The user display should be of reasonable size to allow the display of track information, and

folder/file names of the HDD file system. The display should also be visible in dark

environments, for example in a nightclub so that the DJ can see what he or she is doing.

3.4.2 User Control

The basic requirement of the user control is to allow easy file system navigation of the HDD.

Playback functions like play, stop, pause, fast forward, and rewind will not be needed if the

project is integrated with Mr Garth Williams’ thesis, because these controls are part of his

system.


William Wong 16

The user control should consist of buttons that are easily controlled, and are placed near the

user display to keep both user interfaces intact.

3.5 Controller

The controller can be thought of as the brain of the project which executes the firmware

program developed for the system. It will control the extraction and buffering of audio data

from the HDD while maintaining the user interface, and communication with Mr Garth

Williams’ system. It should also relinquish full access of the HDD when the remote storage

interface is detected with the user’s PC for file uploading to the HDD.

With the extraction and buffering of audio data from the HDD the main focal point of the

controller, the speed and memory size of the controller is a crucial factor.

3.5.1 Memory

The memory should be big enough to allow the storage of at least a few seconds of audio data,

in addition of storing some FAT32 file system data. With MP3 data, the maximum bit rate is

320Kbps, which works out to 960K bits for 3 seconds of data. Add to that, the space to fill a

cluster of FAT32 data (1 cluster = 8 sectors = 8 x 512 bytes = 8 x 512 x 8 bits = 32,768 bits),

the total memory size should be a minimum of 1 megabits (refer to Figure 3-3 for the

controller memory illustration).

Because the memory of microcontrollers is relatively small, an external memory system

might need to be added to extend the controller’s memory capacity.

Figure 3-3: Controller memory

3.5.2 Speed

In deciding a suitable speed for the controller, no definite criteria can be set. Obviously, the

faster the controller, the better as it means more instructions can be executed at the same time.

However, there is a trade off for speed increase, namely higher cost and power consumption.

1Mbits+

Store FAT32

info

Audio data buffer


William Wong 17

A balance should be reached in choosing a fast controller while keeping cost and power

consumption down.

3.5.3 I/O Ports

The controller should have enough I/O pins to service all subsystems of the project. Several

pins must also be interrupt-table for the detection user control, remote storage access, and

communication with Mr Garth Williams’ system. Because the HDD uses 16-bits as its data

word transfer, 16 I/O pins will be allocated to the controller as the 16-bit data bus for the data

transfer of the HDD, external memory and to Mr Garth Williams’ system. Table 3-1

summarises the approximate I/O pins needed by each subsystem excluding the data bus.

Subsystems I/O pins HDD 8

External memory 3 User interface 14

Communication with Mr Garth Williams’ System

6

TOTAL 31

Table 3-1: Approximate total of I/O pins for controller

The HDD IDE/ATA interface requires a total of 8 I/O pins for signal control, with 5 pins

used for addressing, 2 pins for read/write strobe signal, and 1 pin required for HDD reset.

For the external memory, 3 additional I/O pins are needed if the data bus is also used for

addressing the memory with the help of latches. 2 pins are required for the memory

read/write strobe while 1 pin will signal an address latch.

The user interface should require approximately 14 pins, with the user display occupying 8

pins in view of interfacing with a standard LCD display, while the user control takes up 6

pins to accommodate for a 3x3 matrix buttons design.

The communication with Mr Garth Williams’ system will require 2 I/O pins for the serial

USART interface and approximately 2 to 4 more I/O pins for handshaking. More details for

this subsystem are given in Chapter 3.6.


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3.6 Project Integration with Mr Garth Williams’ System

The buffered audio data is sent across to Mr Garth Williams’ system via the 16-bit data bus,

Communication between both systems is maintained via the serial USART interface, while a

few interrupt handshaking pins are also be needed on both systems to signal and coordinate

each word transfer.

The USART communication will be used to trigger events and inform the opposite system its

current state. For example, this system will need to inform Mr Garth Williams’ system if the

user changes the track for playback. In this case, a byte sent to his system via the USART

communication can be filled with a protocol message designating this event to interrupt his

system.

3.7 Firmware

The firmware is the program written to the controller for execution. It will orchestrate all

hardware connected to the controller including the HDD storage medium, user display, and

user control.

3.7.1 Functions

The main functions of the firmware and controller are:

• Manipulate through the file system of the HDD

• Extract and buffer audio data from the HDD

• Display the current file/folder name being scrolled

• Detect user control and implement the designated action

• Send the buffered data to Mr Garth Williams’ system with the help of handshaking

signals

• Serial USART Communication with Mr Garth Williams’ system

• Detection of remote storage interface and relinquish HDD

With most tasks occurring concurrently or close to each other, the speed of the controller and

along with timing issues of the firmware must be heavily considered.


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3.7.2 Language

The C programming language chosen by the author is C, with a minimum use on assembly.

The reasons for this are:

• Efficient C compilers available for most microcontrollers

• Most embedded systems are programmed in C

• The magnitude of the firmware is better suited for C than assembly

• The author’s familiarity with C in embedded programming

CHAPTER 4:

Hardware Implementation


William Wong 21

4.0 HARDWARE IMPLEMENTATION

4.1 Plan

The following plan was carried out for implementing the hardware phase of the project:

1. Subsystems design (Chapter 4.1 to Chapter 4.4)

2. Overall system design (Chapter 4.5)

3. Purchase components

4. PCB design and manufacture

5. PCB soldering and testing

6. Final product enclosure

4.2 Controller

4.2.1 Component Decision

Microchip’s PIC microcontrollers were briefly considered for the controller choice due to the

author’s familiarity with its PIC16F87x series and already an owner of its programmer.

However, with the top of the range microcontroller for the PIC16 family [9], the PIC16F877

has only 368 bytes of internal memory available and this is hardly enough for dealing with

16-bits HDD data transfer and stack sizes for the firmware.

With the higher PIC18 series family, the memory size of these microcontrollers improved.

However, a new programmer was needed to program this family of microcontrollers as UQ

does not own one. To purchase a programmer just to program a specific series of

microcontrollers was considered not feasible.

With Atmel AVR development kits and resources available by UQ [10], the Atmel AVR

microcontrollers were investigated for its suitability for the controller of this project. It was

found that most Atmel AVR microcontrollers have higher speed and memory sizes than its

PIC16 series counterparts, while keeping the cost approximately the same.


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The ATmega128 microcontroller [11] is the top of the range microcontroller from its AVR 8-

bit family. It contains 4KB of internal SRAM with up to 16MIPS throughput when clocked

at 16MHz. It also provides a giant 128KB of reprogrammable flash memory and 53

programmable I/O pins configured in 7 ports. With so many features, this controller is

cheaply priced at A$29 from Polykom [12].

Figure 4-1: ATmega128 pin-outs

Using this microcontroller, the controller specifications made in Chapter 3.5 are easily

satisfied. Hence, this controller was chosen to form the basis of the entire project. The TQFP

package version with +5V operating voltage and 0-16MHz speed grade was purchased.

Appendix A contains the first page datasheet of the ATmega128.

As can be seen in Figure 4-1, the schematic design of the ATmega128 is very flexible with

turned-pin connectors joined to all I/O lines. This will allow easier debugging of I/O lines,

while also realizing into a personal development board.


William Wong 23

4.2.2 Programming Interface

The simplest way to program the ATmega128 is by using the SPI interface for In-system

programming which requires the following connections: RESET for holding in reset state,

MOSI for serial-data in, MISO for serial-data out, and SCK for serial clock. However for the

ATmega128, the MOSI/MISO pins for the programming interface are not mapped to those

signals but rather, the PE0(RXD0)/PE1(TXD0) signals.

The STK200 programming dongles constructed by the laboratory supervisor, Mr Len Payne

[13], were available at the thesis lab which allows the programming of Atmel AVR

microcontrollers when the STK200 dongle is connected from the parallel port of a PC to the

standard STK200 header on the system. The dongle requires a +5V supply from the system

for powering a buffer chip. The schematic of the 10 pins programming header is illustrated

in Figure 4-2.

Figure 4-2: STK200 programming header

4.2.3 Voltage Supervisory

A voltage supervisory circuit used by the school’s AVR8515 Project Board [13] was

implemented for holding the ATmega128 in reset state until the +5V supply have reached

above 4.6V. This avoids the microcontroller from triggering a false start if the +5V line is

not above the logic high threshold.


William Wong 24

Figure 4-3: ATmega128 voltage supervisory circuit

4.2.4 RS232 Terminal

A standard RS232 line driver circuit utilising the dual-channel MAX232N [14] was used for

interfacing the USART interface with a PC. Jumper headers have been placed to isolate the

TX and RX lines to give greater control. The first channel USART0 is designed to be a

debugging terminal for the ATmega128 firmware, and hence is connected to a PC DB9

socket.

Figure 4-4: ATmega128 RS232 terminal


William Wong 25

4.2.4 External Memory

An external memory was added to the controller for storing FAT32 files system information

of the HDD and to buffer audio data, as described in the specifications in Chapter 3.5. A

1Mbit SRAM arranged in 64K x 16 bits was chosen to accommodate with the system’s 16-bit

data bus. The cheapest SRAM found was the Alliance Semiconductor’s AS7C1026 model

from Farnell Australia [15], costing A$20.63.

However when the order was made, a fax return was received informing that the product is

no longer manufactured but the alternate part was added as replacement. The alternate part

was the model AS7C31026A which has the same specifications as the previous model with

the exception that it is designed for +3.3V use. After investigating the datasheet for the

alternate part (refer to Appendix B), it was found that the device can sustain a maximum

rating of +5V. With that in mind, the memory can be biased to 4.5V without affecting

performance. This ensures the device is not sustained at its maximum rating for a long period.

Latches are needed for latching the memory address from the data bus to the address lines of

the SRAM. Two 8-bit latches were utilised for latching the 16-bit memory address. From

the advice given by the external memory interface of the ATmega128 datasheet, the Fairchild

74VHC573 advance high speed latches were used with slower D to Q propagation delay, data

setup time, and data hold time.

The output enable OE line along with the LB and UB lines are grounded, while the RD and

WR lines from the Atmel controller controls the chip enable CE line and write enable WE

line of the SRAM respectively. This configuration allows the SRAM to be in standby state

whenever reading and writing to the SRAM is not required, hence saving on power

consumption. For reading the SRAM, since the OE line is grounded permanently, an active

RD line will enable the data output at the data bus. For writing to SRAM, both WR and RD

lines must be active. To summarise the signals to the Atmel controller, two lines from the

Atmel WR and RD are for controlling the memory read and write, while one latch line (ALE)

is used for latching in the SRAM address from the data bus. This is illustrated in Figure 4-5.


William Wong 26

Figure 4-5: External memory

4.3 Storage

4.3.1 ATA/IDE Interface

The ATA/IDE interface is used for data transfer to and from the HDD, whereby 16 bits of

data can be transmitted at the same time. A 40-pins IDE ribbon type cable is used as the

medium for transmission. One end of the cable plugs into the hard drive, while the other end

connects to the on-board controller. Out of the 40 signals, 6 lines are for grounding. The rest

of the signals needed by the system are described below:

• DD0 to DD15 represents the 16-bit data bus which is where all data are written to and

read from the HDD

• CS0, CS1, DA0, DA1, and DA2 are addressing inputs that selects the registers shown

in Table 4-2 when combined with the read and write strobe signals (/DIOR and

/DIOW)

• /RESET is an active low hardware reset of the HDD

Before connecting these signals to the ATmega128, 2 ports are defined as the 16-bit data bus:

PORTA as the least significant bits, PORTC as the most significant bits. The reason for

choosing these ports is because the pins on these ports are situated next each other.


William Wong 27

Table 4-1: 40-pin IDE connector signals

Table 4-2: HDD register selections


William Wong 28

The 16-bit data bus from the HDD is than connected to the ATmega128 data bus (PORTA,

PORTC), while the addressing lines, read/write strobe lines, and /RESET line is connected to

PORTF, which will be controlling the HDD operation. No connections are made with the

remaining signals as they are used for DMA mode transfer which is not used by the system.

Figure 4-6: HDD control pins Figure 4-7: HDD data bus

4.3.2 File System Management

The USB interface was chosen for the remote storage access of the HDD due to its high

transfer rate compared with serial or parallel interface. Cypress manufactures a variety of

USB microcontroller that can handle the mass storage class of the ATA/IDE interface.

Samples were obtained of the Cypress SL11R-IDE chip which is basically a USB to IDE

bridge chip. By following the development circuit and uploading the firmware provided, the

HDD should appear as a remote drive on a PC when the USB connection is made. For the

schematic of this system, please refer to the full hardware schematic in Appendix C.

The SL11R-IDE will be powered by the USB to ensure the chip is inactive when no USB

connection is established. Since the chip is +3.3V powered, the LM1117 voltage regulator

purchased from RS Components [16] was used to step down to this voltage from the USB

voltage of +5V. The firmware of the SL11R-IDE is stored and loaded from the 16Kbits

AT24C164 serial I2C EEPROM purchased from RS Components [16].

For the ATmega128 to detect a USB connection with a remote PC, the USB power

(USBVCC) is directed to an interrupt-able pin in the ATmega128 to interrupt the system.


William Wong 29

4.4 User Interface

4.4.1 User Display

An alphanumeric LCD was chosen for the user display due to its low cost compared with

graphics LCD units. The minimum requirement is a two rows LCD display with LED

backlight, with the first row displaying the folder name, and the second row displaying the

track name of the file system. The cheapest and most characters LCD that could be found

was the GPC402-555-NYPBELY 40x2 characters LCD from PolyKOM [12].

There are 16 lines coming out of the LCD with pin 1 and 2 used by the LCD electronic (+5V

and GND). The contrast of the display can be adjusted by placing a potentiometer at pin 3.

Pins 7 to 10 are be left unconnected because 4-bit LCD interface mode will be used by the

firmware which only utilises the most significant four bits of the LCD data bus (pins 11 to 14)

for data transfer to and from the LCD. Pins 4, 5 and 6 are control signals for the LCD (RS,

R/W, E), which along with the significant four bit data bus (pins 11 to 14) are connected to

PORTB of the controller. Pins 15 and 16 are the anode and cathode points for the LED

backlight. The cathode is connected to ground permanently, while the anode is connected to

+5V via an ON/OFF switch for the user to control.

Figure 4-8: User display


William Wong 30

4.4.2 User Control

Although not all 9 buttons are needed for controlling the system, a 3x3 row column matrix

pushbuttons system for the user control adds flexibility to the design. The columns of the

matrix will be output from the system while the rows of the matrix are input to the system.

Because the LCD 4-bit data bus is also output from the system, the three column lines of the

matrix can utilise these lines.

For input into the system, the row lines of the matrix should be connected to interrupt-able

pins so that the system is interrupted by a button press, and take trigger the appropriate event

for that button press. Interrupt-able pins 6, 7 and 8 from PORTE are chosen for the row

inputs of the user control matrix.

Resistor divider circuit were implemented for each row-column combination. This ensures

minimal current drawn while allowing the row inputs to recognise a high when the buttons

are pushed. The voltage input to a particular row when a button is pressed from a column

outputting high is simply 10k/(10k+1k) x 5V = 4.54 volts, which is within the voltage high

threshold for the ATmega128.

Figure 4-9: User control


William Wong 31

4.5 Project Integration with Mr Garth Williams

The hardware implementation for integrating with Mr Garth Williams’ system is illustrated in

Figure 4-10 below. Signals D0 to D15 denotes the 16-bit data bus, while RXD1 and TXD1

are pins from the second channel USART. CTRL1 to CTRL4 are I/O pins allocated for

handshaking with CTRL3 and CTRL4 interrupt-able.

Figure 4-10: Integration with Mr Garth Williams' System

4.6 Overall System Design

Appendix C contains the full hardware schematic with the subsystems combined. The 16-bit

data bus located on PORTA and PORTC of the ATmega128 is shared among the HDD,

SRAM, and the SL11R-IDE USB-IDE chip.

The power supply of the system will be +12V which is needed by the motor of the HDD. A

voltage regulator is required to step down this voltage to +5V. Table 4-3 lists the total

maximum current consumption of the overall design for +5V rail by the major subsystems.

Components Max current (mA) ATmega128 20

MAX232 10 HDD 600

LCD + LED black 400 SRAM 160

TOTAL 1190

Table 4-3: Maximum current consumption of overall design


William Wong 32

Add in safety margin of around 300mA, the voltage regulator must be capable of supplying a

maximum of 1.5 amps. The L78S05 voltage regulator was found to be able to source 2 amps

and was purchased from RS Components [16].

4.7 PCB Design and Manufacture

The full hardware schematic was transferred onto one PCB design in Protel. The PCB

dimension was kept to within 5” x 4”, in view of fitting the PCB on top of the HDD. The

PCB was manufactured at the Electronics Workshop [17].

Before submitting the PCB for manufacturing, design rules check and netlist compare were

carried out to ensure the PCB is thoroughly checked against the design guidelines given by

the Electronics Workshop, and the netlist compares exactly that of the schematic file.

Appendix D and E contains the PCB in Protel and 3D view.

4.8 PCB Soldering and Testing

After the PCB was manufactured, all connections were checked against the schematic using

the continuity tester on a multimeter. This ensures mistakes are picked up before any

soldering work. The components were soldered from the smallest components to the largest,

and continuity testing was again conducted to ensure correct connections and no undesired

short-circuits.

The first thing to test was the power supply, which went smoothly with +5V coming out of

the voltage regulator. The Atmel ATmega128 was tested next by ensuring that it can be

programmed and detected by the STK200 dongle. The remaining components were

eventually tested and be found functioning correctly.


William Wong 33

4.9 Product Enclosure

A metal enclosure was purchased from Dick Smith Electronics to house the HDD and PCB of

the final product. A few days were spent at the Mechanical workshop at Hawken Building in

drilling and cutting holes of the enclosures. The following tasks were completed on the

enclosure:

• Securely mounting the HDD to the enclosure with metal screws

• Square holes for USB socket, serial DB9 socket, and LCD user display

• Holes for mounting the 6 user control pushbuttons and LEDs

• Hole for mounting the potentiometer for LCD contrast

• Holes for on/off switch and LCD LED-backlight switch

Appendix G contains photos of the final product.

CHAPTER 5:

Firmware Implementation


William Wong 35

5.0 FIRMWARE IMPLEMENTATION

5.1 Development Software

CodeVisionAVR was used as the C compiler for developing the firmware for the

ATmega128. Its library file “stdio.h” allows the transmission of formatted text like printf

command to the PC via the channel one USART interface. This proved to be an important

debugging tool used for troubleshooting the firmware.

Version control of the firmware was implemented whereby each phase of the developing

software was saved to a new file. A total of 15 versions were created during the firmware

implementation of this thesis. Table 5-1 lists the descriptions of each version control and

what it builds upon from the previous version.

Versions Code Description 0.1 Light a LED on I/O pin 0.2 Use “delay.h” library to blink LED 0.3 Use “lcd.h” library to display characters on LCD 0.4 Use “stdio.h” library to send characters to PC via USART0 0.5 Pushbuttons detection 0.6 SRAM read/write 0.7 Initialise and identify HDD 0.8 Sector reads from HDD send to PC via USART0 0.9 Sector reads from HDD to SRAM 1.0 FAT32 file system recognition 1.1 Process HDD root directory v1 1.2 Process HDD root directory v2 1.3 Root directory navigation with pushbuttons v1 1.4 SL11R-IDE USB interrupt control 1.5 Root directory navigation with pushbuttons v2

Table 5-1: Firmware version control

5.2 Early Developments

Early versions of the firmware were focused on getting familiar with programming in the

Atmel AVR environment. The firmware focused on using basic library functions to delay,

control the LCD, and send debugging information to PC via USART0.


William Wong 36

5.3 User Interface

5.3.1 User Display

For LCD interface to work with our hardware, the LCD port must be defined to PORTB as in

our hardware schematic and library must be included as part of the project: #asm

.equ __lcd_port=0x18

#endasm

#include <lcd.h>

The LCD must be first be initialised to the number of columns of the LCD, which is 40: lcd_init(40);

The following commands are mainly used for controlling the LCD throughout the firmware:

• lcd_clear(); - clears the LCD and home the cursor at row 0, column 0

• lcd_gotoxy(x,y); - position the LCD cursor to column x, row y

• lcd_putsf(“str”); - displays at the current display position the string “str”,

located in FLASH.

• lcd_putchar(c); - displays the character c at the current display position.

5.3.2 User Control

Timer/counter 1 was used to trigger the scanning of each column every 200 ms (the rate of 5

columns scanned per second). Three interrupts service routines are initialised to interrupt on

the rising edge of each row, designating a push button has been pushed. To work out which

button was pressed, a global variable last_column stores the last column scanned, and

depending on which row interrupts, which pushbutton is triggered will be known.


William Wong 37

5.4 HDD Interface

The firmware begins by running the ata_init() function which executes the following

tasks:

• Toggle /IDE_RESET pin to hardware reset the HDD

• Select device 0 (master mode) and LBA address translation mode in HDD

device/head register

• Send RECALIBRATE command to HDD command register and display error

message on LCD if the error bit is set in the HDD status register

Next the device is identified by sending an IDENTIFY DEVICE command to the HDD

command register, and than reading the 256 words of data about the device. Some of the

identity information is displayed to the LCD for device information (ie. the HDD model

number).

Functions are than created to read sectors or cluster of a hard drive into different form (a

cluster is equal to 8 sectors, while a sector is 512 bytes or 256 words):

• ata_read_sector_sram(lba, page)

The logical LBA sector is read into a page in external SRAM

• ata_read_sector_buffer(lba, *buffer)

The logical LBA sector is read into a local buffer array in the ATmega128 SRAM

• ata_read_cluster_sram(cluster_no, sram_page)

The logical LBA 8 sectors of a cluster is read into a page in SRAM

These functions are than used for reading the FAT32 file system contents on the HDD. Refer

to Appendix J and K for firmware on the IDE interface.


William Wong 38

5.5 FAT32 File System

After the IDE interfacing, the next step for the firmware is to navigate through the FAT32 file

system. The boot sector of the HDD (LBA address 0) is read and than checked to make sure

it is formatted to FAT32.

Next, the root directory cluster is read into the first 8 pages of the external SRAM which

contains the entries of all files and folders on the root directory of the HDD. Each entry is 32

bytes long, containing information about the file/folder including its name and the starting

cluster location for the actual data.

Next, entries in the root directory cluster are scanned for valid audio file format (WAV, MP3

or WMA file extensions), and the position of the valid file’s entry in the root directory is

stored in the array table WAVFileTable. For long file name contents, track names greater

than 40 characters are ignored, as they cannot be fitted on the LCD screen. After scanning all

contents in the root directory cluster and filling up the array table, the file name of the first

entry in the table is displayed, and the user control is enabled to allow user navigation of the

root directory.

The next track and prev track pushbuttons when activated will search for the next or previous

entry in the array table that contains a valid audio file, and outputs that entry’s filename onto

the LCD user display. Hence the navigation of the root directory has been implemented.

For extracting the current file displayed on the LCD screen, the play button must be pressed

which triggers an interrupt service routine to send all data of the current file to the USART

interface for capture and playback

Appendix H to L2 contains the full code listing of the firmware implemented.


William Wong 39

CHAPTER 6:

Product Evaluation


William Wong 40

6.0 PRODUCT EVALUATION

The final product has achieved most of the specifications defined in Chapter 3, with the main

goal of extracting audio file from the HDD functioning well. The hard drive was capable of

transferring 300 to 400 MB/s, which surpassed the specifications. The extracted audio files

were compared with its original, using the hex editor program – WinHex [18], and was found

to be equal in values, but with some additional bytes added.

Baud rate error in the USART interface is the probable cause for this error. Also, the

HyperTerminal program used for the capture and saving the extracted audio files might have

some emulation type problem, where some low ASCII values are recognised as escape

sequences and byte values changes when stored to a file.

6.1 File System Limitations

The limitations of the audio file extraction and FAT32 navigation of the current product are:

• Limited to searching audio files in the root directory

• Limited to browsing the first 128 files or folders in the root directory. This is due to

system’s limit on searching from the first root directory cluster.

• All data in the last cluster of an audio file extraction is sent

6.2 Remote Storage Access

The SL11R-IDE USB chip when implemented produces some strange results. The HDD can

be recognised as shown on Figure 6-1, with the correct capacity of the HDD displayed.

However the drive could not be initialized by Windows and the file system format could not

be detected. Some reasons for this could be an old firmware problem in the SL11R-IDE or

the HDD is not compatible with the USB chip.


William Wong 41

Figure 6-1: USB remote storage detection

6.3 Personal Reflections

My overall performance in the project was sound although my project management side of

the thesis could be better. The hardware implementation stage of the thesis took too long,

allowing not much time to develop the firmware. The use of Gantt chart and project

management software would have improved my performance.

But nevertheless, this project was an invaluable experience for me as I gained knowledge in

the Atmel AVR microcontrollers, the ATA/IDE interface along with the FAT32 file systems.

My Protel skills in designing schematics and PCBs have strengthened.

CHAPTER 7:

Future Developments


William Wong 43

7.0 FUTURE DEVELOPMENTS

The short-term development of the project is to improve the shortcomings of the current file

system navigation described in Chapter 6.1, and to get the USB remote interface working.

Another future development is to implementation this project with Mr Garth Williams’

turntable system, so that the audio files extracted in this system can be scratched.

Other possible expansion includes the interface with other storage sources such as serial ATA

devices, CD/CD-R/CD-RW discs, compact flash cards, and USB flash drive.

A graphic LCD would also be a nice feature that enhances the appearance of the product.

CHAPTER 8:

Conclusion


William Wong 45

8.0 CONCLUSION

The storage and user interface of the project was not integrated with Mr Garth Williams’

system due to the lack of time for implementing the systems together. However the potential

is there for combining the two projects into one digital turntable system.

The main goal of extracting audio files ranging from WAV to MP3 to WMA formats was

fulfilled. The user interface was functional with the user control able to navigate the FAT32

file system’s root directory and display the right information to the LCD.

CHAPTER 9:

Appendices


William Wong 47

9.0 APPENDICES

Appendix A: ATmega128 Microcontroller


William Wong 48

Appendix B: AS7C31026A SRAM


William Wong 49

Appendix C: Full Hardware Schematic

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C3)

58

PF4

(AD

C4 /

TCK

)57

PF5

(AD

C5 /

TMS)

56

PF6

(AD

C6 /

TDO

)55

PF7

(AD

C7

/ TD

I)54

ARE

F62

AG

ND

63

AVCC

64

PE0

(PD

I / R

XD

0)2

PE1

(PD

O /

TXD

0)

3

PE2

(AC+

/ X

CK0)

4

PE3

(AC-

/ O

C3A

)5

PE4

(INT4

/ O

C3B

)6

PE5

(INT5

/ O

C3C

)7

PE6

(INT6

/ T3

)8

PE7

(INT7

/ IC

3)9

PB0

( SS

)10

PB1

(SCK

)11

PB2

(MO

SI)

12

PB3

(MIS

O)

13

PB4

(OC

0)14

PB5

(OC

1A)

15

PB6

(OC1

B)16

PB7

(OC2

/ O

C1C)

17

(INT0

/ SC

L) P

DO

25

(INT1

/ SD

A)

PD1

26

(INT2

/ R

XD

1) P

D2

27

(INT3

/ TX

D1)

PD

328

(IC1)

PD

429

(XCK

1) P

D5

30

(T1)

PD

631

(T2)

PD

732

XTA

L223

XTA

L124

GND53GND22

VCC21 VCC52

PEN

1

RESE

T20

PG4

(TO

SC1)

19

PG3

(TO

SC2)

18

U1

ATM

EGA

128

1 2 3

K3

+5V

HEA

DER

1 2 3

K4

GN

DH

EAD

ER

+5V

1 2 3

K1

ALT

PWR

+12V

IN

1 2 3 4

K2

HD

DPW

R

+12V

+5V

1 2 3 4 5 6 7 8 9 10

K5

STK

200

+5V

K5R1

470R

U1C

3

100n

F

U1C

4

100n

F

U1C5

100n

F

K6R1

470R

+5V

R1

IN13

R2

IN8

T1

IN11

T2

IN10

GND 15V+2

V-6

VCC16

R1

OU

T12

R2

OU

T9

T1 O

UT

14

T2 O

UT

7

C1+

1

C1 -

3C2

+4

C2 -

5

U2

MA

X23

2N

+5V

+

U2C1

1uF

+

U2C2

1uF

+U2

C3

1uF

+U

2C4

1uF

+5V

1 6 2 7 3 8 4 9 5

K7

DB9

F

K0

12V

123

JP1

PWR

JMP

+12V

IN

+5V

+K

1C1

4.7u

F

RXD

0

RXD0

RXD

0

RESE

T

SCK

TXD

0

+5V

TXD0

SCK

RESE

T

TXD

0

TXD

1RX

D1

RXD

1

TXD

1

1 2 3

K8

USA

RT1

TXD

1_R

S232

RXD

1_RS

232

1 2

JP2

TX0J

P

1 2

JP3

RX

0JP

1 2

JP4

TX1J

P

1 2

JP5

RX

1JP

U2C

5

100n

F

K5D

1PR

OG

LED

K6D

1H

DD

LED

1

K9

AR

EF

D0

D1

D2

D3

D4

D5

D6

D7

D8 D9 D10

D11

D12

D13

D14

D15

DIO

WD

IOR

DA

0D

A1

DA2

CS0

CS1

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

K11

LCD

+5V

K11

P1PO

T1LC

D_R

SLC

D_R

/WLC

D_E

LCD

_D0

LCD

_D1

LCD

_D2

LCD

_D3

LCD

_D4

LCD

_D5

LCD

_D6

LCD

_D7

+5V

K11

S1

LCD

_BL

U3C1

300n

FU3

C210

0nF

IDE_

RST

K6R2

4k7

+5V

K11C

1

100n

F

1

K10

PEN

RES

ET1

GND

2

D7

3D

84

D6

5D

96

D5

7D1

08

D4

9D1

110

D3

11D1

212

D2

13D1

314

D1

15D1

416

D0

17D1

518

GN

D19

NC

20

DM

ARQ

21GN

D22

DIO

W23

GND

24

DIO

R25

GND

26

IOR

DY

27SP

SYN

C28

DM

ACK

29GN

D30

INTR

Q31

IO16

32

A1

33PD

IAG

34

A0

35A

236

CS0

37CS

138

DA

SP39

GND

40

K6

IDE

LCD

_D4

LCD

_D5

LCD

_D6

LCD

_D7

LCD

_E

LCD

_RS

+5V

U4R1

10k

U4S

1

RESE

T

U4C1

22nF

RESE

T

CS0

CS1

DA

0D

A1

DA

2

IDE_

RST

DIO

RD

IOW

ROW

1RO

W2

ROW

3

RESE

T1

INPUT2

GND3

U4

MC

3406

4P5

Vin

1V

out

2

GND 3

U3 L78S

05CV

+5V

+5V

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

ALE

ALE

ALE

A4

1A

32

A2

3A

14

A0

5

A15

18A

1419

A13

20A

1221

A11

24A

1025

A9

26A

827

A7

42A

643

A5

44

I/O0

7

I/O1

8

I/O2

9

I/O3

10

I/O4

13

I/O5

14

I/O6

15

I/O7

16

I/O8

29

I/O9

30

I/O10

31

I/O11

32

I/O12

35

I/O13

36

I/O14

37

I/O15

38

VCC11

VCC33

GND 12

GND34

CE

6

WE

17

OE

41

LB

39

UB

40

NC22

NC23

NC28

U7

AS7

C31

026A

-12T

C

+5V

+5V

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

RDWR

RD WR

OE

1

ALE

11

D0

2

D1

3

D2

4

D3

5

D4

6

D5

7

D6

8

D7

9

O1

19

O2

18

O3

17

O4

16

O5

15

O6

14

O7

13

O8

12

GN

D10

VCC

20

U5

74V

HC5

73N

OE

1

ALE

11

D0

2

D1

3

D2

4

D3

5

D4

6

D5

7

D6

8

D7

9

O1

19

O2

18

O3

17

O4

16

O5

15

O6

14

O7

13

O8

12

GN

D10

VCC

20

U6

74V

HC5

73N

U7C1

100n

F

U7C

2

100n

F

Vol

tage

Sup

ervi

sory

Inpu

t Pow

er

Po

wer

So

cket

s

RS

232

Term

inal

STK

200

Hea

der

Pro

gram

min

g

Use

r Dis

play

Mem

ory

Buf

fer

1 2 3 4 5 6 7 8

PF 8pin

s

GN

D+5

V

1 2 3 4 5 6 7 8

PE 8pin

s

1 2 3 4 5 6 7 8

PB 8pin

s

1 2 3 4 5 6 7 8

PA 8pins

1 2 3 4 5 6 7 8

PC 8pins

1 2 3 4 5 6 7 8

PD 8pins

1 2 3

PGL

3pins

12

PGU

2pin

s

K6R3

4k7

INTR

Q

K6R

45k6

+5V

TXD

1_RS

232

RXD

1_RS

232

DA

SP

IO16

PDIA

G

IOR

DY

DM

ACK

DM

ARQ

SPSY

NC

CTRL

1CT

RL2

CTRL

3CT

RL4

R1

1k

USB

VCC

12

34

56

78

910

1112

1314

1516

1718

1920

2122

K12

OU

TPU

T

R2 1k

Use

r C

ontr

ol

R3 1k

PB1 P

B

PB2 P

B

PB3 P

B

PB4 PB

PB5 PB

PB6 PB

PB7 PB

PB8 PB

PB9 PB

LCD_D4

LCD_D5

LCD_D6

ROW

3

ROW

2

ROW

1D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

RXD

1TX

D1C

TRL1

CTR

L2C

TRL3

CTR

L4

Sys

tem

Out

put

40-p

ins

IDE

Con

nect

or

1 2 3 4

J1 USB

TY

PE B

J1R1

36 J1R2 36

DA

TA-

DA

TA+

J1FB1

80(B

EAD

1206

TY

PE)

USB

VCC

J1C2

100n

FJ1

C110

0nF

J1R3

1k5U

SBPU

US

B S

ocke

t

1 2 3

JP6

PWRJ

P

+5V

USB

VCC

VC

C

GND 2

Vou

t1

Vin

3

U10

LM11

17-3

.3T

VCC

+U1

0C1

10uF

+U

10C

210

uF

+3V

3

3.3V

Reg

ulat

or

Po

wer

Sel

ecti

on

U8C3

100n

FU8

C410

0nF

U8C

510

0nF

U8C6

100n

FU

8C7

100n

FU8

C810

0nF

U8C

910

0nF

+3V3

SL1

1R-ID

E D

ecou

plin

g C

apac

itors

A0

1

A1

2

A2

3

GN

D4

SDA

5SC

L6

WP

7VC

C8

U11

AT2

4C16

4-10

PC

VCC

U11

R1

1k5 U11C

110

0nF

I2C

EE

PR

OM

SDA

SCL

GPI

O31

60

GPI

O30

61

GPI

O29

62

GPI

O28

63

GPI

O27

66

GPI

O26

67

GPI

O25

68

GPI

O24

69

GPI

O23

70

GPI

O22

71

GPI

O21

72

GPI

O20

73

GPI

O19

74

GPI

O18

76

GPI

O17

77

GPI

O16

78

GPI

O15

80

GPI

O14

81

GPI

O13

82

GPI

O12

83

GPI

O11

84

GPI

O10

85

GPI

O09

86

GPI

O08

91

RES

ET48

TEST

44

WR

L45

WR

H46

RD

47

RA

S49

CASL

52

CA

SH53

DR

AM

OE

54

DR

AM

WR

55

XRA

MSE

L56

XRO

MSE

L57

XM

EMSE

L58

X_P

CLK

59

X1

15

X2

16

A3

39

A2

41

A1

42

A0

43

D15

21

D0

2D

13

D2

4D

35

D4

6D

57

D6

8D

79

D8

10D

911

D10

12D1

113

D12

18D1

319

D14

20

GPI

O7

92

GPI

O6

93

GPI

O5

94

GPI

O4

95

GPI

O3

96

GPI

O2

97

GPI

O1

98

GPI

O0

99

GND

14

GND

40

GND

64

GND

65

GND

79

GND

90

VDD

1

VDD

17

VDD

50

VDD

51

VDD

75

VDD

87

VDD

100

DA

TA+

88

DA

TA-

89

U8 SL11

R-ID

E

GN

DG

ND

GN

DG

ND

GN

DG

ND

+3V

3+3

V3

+3V

3+3

V3

+3V

3+3

V3

+3V

3

DA

TA+

DA

TA-

U8R1

1M

U8R2

100R

U8Y

148

MH

z

U8C

1

10nF

U8C2

22pF

U8L

1

3u3H

SCL

SDA

USB

PUT

XR

XPW

CIN

TRQ

DA

SPD

IOW

CS0

CS1

DIO

RD

ETEC

T

DA

0D

A1

DA

2

D8

D9

D10

D11

D12

D13

D14

D15

D0

D1

D2

D3

D4

D5

D6

D7

VD

D3

RST

2V

SS1

U9

MCP

130-

450H

I/TO

U9C

110

0nF

1 2 3 4

K13

5pin

s

Thes

is P

roje

ct: S

tora

ge M

anag

emen

t for

MP

3 Tu

rnta

ble

U3S1

PWRS

W

+12V

12

JP7

USB

_RES

ET_V

DD

USBVCC

1

K14

USB

_RES

ET

LCD

_R/W

R6

10k

R5 10k

R4 10k


William Wong 50

Appendix D: PCB (Protel View)


William Wong 51

Appendix E: PCB (3D View)


William Wong 52

Appendix F: PCB Soldering


William Wong 53

Appendix G: Photos of the Final Product

Appendix G.1 Top view without cover

Appendix G.2 Front view


William Wong 54

Appendix G.3 Rear view

Appendix G.4 The LCD user display with LED backlight on


William Wong 55

Appendix H: Firmware (thesis.h)

/************************************************************* THE UNIVERSITY OF QUEENSLAND BACHELOR OF ENGINEERING (EE) 2003 SEMESTER 2 ENGG4801 THESIS PROJECT Project: Storage and User Interface for Digital Turntable Supervisor: Dr Peter Sutton Author: William Wai-Luen Wong StudentID: 33633134 Email: [email protected] Code Name: thesis.h Code Description: Header file for thesis15.c **************************************************************/ // * CodeVision LCD Module Library Function using PORTB #asm .equ __lcd_port=0x18 #endasm #include <lcd.h> // * TYPE DEFINITIONS typedef unsigned char byte; // 8-bits typedef unsigned int word; // 16-bits typedef unsigned long int dword;// 32-bits (mainly for LBA-addressing) typedef struct // FAT DIR structure { byte name[11]; dword fstclus; } DIR; typedef struct // FAT Long File Name (LFN) structure { byte LFN_name[40]; dword fstclus; } LFN; // * FUNCTION PROTOTYPES void init(void); void sram_read(word page, byte hex); void sram_read_buffer(word page, byte *buffer); byte sram_read_rootclus(word offset); void buffer_read(byte *buffer, byte hex); void USART1_tx(byte message); void FAT_BS(void); void scan_files(void); void file_update(void); void next_track(void); void prev_track(void); void play_once(void); dword FAT(dword cluster_no); // * BITS/VARIABLE DEFINITIONS // System properties #define XTAL 16000000 #define USART0_BAUD 57600 #define USART1_BAUD 57600 // Byte manipulations #define ZERO 0 #define BIT0 0b00000001 #define BIT1 0b00000010 #define BIT2 0b00000100 #define BIT3 0b00001000 #define BIT4 0b00010000 #define BIT5 0b00100000 #define BIT6 0b01000000 #define BIT7 0b10000000 // Data bus #define DATA_BUS_LOW_IN PINA #define DATA_BUS_HIGH_IN PINC


William Wong 56

#define DATA_BUS_LOW_OUT PORTA #define DATA_BUS_HIGH_OUT PORTC // SRAM #define SRAM_CONTROL PORTG #define SRAM_CONTROL_DIR DDRG #define SRAM_WR BIT0 #define SRAM_RD BIT1 #define SRAM_ALE BIT2 // * MACRO DEFINITIONS // Assembly #define SEI #asm("sei") #define CLI #asm("cli") #define NOP #asm("nop") #define TWO_NOPS NOP; \ NOP; // Exit - Atmel will do nothing and loops indefinately #define EXIT for(;;) NOP; // I/O ports and data bus initialisation #define DATA_BUS_DIR_IN DDRA = ZERO; \ DDRC = ZERO; #define DATA_BUS_DIR_OUT DDRA = (BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0); \ DDRC = (BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0); #define DATA_BUS_INIT DATA_BUS_LOW_OUT = ZERO; \ DATA_BUS_HIGH_OUT = ZERO; \ DATA_BUS_DIR_IN; #define PORTE_INIT PORTE = ZERO; \ DDRE = BIT1; #define PORTG_INIT SRAM_CONTROL = (BIT1 | BIT0); \ SRAM_CONTROL_DIR = (BIT2 | BIT1 | BIT0); // SRAM #define SRAM_ON SRAM_CONTROL &= ~SRAM_RD; #define SRAM_OFF SRAM_CONTROL |= SRAM_RD; #define SRAM_WRITE SRAM_CONTROL &= ~SRAM_WR; \ NOP; \ SRAM_CONTROL |= SRAM_WR; #define SRAM_LATCH SRAM_CONTROL |= SRAM_ALE; \ NOP; \ SRAM_CONTROL &= ~SRAM_ALE; // LCD #define lcd_blank lcd_clear(); #define lcd_home lcd_gotoxy(0,0); #define lcd_2ndrow lcd_gotoxy(0,1); #define lcd_2ndrowclear lcd_2ndrow; \ lcd_putsf(" "); \ lcd_2ndrow; #define lcd_display_normal _lcd_ready(); \ _lcd_write_data(BIT3 | BIT2); #define lcd_display_off _lcd_ready(); \ _lcd_write_data(BIT3); #define lcd_cursor _lcd_ready(); \ _lcd_write_data(BIT3 | BIT2 | BIT1); #define lcd_blink _lcd_ready(); \ _lcd_write_data(BIT3 | BIT2 | BIT0); #define lcd_shift_right _lcd_ready(); \ _lcd_write_data(BIT4 | BIT3 | BIT2); #define lcd_shift_left _lcd_ready(); \ _lcd_write_data(BIT4 | BIT3); #define lcd_move_right _lcd_ready(); \ _lcd_write_data(BIT4 | BIT2); #define lcd_move_left _lcd_ready(); \ _lcd_write_data(BIT4); #define lcd_space lcd_putsf(" "); #define lcd_sector_error lcd_blank; \ lcd_putsf("Sector read error! Scan device for disk"); \ lcd_2ndrow; \ lcd_putsf("errors... (Error code = 0x"); \ lcd_putchar(ata_read_register(ATA_REG_ERROR)); \ lcd_putchar(')'); \ delay_ms(5000); #define lcd_not_fat32_error lcd_blank; \ lcd_putsf("FAT32 file system not found! Please"); \ lcd_2ndrow; \ lcd_putsf("format device to FAT32 only..."); \ EXIT;


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#define lcd_stop lcd_gotoxy(18,0); \ lcd_putchar(ASCII_STOP); #define lcd_play lcd_gotoxy(18,0); \ lcd_putchar(ASCII_PLAY); // Characters for playback symbols #define ASCII_STOP 0xFF #define ASCII_PLAY 0x7E // USART0 - 'printf' function #define CLEAR_SCREEN "\0x1B[2J" #define cls printf(CLEAR_SCREEN); // Parameters to 'printf' function in HEX or ASCII form #define HEX 1 #define ASCII 0 // USART1 - commands of user control #define USART1_USB 0x00 #define USART1_STOP 0x01 #define USART1_PLAY 0x02 #define USART1_NEXT_FOLDER 0x04 #define USART1_NEXT_TRACK 0x08 #define USART1_PREV_TRACK 0x10 #define USART1_PREV_FOLDER 0x20 #define USART1_OTHER 0x40 // FAT BS - bytes combination #define bytes_to_word(offset) (((unsigned int)(bs[offset+1]) << 8) | (bs[offset])) #define bytes_to_dword(offset) (((unsigned long int)(bs[offset+3]) << 24) | \ ((unsigned long int)(bs[offset+2]) << 16) | \ ((unsigned int)(bs[offset+1]) << 8) | (bs[offset])) // FAT BS contents #define BPB_BytsPerSec bytes_to_word(11) #define BPB_SecPerClus (bs[13]) #define BPB_ResvdSecCnt bytes_to_word(14) #define BPB_NumFATs (bs[16]) #define BPB_RootEntCnt bytes_to_word(17) #define BPB_TotSec16 bytes_to_word(19) #define BPB_Media (bs[21]) #define BPB_FATSz16 bytes_to_word(22) #define BPB_SecPerTrk bytes_to_word(24) #define BPB_NumHeads bytes_to_word(26) #define BPB_HiddSec bytes_to_dword(28) #define BPB_TotSec32 bytes_to_dword(32) #define BPB_FATSz32 bytes_to_dword(36) #define BPB_ExtFlags bytes_to_word(40) #define BPB_FSVer bytes_to_word(42) #define BPB_RootClus bytes_to_dword(44) #define BPB_FSInfo bytes_to_word(48) #define BPB_BkBootSec bytes_to_word(50) #define BS_DrvNum (bs[64]) #define BS_Reserved1 (bs[65]) #define BS_BootSig (bs[66]) #define BS_VolID bytes_to_dword(67) // FAT32 data structure #define RootDirSectors 0 #define FATSz BPB_FATSz32 #define TotSec BPB_TotSec32 #define FirstSectorofCluster(N) (((N - 2) * (unsigned int)(SecPerClus)) + FirstDataSector) #define DataSec (TotSec - (BPB_ResvdSecCnt + (BPB_NumFATs * FATSz) + RootDirSectors)) #define CountofClusters (DataSec / SecPerClus) #define FATOffset (cluster_no * 4) #define ThisFATSecNum (ResvdSecCnt + (FATOffset / 512)) #define ThisFATEntOffset ((FATOffset % 512)) #define cluster_info (((unsigned long int)(fat[ThisFATEntOffset+3]) << 24) | \ ((unsigned long int)(fat[ThisFATEntOffset+2]) << 16) | \ ((unsigned int)(fat[ThisFATEntOffset+1]) << 8) | (fat[ThisFATEntOffset])) #define BAD_CLUSTER 0x0FFFFFF7 #define EOC 0 // FAT32 root directory cluster contents #define RC_Name(n) (sram_read_rootclus((i*32)+n)) #define RC_Attr (sram_read_rootclus((i*32)+11)) #define RC_FstClus (((unsigned long int)(sram_read_rootclus((i*32)+21)) << 24) | \ ((unsigned long int)(sram_read_rootclus((i*32)+20)) << 16) | \ ((unsigned int)(sram_read_rootclus((i*32)+27)) << 8) | (sram_read_rootclus((i*32)+26)))


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#define RC_FileSize (((unsigned long int)(sram_read_rootclus((i*32)+31)) << 24) | \ ((unsigned long int)(sram_read_rootclus((i*32)+30)) << 16) | \ ((unsigned int)(sram_read_rootclus((i*32)+29)) << 8) | (sram_read_rootclus((i*32)+28))) #define ATTR_READ_ONLY 0x01 #define ATTR_HIDDEN 0x02 #define ATTR_SYSTEM 0x04 #define ATTR_VOLUME_ID 0x08 #define ATTR_DIRECTORY 0x10 #define ATTR_ARCHIVE 0x20 // LFN contents #define ATTR_LONG_NAME (ATTR_READ_ONLY | ATTR_HIDDEN | ATTR_SYSTEM | ATTR_VOLUME_ID) #define LFN_Short_Attr (sram_read_rootclus(((i+LFNpos)*32)+11)) #define LFN_Short_Name_Ext1 (sram_read_rootclus(((i+LFNpos)*32)+8)) #define LFN_Short_Name_Ext2 (sram_read_rootclus(((i+LFNpos)*32)+9)) #define LFN_Short_Name_Ext3 (sram_read_rootclus(((i+LFNpos)*32)+10)) #define LRC_Name1(n) (sram_read_rootclus((i*32)+(n*2)+1)) #define LRC_Name2(n) (sram_read_rootclus((i*32)+(n*2)+14)) #define LRC_Name3(n) (sram_read_rootclus((i*32)+(n*2)+28)) #define LFN_MASK 0x40 // Filename ASCII contents #define ASCII_W 0x57 #define ASCII_A 0x41 #define ASCII_V 0x56 #define ASCII_M 0x4D #define ASCII_P 0x50 #define ASCII_3 0x33 #define ASCII_SPACE 0x20 #define ASCII_DOT 0x2E // * GLOBAL VARIABLES // Keypad byte last_column = 1; // FAT boot sector byte SecPerClus; word ResvdSecCnt; dword FirstDataSector, RootClus; // Playback - element of WAVFileTable currently being played byte CurrentFile; // Plaback - starting cluster containing current wav file, and its file size in bytes dword CurrentFileStartClus, CurrentFileSize; // Valid WAVE file's entry in root cluster stored in table, otherwise no entry is denoted by "0xFF" byte WAVFileTable[128]; // The number of sub components of LFN stored in its entry in table byte LFNFileTable[128];

Appendix I: Firmware (thesis15.c)

/************************************************************** THE UNIVERSITY OF QUEENSLAND BACHELOR OF ENGINEERING (EE) 2003 SEMESTER 2 ENGG4801 THESIS PROJECT Project: Storage and User Interface for Digital Turntable Supervisor: Dr Peter Sutton Author: William Wai-Luen Wong StudentID: 33633134 Email: [email protected] Code Name: thesis15.c Code Version: 1.5 Code Description: Final Firmware **************************************************************/ #include <mega128.h> #include <delay.h> #include <stdio.h> #include "thesis.h" #include "keypad.c" #include "ide3.c" // * Timer 1 output compare A ISR // * Scan next keypad column every 200ms interrupt [TIM1_COMPA] void timer1_compa_isr(void) { keypad_scan(); } // * INT4 ISR: Keypad ROW3 interrupt [EXT_INT4] void ext_int4_isr(void) { // Disable external interrupts except USBVCC (INT7) EIMSK = 0b10000000; EIFR = 0b10000000; lcd_home; switch (last_column) { case 1: // ROW 3, COLUMN 1 //lcd_putsf("Push button 3 pressed!"); //lcd_space; USART1_tx(USART1_NEXT_TRACK); next_track(); break; case 2: // ROW 3, COLUMN 2 //lcd_putsf("Push button 6 pressed!"); //lcd_space; USART1_tx(USART1_OTHER); break; /* case 3: // ROW 3, COLUMN 3 lcd_putsf("Push button 9 pressed!"); break;*/ default: break; } // Re-enable external interrupts EIMSK = 0xF0; EIFR = 0xF0; } // * INT5 ISR: Keypad ROW2 interrupt [EXT_INT5] void ext_int5_isr(void) { // Disable external interrupts except USBVCC (INT7) EIMSK = 0b10000000; EIFR = 0b10000000;


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lcd_home; switch (last_column) { case 1: // ROW 2, COLUMN 1 //lcd_putsf("Push button 2 pressed!"); //lcd_space; USART1_tx(USART1_PREV_TRACK); prev_track(); break; case 2: // ROW 2, COLUMN 2 //lcd_putsf("Push button 5 pressed!"); //lcd_space; /* stop_play = !stop_play; if(stop_play == 0) { USART1_tx(USART1_STOP); //lcd_stop; }*/ USART1_tx(USART1_PLAY); play_once(); break; /* case 3: // ROW 2, COLUMN 3 lcd_putsf("Push button 8 pressed!"); break; */ default: break; } // Re-enable external interrupts EIMSK = 0xF0; EIFR = 0xF0; } // * INT6 ISR: Keypad ROW1 interrupt [EXT_INT6] void ext_int6_isr(void) { // Disable external interrupts except USBVCC (INT7) EIMSK = 0b10000000; EIFR = 0b10000000; lcd_home; switch (last_column) { case 1: // ROW 1, COLUMN 1 //lcd_putsf("Push button 1 pressed!"); //lcd_space; USART1_tx(USART1_PREV_FOLDER); break; case 2: // ROW 1, COLUMN 2 //lcd_putsf("Push button 4 pressed!"); //lcd_space; USART1_tx(USART1_NEXT_FOLDER); break; /* case 3: // ROW 1, COLUMN 3 lcd_putsf("Push button 7 pressed!"); break;*/ default: break; } // Re-enable external interrupts EIMSK = 0xF0; EIFR = 0xF0; } // * INT7 ISR: USBVCC interrupt [EXT_INT7] void ext_int7_isr(void) { // ATA control pins high Z ATA_CNTRL_DIR = ZERO; // Data Bus Hi Z DATA_BUS_DIR_IN; // Switch off SRAM SRAM_OFF;


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// Disable global interrupts CLI; // Signal USB connection to USART1 USART1_tx(USART1_USB); // User display lcd_blank; lcd_putsf("USB connection established"); lcd_2ndrow; lcd_putsf("Unplug cable when finished"); // Wait indefinately until USB connection ceases while(PINE & BIT7); // ATA control port re-initialise ATA_CNTRL_DIR = 0xFF; // Scan root directory again lcd_blank; lcd_putsf("Root directory"); // Read root directory and store wave files entry in WAVFileTAble scan_files(); // Display first file name in WAVFileTAble CurrentFile = 0; file_update(); lcd_stop; // Re-enable global interrupts SEI; } // * READ A PAGE OF SRAM // * Returns a page of SRAM data to PC via USART0 // * Hex or ASCII display are chosen by the parameter 'hex' void sram_read(word page, byte hex) { word sram_address, i; sram_address = page * 256; //printf("\r\n\r\nSRAM read from page = %u\r\n",page); for(i = 0; i < 256; i++) { // Latch address DATA_BUS_DIR_OUT; DATA_BUS_HIGH_OUT = sram_address >> 8; DATA_BUS_LOW_OUT = sram_address & 0x00FF; SRAM_LATCH; // Send SRAM data to PC from latched address location DATA_BUS_DIR_IN; SRAM_ON; NOP; if(hex == HEX) { if(i % 8 == 0) { printf("\r\n"); } printf("%02X %02X ",DATA_BUS_LOW_IN,DATA_BUS_HIGH_IN); } else { putchar(DATA_BUS_LOW_IN); putchar(DATA_BUS_HIGH_IN); } SRAM_OFF; sram_address++; } } // * READ A PAGE OF SRAM


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// * Returns a page of SRAM to local buffer in Atmel void sram_read_buffer(word page, byte *buffer) { word i, sram_address; sram_address = page * 256; for(i = 0; i < 256; i++) { // Latch address DATA_BUS_DIR_OUT; DATA_BUS_HIGH_OUT = sram_address >> 8; DATA_BUS_LOW_OUT = sram_address & 0x00FF; SRAM_LATCH; // Store SRAM data to buffer DATA_BUS_DIR_IN; SRAM_ON; NOP; buffer[i*2] = DATA_BUS_LOW_IN; buffer[i*2+1] = DATA_BUS_HIGH_IN; SRAM_OFF; sram_address++; } } // * READ A SECTOR STORED IN BUFFER ARRAY // * Returns a sector worth of data to PC via USART0 // * Hex or ASCII display are chosen by the parameter 'hex' void buffer_read(byte *buffer, byte hex) { word i; printf("\r\n\r\n*** Buffer read ***\r\n\r\n"); for(i = 0; i < 256; i++) { if(hex == HEX) // Display in hex form { if(i % 8 == 0) { printf("\r\n"); } printf("%02X %02X ",buffer[i*2],buffer[i*2+1]); } else // Display in ASCII characters form { printf("%c%c",buffer[i*2],buffer[i*2+1]); } } } // * READ A BYTE FROM SRAM // * Returns a byte from root cluster in SRAM from given offset number "offset" byte sram_read_rootclus(word offset) { word sram_address; byte data_return; sram_address = offset / 2; // Latch address DATA_BUS_DIR_OUT; DATA_BUS_HIGH_OUT = sram_address >> 8; DATA_BUS_LOW_OUT = sram_address & 0x00FF; SRAM_LATCH; // return byte in position offset DATA_BUS_DIR_IN; SRAM_ON; NOP; if(offset % 2) { data_return = DATA_BUS_HIGH_IN; } else


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{ data_return = DATA_BUS_LOW_IN; } SRAM_OFF; sram_address++; return data_return; } // * USART1 TX // * Transmit the byte in parameter 'message' through USART1 void USART1_tx(byte message) { // Only send when USART1 transmit buffer is empty while(!(UCSR1A & BIT5)); UDR1 = message; } // * MAIN INITIALISE FUNCTION // * Setup PORTs, TIMERs, USARTs, INTERRUPTs, ATA void init(void) { // Disable global interrupts CLI; // Analog comparator off ACSR = BIT7; // Pull up on input ports disabled SFIOR |= BIT2; // 16-bit I/O data bus initialisation // Initialise as inputs // PORTA = D15..D8 // PORTC = D7..D0 DATA_BUS_INIT; // SRAM I/O control initialisation // Initialise as outputs // PORTG.0 = /WR = '1' // PORTG.1 = /RD = '1' // PORTG.2 = ALE = '0' PORTG_INIT; // ATA control pins initialisation // Initialise as outputs // PORTF = 0b11111111 (data bus high Z) PORTF_INIT; // PORTE initialisation // PE0 for USART0 RX input // PE1 for USART1 TX output // PE4/PE5/PE6 for Keypad ROW3/ROW2/ROW1 EXT-INT input // PE7 for USBVCC EXT-INT input PORTE_INIT; // PORTE data direction: I I I I I I O I // External Interrupts // INT4/INT5/INT6/INT7 Rising Edge Modes EICRA = ZERO; EICRB = 0xFF; EIMSK = 0xF0; EIFR = 0xF0; // USART0 asynchronous tx mode // 8 data bit, 1 stop bit, no parity, // Baud rate specify in thesis.h header file // Use for data transfer UCSR0A = ZERO; UCSR0B = BIT3; // USART0 TX enable UCSR0C = (BIT2 | BIT1); // Async, 8 data, 1 stop, no parity UBRR0H = ZERO; UBRR0L = (XTAL / (16*USART1_BAUD)) - 1; // USART1 asynchronous tx mode // 8 data bit, 1 stop bit, no parity, // Baud rate specify in thesis.h header file // Use for communication


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UCSR1A = ZERO; UCSR1B = BIT3; // USART1 TX enable UCSR1C = (BIT2 | BIT1); // Async, 8 data, 1 stop, no parity UBRR1H = ZERO; UBRR1L = (XTAL / (16*USART1_BAUD)) - 1; // Timer/Counter 1 Output Compare A // CTC top = OCR1A mode // fclk/256 clock select (62.5kHz, 16us clk cycle) // OCR1A compare at 200ms (12500 x 16us = 200ms) TCCR1A = ZERO; TCCR1B = ZERO; //Timer 1 stopped for the moment TCNT1H = ZERO; TCNT1L = ZERO; // OCR1A = 12500 = 0x30D4 OCR1AH = 0x30; OCR1AL = 0xD4; // Output Compare A match interrupt enable TIMSK = BIT4; // Initialise LCD module (40 char x 2 lines) lcd_init(40); // Print opening message on LCD // Allow > 10 seconds for IDE device to spin up lcd_gotoxy(9,0); lcd_putsf("\0177 DIGITAL TURNTABLE \0176"); lcd_gotoxy(14,1); lcd_putsf("Loading."); delay_ms(2500); lcd_putchar('.'); delay_ms(2500); lcd_putchar('.'); delay_ms(2500); lcd_putchar('.'); delay_ms(2500); lcd_putchar('.'); // Initialise device ata_init(); // Identify device ata_identify(); // Determine file system of IDE device FAT_BS(); delay_ms(4000); // Read root directory cluster to beginning of SRAM if(ata_read_cluster_sram(RootClus,0)) { lcd_sector_error; } lcd_blank; lcd_putsf("Root directory"); // Read root directory and store wave files entry in WAVFileTAble scan_files(); // Display first file name in WAVFileTAble CurrentFile = 0; file_update(); lcd_stop; // Enable global interrupts SEI; // Start Timer1 256 prescaler (keypad scan) TCCR1B = (BIT3 | BIT2); } // * UPDATE FILENAME AND FIRST CLUSTER INFO OF CURRENT FILE // * Filename on LCD updated to CurrentFile entry in WAVFileTable updated // * CurrentFileStartClus updated to CurrentFile entry in WAVFileTable updated void file_update(void)


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{ word i, y, LFNpos; byte count; i = WAVFileTable[CurrentFile]; LFNpos = LFNFileTable[CurrentFile]; lcd_2ndrow; // Proceed if entry is not a LFN if(LFNpos == 0) { // Display filename in 2nd row of LCD for(count = 0; count < 8; count++) { if(RC_Name(count) != ASCII_SPACE) { lcd_putchar(RC_Name(count)); } } lcd_putchar(ASCII_DOT); // Display file extension after dot after filename in 2nd row of LCD (should be "WAV") for(count = 0; count < 3; count++) { lcd_putchar(RC_Name(count+8)); } // Store starting cluster for file in global variable CurrentFileStartClus = RC_FstClus; CurrentFileSize = RC_FileSize; } else // Process LFN entry { // Move to 1st long entry i += (LFNpos - 1); // Write filename to LCD from 1st LFN entry to last LFN entry for(count = 0; count < LFNpos; count++) { for(y = 0; y < 5; y++) { if((LRC_Name1(y) != 0x00) && (LRC_Name1(y) != 0xFF)) { lcd_putchar(LRC_Name1(y)); } } for(y = 0; y < 6; y++) { if((LRC_Name2(y) != 0x00) && (LRC_Name2(y) != 0xFF)) { lcd_putchar(LRC_Name2(y)); } } for(y = 0; y < 2; y++) { if((LRC_Name3(y) != 0x00) && (LRC_Name3(y) != 0xFF)) { lcd_putchar(LRC_Name3(y)); } } i--; } // Store starting cluster for file in global variable i += (LFNpos+1); CurrentFileStartClus = RC_FstClus; CurrentFileSize = RC_FileSize; } } // * BOOT SECTOR DECODE // * Determine FAT type and sector/cluster structures of device void FAT_BS(void) { // Store FAT boot sector (512 bytes = 1 sector)


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byte bs[512]; // Read boot sector of device and determine its FAT type if(ata_read_sector_buffer(0,bs)) { lcd_sector_error; } ResvdSecCnt = BPB_ResvdSecCnt; SecPerClus = BPB_SecPerClus; RootClus = BPB_RootClus; FirstDataSector = (ResvdSecCnt + (BPB_NumFATs * FATSz) + RootDirSectors); if((BPB_RootEntCnt != 0) || (CountofClusters < 65525)) { lcd_not_fat32_error; // Device not formatted to FAT32 } else // Device is FAT32 { lcd_gotoxy(35,0); lcd_putsf("FAT32"); } } // * READ INFORMATION ABOUT A CLUSTER IN FAT // * Return the result of the information obtained dword FAT(dword cluster_no) { byte fat[512]; // Read the sector in FAT holding information for given cluster if(ata_read_sector_buffer(ThisFATSecNum,fat)) { lcd_sector_error; } if(cluster_info > BAD_CLUSTER) // End of cluster, return EOC mark (0) { return EOC; } else if(cluster_info == BAD_CLUSTER) // Bad cluster, return bad cluster marker { return(BAD_CLUSTER); } else // User data, return next cluster of file { return cluster_info; } } // * Scan root directory and fill the arrays WAVFileTable and LFNFileTable // * with the entries in root directory cluster containing a short or long name WAV file void scan_files(void) { byte WAVFileTablePos, LFNpos; word i; // Clear WAVFileTAble array with 0xFF for(i = 0; i < 128; i++) { WAVFileTable[i] = 0xFF; } WAVFileTablePos = 0; // Scan each root cluster entry for(i = 0; i < 128; i++) { // Proceed if there is an entry(!=0x00) and it is not empty (!=0xE5) if((RC_Name(0) != 0x00) && (RC_Name(0) != 0xE5)) { // Process short name entry if(RC_Attr != ATTR_LONG_NAME) { // Proceed if entry is not a directory, and is not a hidden/system/volume ID label file if(!(RC_Attr & ATTR_DIRECTORY) && !(RC_Attr & ATTR_HIDDEN) \ && !(RC_Attr & ATTR_SYSTEM) && !(RC_Attr & ATTR_VOLUME_ID))


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{ // Proceed if file extension is WAV or MP3 or WMA if(((RC_Name(8) == ASCII_W) && (RC_Name(9) == ASCII_A) && (RC_Name(10) == ASCII_V)) || \ ((RC_Name(8) == ASCII_M) && (RC_Name(9) == ASCII_P) && (RC_Name(10) == ASCII_3)) || \ ((RC_Name(8) == ASCII_W) && (RC_Name(9) == ASCII_M) && (RC_Name(10) == ASCII_A))) { WAVFileTable[WAVFileTablePos] = i; LFNFileTable[WAVFileTablePos] = 0; WAVFileTablePos++; } } } else // Process LFN entry { // Position of current sub component LFN LFNpos = RC_Name(0) & ~LFN_MASK; // Proceed if LFN is less than 40 characters if(LFNpos < 4) { // Proceed if short entry of LFN is not a directory, hidden/system/volume ID file if(!(LFN_Short_Attr & ATTR_DIRECTORY) && !(LFN_Short_Attr & ATTR_HIDDEN) \ && !(LFN_Short_Attr & ATTR_SYSTEM) && !(LFN_Short_Attr & ATTR_VOLUME_ID)) { // Proceed if short entry of LFN's file extension is WAV or MP3 or WMA if(((LFN_Short_Name_Ext1 == ASCII_W) && (LFN_Short_Name_Ext2 == ASCII_A) && (LFN_Short_Name_Ext3 == ASCII_V)) || \ ((LFN_Short_Name_Ext1 == ASCII_M) && (LFN_Short_Name_Ext2 == ASCII_P) && (LFN_Short_Name_Ext3 == ASCII_3)) || \ ((LFN_Short_Name_Ext1 == ASCII_W) && (LFN_Short_Name_Ext2 == ASCII_M) && (LFN_Short_Name_Ext3 == ASCII_A))) { WAVFileTable[WAVFileTablePos] = i; LFNFileTable[WAVFileTablePos] = LFNpos; WAVFileTablePos++; i += LFNpos; } else // skip all remaining LFN sub components entry and short entry { i += LFNpos; } } else // skip all remaining LFN sub components entry and short entry { i += LFNpos; } } else // skip all remaining LFN sub components entry and short entry { i += LFNpos; } } } } } void next_track(void) { // point to first file in table if current file is last entry or the next entry is empty if(CurrentFile == 127 || (WAVFileTable[CurrentFile + 1] == 0xFF)) { CurrentFile = 0; } else // increment to next file in WAVFileTable { CurrentFile++; }


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// Update current file lcd_2ndrowclear; file_update(); } void prev_track(void) { byte prev = 127; // point to last valid file entry in table if current file is first entry of table if(CurrentFile == 0) { while(WAVFileTable[prev] == 0xFF) { prev--; } CurrentFile = prev; } else // decrement to prev file in WAVFileTable { CurrentFile--; } // Update current file lcd_2ndrowclear; file_update(); } void play_once(void) { word CScount; dword FileClus, Cluscount,NextClus; FileClus = (CurrentFileSize / (512 * SecPerClus)); lcd_play; // Send first cluster ata_read_cluster_sram(CurrentFileStartClus,8); for(CScount = 0; CScount < SecPerClus; CScount++) { sram_read(8+CScount,ASCII); } // Proceed if file is more than one cluster if(FileClus > 0) { // Get next cluster from FAT NextClus = FAT(CurrentFileStartClus); for(Cluscount = 0; Cluscount < FileClus; Cluscount++) { // Send next cluster given by FAT ata_read_cluster_sram(NextClus,8); for(CScount = 0; CScount < SecPerClus; CScount++) { sram_read(8+CScount,ASCII); } // Get next cluster from FAT NextClus = FAT(NextClus); } } lcd_stop; } // * MAIN ROUTINE // * main void main(void) { init(); // Loop indefinately EXIT; }


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Appendix J: Firmware (ide.h)

/************************************************************* THE UNIVERSITY OF QUEENSLAND BACHELOR OF ENGINEERING (EE) 2003 SEMESTER 2 ENGG4801 THESIS PROJECT Project: Storage and User Interface for Digital Turntable Supervisor: Dr Peter Sutton Author: William Wai-Luen Wong StudentID: 33633134 Email: [email protected] Code Name: ide.h Code Description: Header file for ide3.c **************************************************************/ // * EXTERNAL FUNCTION PROTOTYPES extern void ata_init(void); extern void ata_hard_reset(void); extern void ata_identify(void); extern void ata_select_device(byte device); extern void ata_write_byte(byte ata_byte_write); extern void ata_write_cmd(byte ata_byte_write); extern byte ata_read_register(byte ata_register); extern byte ata_busy(void); extern byte ata_drdy(void); extern byte ata_drq(void); extern byte ata_err(void); extern word ata_read_word(void); extern byte ata_read_sector(dword lba); extern byte ata_read_sector_sram(dword lba, word page); extern byte ata_read_sector_buffer(dword lba, byte *buffer); extern byte ata_read_cluster_sram(dword cluster_no, word sram_page); // * BITS/VARIABLE DEFINITIONS // ATA control pins on PORTF #define ATA_CNTRL PORTF #define ATA_CNTRL_DIR DDRF #define CS1 0b00000001 #define CS0 0b00000010 #define DA2 0b00000100 #define DA1 0b00001000 #define DA0 0b00010000 #define IDE_RESET 0b00100000 #define DIOR 0b01000000 #define DIOW 0b10000000 // ATA I/O control block registers // DIOW // |DIOR // ||IDE_RESET // |||DA0 // ||||DA1 // |||||DA2 // ||||||CS0 // |||||||CS1 // |||||||| #define ATA_REG_HIZ 0b11100011 #define ATA_REG_ALTSTATUS 0b11101110 #define ATA_REG_DEVICECNTRL 0b11101110 // ATA I/O command block registers #define ATA_REG_DATA 0b11100001 #define ATA_REG_ERROR 0b11110001 #define ATA_REG_FEATURES 0b11110001 #define ATA_REG_SECTORCNT 0b11101001 #define ATA_REG_SECTORNUM 0b11111001 #define ATA_REG_CYLINDERLOW 0b11100101 #define ATA_REG_CYLINDERHIGH 0b11110101 #define ATA_REG_DEVICEHEAD 0b11101101 #define ATA_REG_STATUS 0b11111101 #define ATA_REG_COMMAND 0b11111101


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// ATA status register #define ATA_STATUS_BUSY BIT7 #define ATA_STATUS_DRDY BIT6 #define ATA_STATUS_DF BIT5 #define ATA_STATUS_DSC BIT4 #define ATA_STATUS_DRQ BIT3 #define ATA_STATUS_CORR BIT2 #define ATA_STATUS_IDX BIT1 #define ATA_STATUS_ERR BIT0 // ATA device/head register #define ATA_DEVICEHEAD_DEV0 0b11100000 // Device 0 LBA mode #define ATA_DEVICEHEAD_DEV1 0b11110000 // Device 1 LBA mode // ATA commands #define ATA_CMD_RECALIBRATE 0x10 #define ATA_CMD_IDENTIFY_DEVICE 0xEC #define ATA_CMD_READ_SECTORS 0x20 // * MACRO DEFINITIONS // ATA control pins initialisation #define PORTF_INIT ATA_CNTRL = (DIOW | DIOR | IDE_RESET | DA0 | DA1 | DA2 | CS0 | CS1); \ ATA_CNTRL_DIR = (DIOW | DIOR | IDE_RESET | DA0 | DA1 | DA2 | CS0 | CS1); // ATA status #define busy ata_busy() #define drdy ata_drdy() #define drq ata_drq() #define err ata_err() #define ata_diow_pulse ATA_CNTRL &= ~DIOW; \ TWO_NOPS; \ ATA_CNTRL |= DIOW;


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Appendix K: Firmware (ide.c)

/************************************************************* THE UNIVERSITY OF QUEENSLAND BACHELOR OF ENGINEERING (EE) 2003 SEMESTER 2 ENGG4801 THESIS PROJECT Project: Storage and User Interface for Digital Turntable Supervisor: Dr Peter Sutton Author: William Wai-Luen Wong StudentID: 33633134 Email: [email protected] Code Name: ide3.c Code Description: IDE interface for hard disk drive **************************************************************/ #include "ide.h" // * INITIALISE ATA DEVICE // * Initialises Device 0 void ata_init(void) { // Hardware reset while(!drdy); ata_hard_reset(); delay_ms(10); // Select device 0 LBA mode ata_select_device(0); // Recalibrate device ata_write_cmd(ATA_CMD_RECALIBRATE); // Check if error occured while(busy); if(err) { lcd_blank; lcd_putsf("Device error! Ensure device is not"); lcd_2ndrow; lcd_putsf("damaged and is readable..."); EXIT; //printf("\r\nDEVICE ERROR!! Error register = 0x%X.",ata_read_register(ATA_REG_ERROR)); } } // * ATA DEVICE HARDWARE RESET // * IDE_RESET line is toggled low for 30us, specified in ATA-3 void ata_hard_reset(void) { DATA_BUS_DIR_IN; ATA_CNTRL = ATA_REG_HIZ; ATA_CNTRL &= ~IDE_RESET; delay_us(30); ATA_CNTRL |= IDE_RESET; } // * SELECT ATA DEVICE // * Default device is 0 void ata_select_device(byte device) { while(!drdy); ATA_CNTRL = ATA_REG_DEVICEHEAD; switch(device) { case 0: ata_write_byte(ATA_DEVICEHEAD_DEV0); break; case 1: ata_write_byte(ATA_DEVICEHEAD_DEV1); break; default:


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ata_write_byte(ATA_DEVICEHEAD_DEV0); break; } } // * IDENTIFY ATA DEVICE // * Receive device information void ata_identify(void) { byte i; word word_read; // Identify device while(!drdy); ata_write_cmd(ATA_CMD_IDENTIFY_DEVICE); // Display device characteristic on 2nd row of LCD lcd_blank; lcd_2ndrow; while(!drq); word_read = ata_read_word(); if(word_read & 0x8000) lcd_putsf("ATAPI "); else lcd_putsf("ATA "); if(word_read & 0x0080) lcd_putsf("removable device detected"); else lcd_putsf("non-removable device detected"); for(i = 0; i < 26; i++) { ata_read_word(); } // Display model number on 1st row of LCD lcd_home; for(i = 0; i < 20; i++) { word_read = ata_read_word(); lcd_putchar(word_read >> 8); lcd_putchar(word_read & 0x00FF); } // Read the rest of identify device words for(i = 0; i < 209; i++) ata_read_word(); } // * WRITE BYTE TO ATA I/O // * Writes a byte to lower data bus void ata_write_byte(byte ata_byte_write) { DATA_BUS_DIR_OUT; DATA_BUS_LOW_OUT = ata_byte_write; ata_diow_pulse; ATA_CNTRL = ATA_REG_HIZ; DATA_BUS_DIR_IN; } // * WRITE COMMAND TO ATA COMMAND REGISTER // * Sends an ATA command to device void ata_write_cmd(byte ata_byte_write) { while(!drdy); ATA_CNTRL = ATA_REG_COMMAND; ata_write_byte(ata_byte_write); } // * READ ATA REGISTER // * Returns a byte from the register specified in parameter 'ata_register' byte ata_read_register(byte ata_register) { byte ata_byte_read; DATA_BUS_DIR_IN; ATA_CNTRL = ata_register; ATA_CNTRL &= ~DIOR;


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TWO_NOPS; ata_byte_read = DATA_BUS_LOW_IN; ATA_CNTRL |= DIOR; ATA_CNTRL = ATA_REG_HIZ; return ata_byte_read; } // * CHECK BUSY BIT IN ATA STATUS REGISTER // * Returns 1 if device is busy with command block registers byte ata_busy(void) { if(ata_read_register(ATA_REG_STATUS) & ATA_STATUS_BUSY) return 1; else return 0; } // * CHECK DRDY BIT IN ATA STATUS REGISTER // * Returns 1 if device is ready to accept command codes byte ata_drdy(void) { byte word_read; word_read = ata_read_register(ATA_REG_STATUS); if(word_read & ATA_STATUS_BUSY) return 0; else if(word_read & ATA_STATUS_DRDY) return 1; else return 0; } // * CHECK DRQ BIT IN ATA STATUS REGISTER // * Returns 1 if device is ready to transfer data byte ata_drq(void) { byte word_read; word_read = ata_read_register(ATA_REG_STATUS); if(word_read & ATA_STATUS_BUSY) return 0; else if(word_read & ATA_STATUS_DRQ) return 1; else return 0; } // * CHECK ERR BIT IN ATA STATUS REGISTER // * Returns 1 if error occured during last command byte ata_err(void) { byte word_read; word_read = ata_read_register(ATA_REG_STATUS); if(word_read & ATA_STATUS_BUSY) return 0; else if(word_read & ATA_STATUS_ERR) return 1; else return 0; } // * READ ATA DATA // * Returns a word from the data register word ata_read_word(void) { word ata_word_read; DATA_BUS_DIR_IN; ATA_CNTRL = ATA_REG_DATA; ATA_CNTRL &= ~DIOR; TWO_NOPS; ata_word_read = DATA_BUS_HIGH_IN; ata_word_read <<= 8; ata_word_read |= DATA_BUS_LOW_IN; ATA_CNTRL |= DIOR; ATA_CNTRL = ATA_REG_HIZ;


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return ata_word_read; } // * READ ONE SECTOR // * Reads one LBA-addressed sector to PC via USART and returns an error code if any byte ata_read_sector(dword lba) { byte i,j; //word word_read; printf("\r\n\r\n SECTOR: %u\r\n",lba); // 28-bit LBA address lba += 63; //There are 63 sectors before boot sector which we discount lba &= 0x0FFFFFFF; // Write bits 27 - 24 of LBA address to device head register while(!drdy); ATA_CNTRL = ATA_REG_DEVICEHEAD; ata_write_byte((lba >> 24) | ATA_DEVICEHEAD_DEV0); while(!drdy); ATA_CNTRL = ATA_REG_CYLINDERHIGH; ata_write_byte(lba >> 16); while(!drdy); ATA_CNTRL = ATA_REG_CYLINDERLOW; ata_write_byte(lba >> 8); while(!drdy); ATA_CNTRL = ATA_REG_SECTORNUM; ata_write_byte(lba); // Write 1 to Sector count register (indicates only reading 1 sector) while(!drdy); ATA_CNTRL = ATA_REG_SECTORCNT; ata_write_byte(1); // Issue read sector command to command register ata_write_cmd(ATA_CMD_READ_SECTORS); // Read the sector (512 bytes = 16 x 16 words) while(!drq); for (i = 0; i < 16; i++) { for(j = 0; j < 16; j++) { //word_read = ata_read_word(); printf("%X ",ata_read_word()); //printf("%c%c",(word_read & 0x00FF),(word_read >> 8)); } printf("\r\n"); } while(busy); return(err); } // * READ ONE SECTOR TO SRAM // * Reads one LBA-addressed sector into a page of SRAM and returns an error code if any byte ata_read_sector_sram(dword lba, word page) { word i, sram_address; // 28-bit LBA address lba += 63; //There are 63 sectors before boot sector which we discount lba &= 0x0FFFFFFF; // Write bits 27 - 24 of LBA address to device head register while(!drdy); ATA_CNTRL = ATA_REG_DEVICEHEAD; ata_write_byte((lba >> 24) | ATA_DEVICEHEAD_DEV0); while(!drdy); ATA_CNTRL = ATA_REG_CYLINDERHIGH; ata_write_byte(lba >> 16);


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while(!drdy); ATA_CNTRL = ATA_REG_CYLINDERLOW; ata_write_byte(lba >> 8); while(!drdy); ATA_CNTRL = ATA_REG_SECTORNUM; ata_write_byte(lba); // Write 1 to Sector count register (indicates only reading 1 sector) while(!drdy); ATA_CNTRL = ATA_REG_SECTORCNT; ata_write_byte(1); // Issue read sector command to command register ata_write_cmd(ATA_CMD_READ_SECTORS); // Calculate actual SRAM 16-bit address from given page number // For page number greater than 255, we loop it back around the memory like a ring buffer if(page > 255) { page %= 256; } sram_address = page * 256; // Read the sector to sram page(1 page = 256 words = 512 bytes) while(!drq); for (i = 0; i < 256; i++) { DATA_BUS_DIR_OUT; DATA_BUS_HIGH_OUT = sram_address >> 8; DATA_BUS_LOW_OUT = sram_address & 0x00FF; SRAM_LATCH; // Write data to latched address location DATA_BUS_DIR_IN; ATA_CNTRL = ATA_REG_DATA; ATA_CNTRL &= ~DIOR; TWO_NOPS; SRAM_ON; SRAM_WRITE; SRAM_OFF; ATA_CNTRL |= DIOR; ATA_CNTRL = ATA_REG_HIZ; sram_address++; } while(busy); return(err); } // * READ ONE SECTOR // * Reads one LBA-addressed sector to internal SRAM and returns an error code if any byte ata_read_sector_buffer(dword lba, byte *buffer) { word i, word_read; // 28-bit LBA address lba += 63; //There are 63 sectors before boot sector which we discount lba &= 0x0FFFFFFF; // Write bits 27 - 24 of LBA address to device head register while(!drdy); ATA_CNTRL = ATA_REG_DEVICEHEAD; ata_write_byte((lba >> 24) | ATA_DEVICEHEAD_DEV0); while(!drdy); ATA_CNTRL = ATA_REG_CYLINDERHIGH; ata_write_byte(lba >> 16); while(!drdy); ATA_CNTRL = ATA_REG_CYLINDERLOW; ata_write_byte(lba >> 8); while(!drdy); ATA_CNTRL = ATA_REG_SECTORNUM;


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ata_write_byte(lba); // Write 1 to Sector count register (indicates only reading 1 sector) while(!drdy); ATA_CNTRL = ATA_REG_SECTORCNT; ata_write_byte(1); // Issue read sector command to command register ata_write_cmd(ATA_CMD_READ_SECTORS); // Read the sector (512 bytes = 256 words) while(!drq); for (i = 0; i < 256; i++) { word_read = ata_read_word(); buffer[i*2] = word_read & 0x00FF; // Low byte buffer[i*2+1] = word_read >> 8; // High byte } while(busy); return(err); } // * READ ONE SECTOR TO SRAM // * Reads one LBA-addressed sector into a page of SRAM and returns an error code if any byte ata_read_cluster_sram(dword cluster_no, word sram_page) { byte result, count; for(count = 0; count < SecPerClus; count++) { result = ata_read_sector_sram(FirstSectorofCluster(cluster_no)+count, sram_page+count); } return(result); }


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Appendix L1: Firmware (keypad.h)

/************************************************************* THE UNIVERSITY OF QUEENSLAND BACHELOR OF ENGINEERING (EE) 2003 SEMESTER 2 ENGG4801 THESIS PROJECT Project: Storage and User Interface for Digital Turntable Supervisor: Dr Peter Sutton Author: William Wai-Luen Wong StudentID: 33633134 Email: [email protected] Code Name: keypad.h Code Description: Header file for keypad.c **************************************************************/ // * EXTERNAL FUNCTION PROTOTYPE extern void keypad_scan(void); // * MACRO DEFINITIONS // Keypad #define clear_column PORTB &= ~(BIT6 | BIT5 | BIT4); #define COL1 PORTB |= BIT4; #define COL2 PORTB |= BIT5; #define COL3 PORTB |=BIT6;

Appendix L2: Firmware (keypad.c)

/************************************************************* THE UNIVERSITY OF QUEENSLAND BACHELOR OF ENGINEERING (EE) 2003 SEMESTER 2 ENGG4801 THESIS PROJECT Project: Storage and User Interface for Digital Turntable Supervisor: Dr Peter Sutton Author: William Wai-Luen Wong StudentID: 33633134 Email: [email protected] Code Name: keypad.c Code Description: Keypad scan on columns **************************************************************/ #include "keypad.h" void keypad_scan(void) { clear_column; switch (last_column) { case 1: // Scan COLUMN 2 COL2; last_column++; break; case 2: // Scan COLUMN 1 COL1; last_column = 1; break; /*case 3: // Scan COLUMN 1 COL1; last_column = 1; break;*/ default: break; } }


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CHAPTER 10:

References

10.0 REFERENCES

[1] Pioneer Electronics Australia Pty Limited. “Professional DJ Audio Products”. <http://www.car.pioneeraus.com.au/prodj/home/index.htm>, 22 September 2003. [2] Pioneer Corporation. “Press Release – June 12, 2003, Tokyo”. <http://www.pioneer.co.jp/press/release118.html>, 22 September 2003. [3] Stanton Group. “Final Scratch”. <http://www.finalscratch.com>, 14 April 2003. [4] Denon Electronics. “Denon DN-S5000 Digital Turntable”. <http://www.usa.denon.com/catalog/products.asp?l=3&c=31>, 25 September 2003. [5] Pioneer Electronics Australia Pty Limited. “Pioneer DMP-555”.

<http://www.car.pioneeraus.com.au/prodj/products/dmp-555/>, 25 September 2003. [6] Viewz. “Removable Storage Guide – Flash Memory”. <http://www.viewz.com/aol/guides/storage7a.shtml>, 25 September 2003. [7] Sonic State Ltd. “Numark Turntable plays CDs”.

<http://www.sonicstate.com/news/shownews.cfm?newsid=1157>, 25 September 2003. [8] DanceFrontDoor. “Technics SL-DZ1200 Digital DJ CD Player”.

<http://www.dancefrontdoor.co.uk/article1464.html>, 26 September 2003. [9] Microchip Technology. “PIC16 Microcontroller Family”. <http://www.microchip.com/1010/pline/picmicro/family/pic16/index.htm>,

28 May 2003. [10] UQ ITEE. “Atmel AVR Resources”.

<http://www.itee.uq.edu.au/~comp1300/pracs/Atmel_AVR_Resources/index.html>, 28 July 2003.

[11] Atmel Corporation. “ATmega128 Microcontroller Datasheet”. <http://www.atmel.com/dyn/resources/prod_documents/doc2467.pdf>, 28 July 2003. [12] POLYkom. “POLYkom online provider”.

<https://www.polykom.com/index.cfm>, 5 August 2003. [13] Payne, Len. “AVR8515 Project Board and STK200 Dongle Schematics”.

<http://www.itee.uq.edu.au/~comp1300/pracs/Atmel_AVR_Resources/AVR_Project_Board.pdf>, 5 August 2003.

[14] Maxim Integrated Products. “MAX220-MAX249 Line Drivers Datasheet”.

<http://pdfserv.maxim-ic.com/en/ds/MAX220-MAX249.pdf>, 5 August 2003. [15] FarnellinOne. “Farnell Australia Distributors”.

<http://international2.farnell.com/Welcome/welcomeforeign.jhtml?countryCode=en_AU>, 8 August 2003.


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[16] RS Components. “RS Components Catalogue”. <http://au.rs-c.dk/search/text_search_frames.html>, 8 August 2003. [17] ITEE. “Electronics Workshop”.

<http://www.itee.uq.edu.au/~ews>, 12 August 2003. [18] Fleischmann, Stefan. “WinHex” <http://www.winhex.com>, 30 September 2003.

Bibliography

[18] “Information Technology – AT Attachment-3 Interface”

<http://www.ata-atapi.com>, 28 July 203.

[19] Microsoft Coporation. “FAT: General Overview of On-Disk Format”.

<http://www.microsoft.com>, 20 August 2003.

[19] Eady, Fred. “Construct an ATA Hard Drive Controller”.

<http://www.circuitcellar.com/library/print/0103/Eady150/index.htm>, 11 May 2003. [20] “Table of ASCII Characters”. <http://web.cs.mun.ca/~michael/c/ascii- table.html>, 19 September 2003.

Documents

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