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STMicroelctronicsSTMicroelctronics
Laroussi Bouzaida Central R&D/ Test Solutions Department MgrCrolles - France
STIL-based D2T FlowSTIL-based D2T Flow
L. Bouzaida STIL Flow Oct’2002
Why STIL in our D2T flowWhy STIL in our D2T flow
Use standard, vendor independent format
Already generated by most of ATPG Allows to:
– Reduce the D2T turn-around– Optimize the test development flow
Enables easier communication between EDA and ATE environments (LCT Initiative)
L. Bouzaida STIL Flow Oct’2002
Supported featuresSupported features
ST/D2T supports Synopsys/TetraMAX Patterns: IEEE Std.1450-1999 and P1450.1 extension Basic features
– Signals block– SignalGroups block– Timing section– Pattern Burst– Pattern– Spec section
Other Features– Scan Structures section – Procedures and Macros– Call and Macro
statements– Shift block– Condition statement– Vectors data mapping
(WFCmap)
L. Bouzaida STIL Flow Oct’2002
STIL to ATE flowSTIL to ATE flow
Design Infos (Netlist, IO Library)
STILTetraMAX
Design Infos (Netlist, IO Library)
TetraMAX STIL
Design Infos (Netlist, IO Library)
STILSimulation,Other ATPG
WGLVCD
…
L. Bouzaida STIL Flow Oct’2002
STIL/WGL performancesSTIL/WGL performances
Patterns processing significantly reduced with STIL versus WGL format
Up to 50% processing time saving with STIL
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Circuit2 Circuit3 Circuit4
WGL(KS)STIL(KS)WGL(ES)STIL(ES)
L. Bouzaida STIL Flow Oct’2002
STIL to ATE usageSTIL to ATE usage
L. Bouzaida STIL Flow Oct’2002
Current activityCurrent activity
STIL reader and writer available in D2T/XUtile production release
On going work with EDA and ATE companies to reduce the test development flow (direct STIL reading). Some application are emerging with Low Cost ATEs
Extension to support full standard features:– Patterns List and Patterns Exec– Domain names – Include– Break Point
L. Bouzaida STIL Flow Oct’2002
ConclusionsConclusions
STIL patterns format support and deployment within ST Divisions
We see a significant process time reduction even if STIL is considered as a “classical”vector format
Coordination between EDA environment and users (like ST) to be aligned regarding the supported features
