STM32 Seminar STM32F2 High-Performance - Компэлcompel.ru/wordpress/wp-content/uploads/2011/12/2-STM32F2-CM3-Hi… · STM32 Seminar STM32F2 High-Performance COMPEL/STM Seminar

STM32 Seminar STM32F2 High-Performance

COMPEL/STM SeminarNov/Dec 2011Nov/Dec 2011

STM32 F2 Series highlights 1/2STM32 F2 Series highlights 1/2

Advanced technology and process from ST:Advanced technology and process from ST:Memory accelerator: ART Accelerator™Multi AHB Bus MatrixMulti AHB Bus Matrix90nm process

Outstanding results:150DMIPS at 120MHz Execution from Flash equivalent to 0-wait state performanceq pOutstanding dynamic power consumption: 188uA/MHz, less than 23mA in run mode from flash at 120MHz with peripherals OFF (running CoreMark benchmark).

STM32 Seminar Nov/Dec 20112

STM32 F2 Series highlights 2/2STM32 F2 Series highlights 2/2

More MemoryyUp to 1MB Flash, up to 128kB SRAM

New peripherals in the STM32 platformUSB OTG High speed 480Mbit/sCamera interfaceCrypto/hash processor32-bit random number generator (RNG)32 bit random number generator (RNG)32-bit RTC with calendar32bit Timers32bit Timers


STM32 F2 block diagram

Cortex M3 with MPU and Trace running at 120 MHzTrace running at 120 MHz

ART Accelerator TM and multi-level AHB Bus Matrix

1.65 to 3.6V Supply

1-MByte Flash 128-KByte1-MByte Flash, 128-KByte SRAM

4 Kbytes back up SRAM

Ethernet, 2xUSB OTG with High Speed support, camera interfaceinterface

Crypto/Hash processor

True random number generator

Fast ADC 2MSPS


Fast ADC 2MSPS

STM32 F2 Series product lines

Notes:

1. HS requires an external PHY connected to ULPI interfaceinterface

2. Crypto/hash processor on STM32F217x and STM32F215x

3. 1.65 V for WLCSP64 package only and 1.8 V for all other packages


STM32 F2 series portfoliop


Real Time performanceReal Time performance


High-performance enhancementsg p

A performance that cannot be outperformed: pe o a ce t at ca ot be outpe o ed150DMIPS at 120MHz

The Adaptive Real Time “ART” Accelerator allows to executeThe Adaptive Real Time ART Accelerator allows to execute code from flash with a performance equivalent to 0 wait-state at 120MHz, making the STM32 F2 among the fastest Cortex gM3 MCU on the market with 150DMIPS at 120MHz!

No Cortex M3 microcontroller can offer more performance in the future in terms or DMIPS/MHz. The only possible improvement

ill f CPU f iwill come from CPU frequency increase.


ART Accelerator in detail

Prefetch queue and branch cache principleq p pStores the first instructions and constants of branch and interrupt eventsPushes them to the prefetch queue the next time they occur, with no execution

ltpenalty


The proof by 250

STM32F2xx(228.6@ 120MHz+30% vs LPC1768

CoreMark[Iter/Sec]

200EEMBC Coremark v1.0 score

+30% vs LPC1768STM32F2xx(190.30@ 100MHz)+8% vs LPC1768

150

LPC1768(175.25@100MHz)

PIC32(183.68@80MHz)

PIC32100 PIC32(77.97@30MHz)

PIC24ColdFire

(62.28@60MHz)CortexR4

50(74.48@40MHz)

(6 . 8@60 )

CortexM0(33.77@24MHz)

(52@24MHz)

Go to www.coremark.org

0

M16(11.208@24MHz) to access the scores


MHz

32-bit multi-AHB bus matrix


Dual RAM

The 128KB of SRAMThe 128KB of SRAM is made of 2 blocks of SRAM one 112KBSRAM, one 112KB and one 16KBBoth can be accessed simultaneously by 2 y ymasters in 0 WS

CPU Th 16KB b d b ffCPUDMAsEth t

The 16KB can be used as a buffer for high speed peripherals like USB-HS, Ethernet, Camera,Ethernet

USB HS

USB HS, Ethernet, Camera, without impacting the CPU

performance


Outstanding power efficiencyOutstanding power efficiency


Outstanding power efficiencyg p y188 μA/MHz, 22.5 mA at 120 MHz executing from Flash memory. Thannks to:Thannks to:

ST’s 90 nm process allowing the CPU core to run at only 1.2 VART Accelerator™ reducing the number of accesses to Flash

Additional contributions to power efficiency:Backup mode: ~3µA with RTC on, ~1uA with 4-Kbyte backed up SRAM,Backup mode: 3µA with RTC on, 1uA with 4 Kbyte backed up SRAM, ~4uA with both on

Standby mode current (typ)= 2uA (RTC OFF, backup SRAM OFF), 5uAStandby mode current (typ) 2uA (RTC OFF, backup SRAM OFF), 5uA (RTC ON, backup SRAM ON)

Separate 1 2VDD input option (on WLCSP and BGA packages) for theSeparate 1.2VDD input option (on WLCSP and BGA packages) for the core: allows to benefit from external high efficiency switch mode regulator.

VDD min down to 1.65 V (on WLCSP package only), 1.8V on other packages


Superior and innovative peripheralsperipherals


New IPNew Peripheral

Communication Peripherals

USB 2.0 ON-THE-GO HIGH SPEED (OTG HS)SPEED (OTG HS)


Main Features

Fully compatible (@ register level) with the full-speed USB OTG peripheral

High-speed (480 Mbit/s), full-speed and low speed operation in host mode and High-speed/Full-speed in d i ddevice mode

Three PHY interfacing optionsInternal full-speed PHY (as for FS peripheral)I2C i t f f f ll d I2C PHYI2C interface for full-speed I2C PHYULPI bus interface for high-speed PHY

DMA support with a dedicated FIFO of 4Kbytes


Device mode Features

USB DEVICE: Same as Full-speed mode with some pextended/new features:

Up to 5 IN bulk, interrupt or isochronous endpoints (Vs 3 in FS)Up to 5 OUT bulk, interrupt or isochronous endpoints (Vs 3 in FS)Separate NVIC interrupt vector for EP1_INSeparate NVIC interrupt vector for EP1_OUT

USB HOST:Same as Full-speed mode features

Up to 12 channels (Vs 8 channels in FS peripheral)

High-speed protocol specific featuresPING protocolSPLIT protocolpMulti-transaction


ULPI High Speed PHY connectiong p


New IP

DIGITAL CAMERA INTERFACE(DCMI)(DCMI)


DCMI FeaturesThe Digital Camera Interface offers:

8-, 10-, 12- or 14-bit parallel interface, , pContinuous or snapshot modeCrop featureSupports the following data formats:

8/10/12/14- bit progressive scan: either monochrome or raw bayerbayerYCbCr 4:2:2 progressive scanRGB 565 progressive videop gCompressed data: JPEG

With a 48MHz PIXCLK and 8-bit parallel input data interface it isWith a 48MHz PIXCLK and 8 bit parallel input data interface it is possible to receive:

up to 15fps uncompressed data stream in SXGA resolution (1280 1024) ith 16 bit i l(1280x1024) with 16-bit per pixelup to 30fps uncompressed data stream in VGA resolution (640x480) with 16-bit per pixel


(640x480) with 16 bit per pixel

DCMI Block DiagramgThe digital camera interface is a synchronous parallel interface that can receive data flows, It consists of:co s s s o

up to 14 data lines DCMI_D[0..13]Pixel clock line DCMI_PIXCLK with a programmable polarity, rising/falling edge. The maximum AHB/PIXCLK ratio =2.5 (PIXCLK=48MHz max)Horizontal synchronization DCMI_HSYNC, indicates the start/end of a lineVertical synchronization DCMI_VSYNC, indicates the start/end of a frame

Five interrupts flags, 1 global interrupt line DCMI

DCMI_D[0..13]

DCMI PIXCLK

DCMI Interrupt to NVICDCMI Request to DMA

Five interrupts flags, 1 global interrupt lineIT_LINE Indicates the end of lineIT_FRAME Indicates the end of frame captureIT_OVR indicates the overrun of data reception

DCMI_PIXCLK

DCMI_HSYNC

DCMI VSYNCHB

Bus

IT_VSYNC Indicates the synchronization frameIT_ERR Indicates the detection of an error

in the embedded synchronization frame detection

DCMI_VSYNCAH


DCMI CROP featureThe DCMI interface supports two types of capture: The DCMI can select a rectangular window from the received imageThe start coordinates and size are specified using two 32-bit registers DCMI_CWSTRT and DCMI_CWSIZE. The size of the window is specified in number of pixel clocks (horizontal dimension) and in number of lines (vertical dimension)

Horizontal offset count

Vertical start line count

ount

ical

line

co

Vert

Capture count


Camera to LCD Data transferLCDSTM32F2xx

FSMC

DMA

C

DCMIDCMI_PIXCLK

DCMI_D[0..13]Camera

DCMI DCMI_HSYNCDCMI_VSYNC

The data are packed into a 32-bit data register (DCMI_DR) and then transferred through a general-purpose DMA channel. The DMA can store the transferred data into internal SRAM or into External memory interfaced with theThe DMA can store the transferred data into internal SRAM or into External memory interfaced with the FSMC and then displayed on the LCD.All the transfer is done through the DMA with 0% CPU load.


New IP

C O O SENCRYPTION MODULES


Crypto/Hash Processor and RNGyp

Encryption/Decryptionyp ypDES/TDES (data encryption standard/triple data encryption standard): ECB (electronic codebook) and CBC (cipher block chaining) chaining algorithms, 64-,128- or 192-bit keyAES (advanced encryption standard): ECB, CBC and CTR (counter mode) chaining algorithms 128 192 or 256 bit key(counter mode) chaining algorithms, 128, 192 or 256-bit key

Universal hashSHA 1 ( h h l ith )SHA-1 (secure hash algorithm)MD5

T d b t (RNG) th t d li 32True random number generator (RNG) that delivers 32-bit random numbers produced by an integrated analog circuitcircuit.


New IP

C OG C OC SSOCRYPTOGRAPHIC PROCESSOR (CRYP)(CRYP)


CRYP algorithms principleg p p

Sender has the message to be sent the secret key (symmetric)

Receiver has

Clear Data

Receiver has the secret key

S d R iSender Receiver

ClearData

EncryptedDataCipher

Clear Data

EncryptedData DeCipher

Symmetric key

Symmetric key


key key

CRYP Features (1/2)

Suitable for AES, DES and TDES enciphering and deciphering operations

Runs at the same frequency as the CPU, up to 120 MHz.q y , p

DES/TDESDirect implementation of simple DES algorithms (a single key K1 is used)Direct implementation of simple DES algorithms (a single key, K1, is used)

Supports the ECB and CBC chaining algorithms

S t 64 128 d 192 bit k (i l di it )Supports 64-, 128- and 192-bit keys (including parity)

64-bit initialization vectors (IV) used in the CBC mode

16 HCLK cycles to process one 64-bit block in DES

48 HCLK cycles to process one 64-bit block in TDES


CRYP Features (2/2)AES

Supports the ECB, CBC and CTR chaining algorithms

Supports 128-, 192- and 256-bit keys

128-bit initialization vectors (IV) used in the CBC and CTR modes

14, 16 or 18 HCLK cycles (depending on the key size) to transform one 128-bit block in AES

Common to DES/TDES and AESIN and OUT FIFO (each with an 8-word depth, a 32-bit width, corresponding to 4 DES blocks or 2 AES blocks)p g )

Automatic data flow control with support of direct memory access (DMA) (using 2 channels, one for incoming data the other for processed data)( g , g p )

Data swapping logic to support 1-, 8-, 16- or 32-bit data


CRYP algorithms overview g

AES DES TDES

64* bits 192***, 128** or 64* bitsKey sizes 128, 192 or 256 bits

* 8 parity bits

* 8 parity bits : Keying option 1** 16 parity bits: Keying option 2***24 parity bits: Keying option 3

Block sizes 128 bits 64 bits 64 bits

Time to process one block

14 HCLK cycle for key = 128bits



16 HCLK cycles 48 HCLK cyclesy y

Type block cipher block cipher block cipher

Structure Substitution-permutation network Feistel network Feistel networknetwork

First published 1998 1977 (standardized on January 1979) 1998 (ANS X9.52)


CRYP Block DiagramgDMA request for incoming d t t f

DMA request for outgoing data transfer

Key: 128-, 192- and 256-bit

AES ECB CBC CTRdata transfer data transfer

Key: 64- 128- and 192-bit

TDES

O FOappi

ng

appi

ngECB CBCKey: 64 , 128 and 192 bit

DESput F

IF

tput

FIF

Dat

a sw

a

Dat

a sw

a

ECB CBCKey: 64-bit

CRYPTO Processor

In

OutD D

FlagsBUSY OFFU OFNEIFNFIFEM OUTRISINRIS BUSY OFFU OFNEIFNFIFEM OUTRISINRIS

OUTIMINIM OUTMISINMIS


CRYPTO Global interrupt

(NVIC)

CRYP throughputg pThroughput in MB/s at 120 MHz for the various algorithms and

implementationsimplementations

AES-128 AES-192 AES-256 DES TDESHW

Theoretical 137.14 120.00 106.67 60.00 20.00HW Without

DMA 51.89 51.89 44.65 30.97 11.43HW With

DMA 128.00 120.00 106.67 60.00 20.00P SW 0 99 0 82 0 69 0 53 0 18Pure SW 0.99 0.82 0.69 0.53 0.18


New IP

SHASH PROCESSORPROCESSOR


HASH Function Definition

arbitrary block of data

fixed size bit stringMessage

(data to be encoded)

fixed-size bit string

DigestHash function( )

Interesting property of HASH Function: Small change on Message=> big change in Digestnot reversible!


HASH Applicationspp

Verifying the integrity of files or messagesCompare the HASH before and after transmission

Verifying the authenticity of files or messagesSignature: Sign the HASH of a messageR i h k i t d th HASH t th ti itReceiver check signature and the HASH to ensure authenticity

“One Way Encryption”:One-Way-Encryption :Password stored as HASH value, not plain textTo check password => compare the HASHsTo check password compare the HASHs


HASH Main FeaturesSuitable for Integrity check and data authentication applications, compliant with:p

FIPS PUB 180-2 (Federal Information Processing Standards Publication 180-2)S H h S d d ifi i (SHA 1)Secure Hash Standard specifications (SHA-1)IETF RFC 1321 (Internet Engineering Task Force Request For Comments number 1321) specifications (MD5)number 1321) specifications (MD5)

AHB slave peripheralp pFast computation of SHA-1 and MD5 :

66 HCLK clock cycles in SHA-150 HCLK clock cycles in MD5

5 × 32-bit words (H0, H1, H2, H3 and H4) for output message digest, reload able to continue interrupted message digest computation


HASH Block DiagramgDMA request

HASH

MD5 SHA-1

O appi

ngMessage

Digestt

put F

IF

Dat

a sw

a

HMAC

Digest

H0..H45x32bit6

x 32

bi

HASH Processor

In D 5x32bit1

FlagsBUSY DMAS DCISDINIS FlagsBUSY DMAS DCISDINIS

DCIM

DINIM


HASH Global interrupt

(NVIC)

DINIM

HASH throughputThroughput in MB/s at 120 MHz for SHA-1 and MD5 algorithms with

different implementations

g p

different implementations

MD5 SHA1

HW Theoretical 116.36 93.66

HW Without DMA 55.25 51.20

HW With DMA 75.29 65.08

Pure SW 8.23 3.68


Crypto/Hash Performance Summaryyp yThroughput at 120 Mhz for the various algorithms and implementations

Throughput @ 120 Mhz

120.00

140.00

80.00

100.00

/s

40.00

60.00MB

/

0 00

20.00

0.00AES-128 AES-192 AES-256 DES TDES MD5 SHA1 RNG

HW Theoretical HW Without DMA HW With DMA Pure SW


New IP

O G ORANDOM NUMBER GENERATOR (RNG)(RNG)


RNG Features32-bit random numbers, produced by an analog generator (based on a continuous analog noise)continuous analog noise)Clocked by a dedicated clock (PLL48CLK)40 periods of the PLL48CLK clock signal between two consecutive random numbersCan be disabled to reduce power-consumptionProvide a success ratio of more than 85% to FIPS 140 2 (FederalProvide a success ratio of more than 85% to FIPS 140-2 (Federal Information Processing Standards Publication 140-2) tests for a sequence of 20 000 bits.5 Flags

1 flag occurs when Valid random Data is ready2 Flags to an abnormal sequence occurs on the seed2 Flags to an abnormal sequence occurs on the seed. 2 flags for frequency error (PLL48CLK clock is too low).

1 interruptT i di t ( b l f )To indicate an error (an abnormal sequence error or a frequency error)


RNG Block DiagramgRNG_CLKRNG_CLK

RNGError management

LFSR(Linear Feedback

Shift register)

32bit random data register

Clock checker

Fault detector

Analog Seed

FlagsInterrupt enable bit IM DRDY CEISSEISSECS CECS

RNG interrupt to NVIC


New IPNew IP

( )System Peripherals

REAL-TIME CLOCK (RTC)


RTC FeaturesCalendar with seconds, minutes, hours, week day, date, month, and year.Daylight saving compensation programmable by softwareDaylight saving compensation programmable by softwareA second clock source (50 or 60Hz) can be used to update the calendar. Digital calibration circuit (periodic counter correction) to achieve 5 ppmg (p ) ppaccuracy20 backup registers (80 bytes) which are reset when an tamper detection event occursevent occurs.

Inputs:pAFO_CALIB: 512 Hz clock output (with an LSE frequency of 32.768 kHz). AFO_ALARM: Alarm A or Alarm B or wakeup

Inputs:AFI_TAMPER: tamper event detection.AFI TIMESTAMP: timestamp event detectionAFI_TIMESTAMP: timestamp event detection

STM32 Seminar Nov/Dec 2011 47

RTC Block DiagramgAFI_TAMPER

AFI_TIMESTAMP

Backup Registers and RTC TamperControl registers

TimeStamp Registers

TimeStamp Flag

Tamper Flag

RTC Reference

Alarm AAFO_CALIB512 Hz clock outputRTCSEL [1:0]

TimeStamp FlagRTC Reference Clock

A h

= Alarm A Flagss, mm, HH/date

HSE (1 MHz)

LSE

LSI

RTCCLK

Asynchronous 7bit Prescaler Calendar RTC_CR_OSEL[1:0]

PREDIV_A [6:0]

AFO_ALARM Day/date/month/year HH:mm:ss

(12/24 format)Calibration

= Alarm B

Synchronous 13bit Prescaler

PREDIV_S [12:0]

Alarm B Flag

Alarm B

ss, mm, HH/date

Wake-Up

16bit autoreload

Asynchrone 4bit Prescaler

Periodic wake up


TimerPeriodic wake up

FlagWUCKSEL [2:0]

Improved IPs

FURTHER IMPROVMENTS


STM32 F2 System Improvement

Low voltage: 1.8V to 3.6V VDD , down to 1.65V on one packageMore flexible remapping of the peripheral to the pinspp g p p pUp to 140 GPIOS4KB backup SRAM: can be used as “EEPROM”pAdditionnal Clock-Out Capability (MCO2)Independant output for CPU & USB clocksp p


More peripherals improvementsp p p

Flexible Static Memory Interface for external LCD, y ,SRAM, PSRAM, NOR and NAND Flash, CompactFlashto expand memory space or support an external display:

running at up to 60MHz

remap capability on I/D code busses to increase p p yexecution performance

3 SPIs running at up to 30 Mbit/s,3 SPIs running at up to 30 Mbit/s, 6 USARTs running at up to 7.5Mbit/sFast GPIO (60 MHz toggling speed)Fast GPIO (60 MHz toggling speed)


ADC Improvements3 ADCs : ADC1 (master), ADC2 and ADC3 (slaves).

Maximum frequency of the ADC analog clock is 30MHzMaximum frequency of the ADC analog clock is 30MHz.

12-bits, 10-bits, 8-bits or 6-bits configurable resolution.

ADC i t ith 12 bit l ti i tADC conversion rate with 12 bit resolution is up to:2 M.sample/s in single ADC mode,

3 75 M sapmle/s in dual interleaved ADC mode3,75 M.sapmle/s in dual interleaved ADC mode,

6 M.sample/s in Triple interleaved ADC mode.

Conversion range: 0 to 3.6 V.ADC supply requirement: VDDA = 2.4V to 3.6V at full speed and down to 1.65V at lower speed.

Up to 24 external channels.

3 ADC1 internal channels connected to:Temperature sensor,

Internal voltage reference : VREFINT (1.2V typ),


VBAT for internal battery monitoring.

Total Conversion Time

Total conversion Time = TSampling + TConversionSampling Conversion

Resolution TConversion

12 bits 12 Cycles12 bits 12 Cycles10 bits 10 Cycles8 bits 8 Cycles

With Sample time= 3 cycles @ ADC CLK = 30MHz total conversion time is equal

8 bits 8 Cycles6 bits 6 Cycles

p y @ _ qto :

resolution Total conversion Time

12 bits 12 + 3 = 15cycles 0.5 us 2 Msps

10 bits 10 + 3 = 13 cycles 0.433 us 2.30 Mspsp

8 bits 8 + 3 = 11 cycles 0.366 us 2.72 Msps

6 bits 6 + 3 = 9 cycles 0 3 us 3 33 Msps


6 bits 6 + 3 = 9 cycles 0.3 us 3.33 Msps

ADC conversion in single mode (12 bit resolution)

SamplingSampling

C iC i

1st sample1st sample 2nd sample2nd sample 3td sample3td sample

3ConversionConversion

12 3 12ADC1ADC1

+2+2This channel is sampled This channel is sampled

each 15 ADC CLK each 15 ADC CLK cyclescyclescycles.cycles.

The sampling speed in The sampling speed in this case is equal to: this case is equal to:

0030MHz/15 = 30MHz/15 = 2Msps2Msps

--22

With 30MHz is the With 30MHz is the maximum ADC CLK in maximum ADC CLK in STM32F2xx product.STM32F2xx product.

STM32 Seminar Nov/Dec 201133 ADC_CLKADC_CLK66 99 1212 1515 1818 2121 2424 2727 3030

ADC conversion in Triple Interleaved mode (12 bit resolution)

3 SamplingSampling

ConversionConversion

12

1st sample1st sample

2nd sample2nd sampleADC1ADC1 3 12

4th sample4th sample

5th sample5th sample ConversionConversion

3 12pp

3d sample3d sample

3 12

3 12

ADC2ADC2

ADC3ADC3



3 12

This channel is sampledThis channel is sampled

5 Cycle5 Cycle

3 12

55 55 55 55

3 12

+2+2This channel is sampled This channel is sampled

each 5 ADC CLK each 5 ADC CLK cycles.cycles.

Th li d iTh li d i

00

The sampling speed in The sampling speed in this case is equal to: this case is equal to:

30MHz/5 30MHz/5 = = 6Msps6Msps

--22

pp

With With 30MHz 30MHz is the is the --22maximum ADC CLK in maximum ADC CLK in STM32F2xx STM32F2xx product.product.

55 1515 25251010 2020

STM32 Seminar Nov/Dec 201133 ADC_CLKADC_CLK66 99 1212 1515 1818 2121 2424 2727 3030

55 1515 25251010 2020

55

STM32F2xx Timer features overview

Counter resolution

Counter typePrescaler factor

DMACapture CompareChannels

Complementaryoutput

Synchronization

Master Config

Slave Config

AdvancedTIM1 and TIM8

16 bitup, down and up/down

1..65536 YES 4 3 YES YES

General purpose (1)TIM2 and TIM5


1..65536 YES 4 0 YES YESTIM2 and TIM5 up/down

General purposeTIM3 and TIM4


1..65536 YES 4 0 YES YES

BasicsBasicsTIM6 and TIM7

16 bit up 1..65536 YES 0 0 YES NO

1 Channel (2)TIM10..11 and 16 bit up 1..65536 NO 1 0

YES(OC signal)

NOTIM13..14 (2)

signal)

2 Channel(2)TIM9 and TIM12

16 bit up 1..65536 NO 2 0 NO YES

(1) New 32-Bit Timers(2) These Timers are identical to XXL Timers


Features overviewGeneral Purpose Feature16/32-bit Counter

Auto Reload ITR 1 Trigger/ClockClockETR

Auto ReloadUp, down and centered counting

modes4x 16 High resolution Capture Compare channels

Programmable direction of the channel: input/output

ControllerTrigger Output

ITR 2ITR 3ITR 4

Programmable direction of the channel: input/outputOutput Compare: Toggle, PWMInput CapturePWM Input Capture

Synchronization

16-Bit Prescaler

SynchronizationUp to 8 IT/DMA RequestsMotor Control Specific FeatureOC Signal Management

6 C l

Auto Reload REG+/- 16/32-Bit Counter

6 Complementary outputs Dead-time management Repetition Unit

Encoder Interface

CH1CH1N

CH2Capture CompareC C

CH1

Hall sensor InterfaceEmbedded Safety features

Break sources: BKIN pin/ CSSLockable unit configuration

CH2CH2N

CH3CH3N

p pCapture Compare

Capture CompareCapture Compare

CH2

CH3

CH4 CH3NCH4

BKIN

CH4


Audio architectureTwo PLLs are available for more flexibilty of the system:system:

The main PLL (PLL) clocked by HSI or HSE used to generate the System clock (up to 120MHz), and 48 MHz l k f USB OTG FS SDIO d RNGclock for USB OTG FS, SDIO and RNG.

A dedicated PLL (PLLI2S) used to generate an accurate clock to achieve high-quality audio performance on the I2Sclock to achieve high quality audio performance on the I2S interface.

2xI2S peripherals with:Less than 0.5% error on sampling frequencyCl k i t i t l hi h lit di PLL iClock input in case an external high quality audio PLL is needed


Clock Scheme – I2S PLL 32.768KHz /2, to 31

LSE OScOSC32_IN

OSC32_OUT

32KH

RTCCLKHSE

/8 SysTickLSI RC

~32KHz IWDGCLK

TIM5 IC4

PCLK1 up to 30MHz

HCLK up to 120MHz

/8 SysTick

CSSHSI RC

16MHz

HSI

If (APB1 pres =1) x1

Else x2

PCLK2 up

TIMxCLKTIM2..7,12..14

APB1 Prescaler/1,2,4,8,16

AHB Prescaler/1,2…512HSE Osc

OSC_OUT

OSC_IN

4 -25 MHz

PLLCLK

/ M HSE

HSI

SYSCLK

120 MHz max

If (APB2 pres =1) x1 Else

x2

PCLK2 up to 60MHz

TIMxCLKTIM1,8..11

APB2 Prescaler/1,2,4,8,16

PLL48CLK (USB FS, SDIO & RNG)

/ P

/ Q

VCO

x N

HSI

/ P

/ Q

x NI2SCLK

Ext. ClockSPI2S_CKIN

VCO

/ R

PLL

HSEPLLCLKMCO1 /1..5

LSE

SYSCLK

MACTXCLK

MACRXCLKMACRMIICLK

USB HSULPI clock

/ R

x N

PLLI2S

PLLI2SCLK

SYSCLKHSE

PLLCLKMCO2 /1..5

PLLI2S

/2,

20


Ethernet PHY

USB2.0 PHY

Flash Read Protection (1/2)( )The user area in the Flash memory can be protected against read operations from an entrusted code.

Level 0: Read protection disabledA ti t d b iti 0 AA t th RDP b t i tActivated by writing 0xAA to the RDP byte registerAll operations from/to the Flash memory or the backup SRAM are possible in any boot configuration.

Level 1: Read protection enabledActivated by writing any other value of 0xAA and 0xCC to the RDP byte registerIn debug mode, any Flash memory or backup RAM accesses are disabled.debug ode, a y as e o y o bac up accesses a e d sab edDebug is still permitted in system SRAM

Level 2: Device is “locked-up”Level 2: Device is locked-upActivated by writing 0xCC to the RDP option byte registerAll protections provided by Level 1 are activeDebug features (CPU JTAG and single wire) are disabledDebug features (CPU JTAG and single-wire) are disabled User options can no longer be changed.Boundary scan disabled


Flash Read Protection (2/2)

W it ti i l di

RDP ≠ 0xAA and RDP ≠ 0xCCOther option(s) modified

( )

Level 1 RDP ≠ 0xCC

Write options including RDP=0xAA

RDP ≠ 0xAA

Write options including RDP = 0xCC Write options including RDP

≠ 0xAA and RDP ≠ 0xCC

Level 2 RDP=0xCC

Level 0 RDP=0xAAWrite options including RDPWrite options including RDP

= 0xCC

RDP = 0xAARDP 0xAAOther option(s) modified

Option byte write (RDP level increase) includes: Option byte erase and New option byte programmingO ti b t it (RDP l l d ) i l d O ti b t N ti b t i d M E


Option byte write (RDP level decrease) includes: Option byte erase, New option byte programming and Mass EraseOption byte write (RDP level identical) includes : Option byte erase and New option byte programming

Thank You !


Documents

STM32 Seminar STM32F2 High-Performance - Компэлcompel.ru/wordpress/wp-content/uploads/2011/12/2-STM32F2-CM3-Hi… · STM32 Seminar STM32F2 High-Performance COMPEL/STM Seminar