STM32: Peripherals MarcelloTraiolatraiola/courses/HLEE503/CM/CM3_STM32... · Marcello TRAIOLA - [email protected] 9 Memorymap The SRAM represents only a "tiny" part of the memory mapping!

STM32: Peripherals

Marcello [email protected]é de Montpellier

November 29, 2018

mailto:[email protected]

Marcello TRAIOLA - [email protected]

STM32 System Architecture



STM32 System ArchitectureS0: I-bus: This bus connects the Instruction bus of theCortex-M4 core to the BusMatrix. This bus is used by the coreto fetch instructions. The targets of this bus are the internalFlash memory, the SRAM and the Core Cupled Memory(CCM) RAM.S1: D-bus: This bus connects the DCode bus (literal loadand debug access) of the Cortex-M4 core to the BusMatrix.The targets of this bus are the internal Flash memory, theSRAM and the CCM RAM.S2: S-bus: This bus connects the system bus of theCortex-M4 core to the BusMatrix. This bus is used to accessdata located in the peripheral or SRAM area. The targets ofthis bus are the SRAM, the AHB to APB1/APB2 bridges, theAHB IO port and the ADC.S3, S4: DMA-bus: This bus connects the AHB masterinterface of the DMA to the BusMatrix which manages theaccess of different Masters to Flash, SRAM and peripherals.



BusMatrix

The BusMatrix manages the access arbitration betweenMastersThe arbitration uses a Round Robin algorithmThe BusMatrix is composed of five mastersI System bus, DCode bus, ICode bus, DMA1&2 bus

and seven slavesI FLITF, SRAM, CCM RAM, AHB2GPIO and AHB2APB1/2

bridges, and ADC



Memory map

Peripherals are memory mapped



Memory map

General purpose input/output



Memory map

Reset and clock control (RCC)



Memory map

External Interrupt



Memory map

The SRAM represents only a "tiny" part of the memorymapping!



Reset and clock control (RCC)

System clock (SYSCLK) selection (three different clocksources):I HSI 8 MHZ RC oscillator clockI HSE oscillator clockI PLL clock

RCC registers allow to enable the use of a particular peripheralI When the peripheral clock is not active, the peripheral register

values may not be readable by software and the returned valueis always 0x0.

RCC_AHBENR, RCC_APB1RSTR, RCC_APB2RSTR



Execution flow

Not all the event in an embedded system are executed in asynchronous and serial wayI Classic instruction execution as ADD, MUL, LDR, etc, is

normally sequential (one after another). The programmerdecides the order.

However, many exceptions could happen to the normalexecution flow:I ResetI Critical failureI Asynchronous signalsI ...



ExceptionsWhat is an exception?I A special event that requires the CPU to stop normal program

execution and perform some service related to the event.Examples of exceptionsI I/O completion, timer time-out, end of conversion,I illegal opcodes, arithmetic overflow, divide-by-0, etc.

Functions of exceptionsI Respond to infrequent but important eventsI I/O synchronizationI Periodic interrupts

Interrupt is a powerful concept in embedded systems forseparating the time-critical events from the others and executethem in a prioritized manner.In a typical embedded system, the embedded processor(microcontroller) is responsible for doing more than one task(but can do only one at a time).



In Hardware: Asynchronous exceptions

How do we manage asynchronous exceptions in amicro-controller? Examples:I Pushing a buttonI A peripheral ending a task (e.g., DMA)I External signalI ...

Two strategies:I PollingI Interrupt



Polling VS InterruptINTERRUPT POLLING

BasicDevice notify CPU

that it needs CPU attention.

CPU constantly checksdevice status whether

it needs CPU’s attention.

MechanismAn interrupt is a

hardware mechanism.Polling is a Protocol.

ServicingInterrupt handler

services the Device.CPU services the device.

IndicationInterrupt-request lineindicates that device

needs servicing.

Comand-ready bit indicatesthe device needs servicing.

CPUCPU is disturbed only

when a device needs servicing,which saves CPU cycles.

CPU has to wait and check whether adevice needs servicing whichwastes lots of CPU cycles.

OccurrenceAn interrupt canoccur at any time.

CPU polls the devicesat regular interval.

Efficiency

Interrupt becomes inefficientwhen devices keep

on interrupting the CPUrepeatedly.

Polling becomes inefficientwhen CPU rarely finds adevice ready for service.

ExampleLet the bell ring

then open the door tocheck who has come.

Constantly keep on openingthe door to check whether

anybody has come.



Example: Using user button on STM32 in polling



Example: Using user button on STM32 in polling

Once the button activated, the CPU has to verify periodicallywhether the button was pressed or not.I Create a procedure which reads the state of the GPIO port

input data register (GPIO_IDR)I invoke the procedure periodicallyI if you find a specific value, then it means that the button was

pressed and a specific action can be performed (e.g., you canswitch on/off a led)



Interrupts scheme



Interrupts

Nested vectored interrupt controller (NVIC) main featuresI 74 maskable interrupt channelsI A programmable priority level of 0-15 for each interrupt. A

higher level corresponds to a lower priority, so level 0 is thehighest interrupt priority

I Low-latency exception and interrupt handlingI Power management controlI Implementation of System Control Registers

The NVIC and the processor core interface are closely coupledI this enables low latency interrupt processing and efficient

processing of late arriving interrupts.

All interrupts including the core exceptions are managed by theNVIC.



Interrupt Priorities



EXTI

Extended interrupts and events controller (EXTI)Manages the external and internal asynchronousevents/interrupts and generates the event request to theCPU/Interrupt Controller and a wake-up request to the PowerManager.An interrupt could be left pending;I for external interrupts, a status register indicates the source of

the interrupt;I for internal interrupts, the pending status is assured by the

generating peripheral, thus no need for a specific flag.

Each input line can be masked independently.



External and internal interrupt/event line mapping

36 interrupt/event lines areavailable: 8 lines are internal(including the reserved ones); theremaining 28 lines are external.The GPIOs are connected to the 16external interrupt/event lines in thefollowing manner:



Configuring InterruptsFor the external interrupt lines the interrupt line should beconfigured and enabled.I This is done by enabling the interrupt request by writing a "1"

to the corresponding bit in the interrupt mask register(IMR).

When the external interrupt line receives a signal, an interruptrequest is generated and the corresponding pending bit is alsoset.

In practice, to configure a line as interrupt source, use thefollowing procedure:I Configure the system controller to manage the external

interrupt line connection to the GPIOsI Configure the corresponding mask bit in the EXTI_IMR

register.I Configure the Trigger Selection bits of the Interrupt line

(EXTI_RTSR and EXTI_FTSR).I Set the Interrupt Service Routine.I Clear the pending request.







Enable SYSCFG clock






Configuring Interrupts

Configure the corresponding mask bit in the EXTI_IMRregister:




Configure the Rising Trigger Selection bits of the Interruptline (EXTI_RTSR)




Configure the Falling Trigger Selection bits of the Interruptline (EXTI_FTSR)




Set theInterruptService Routine(Vector Table)




Configure the NVIC Interrupt set enable register (NVIC_ISER)to activate the interruptThis will "wake up" (interrupt) the processor, asking it toserve the request




Find the Name of the Interrupt service routine (ISR)

Write your function with the same name to perform anaction.




Clear the pending request.


Documents

STM32: Peripherals MarcelloTraiolatraiola/courses/HLEE503/CM/CM3_STM32... · Marcello TRAIOLA - [email protected] 9 Memorymap The SRAM represents only a "tiny" part of the memory mapping!