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Statistical and Numerical Approach for a computerefficient circuit yield analysis

Lucas Brusamarello1, Roberto da Silva1, Gilson I. Wirth2, and Ricardo Reis1

1 UFRGS - Universidade Federal do Rio Grande do Sul - Instituto de InformaticaAv. Bento Goncalves, 9500. CEP 91501-970. Porto Alegre, Brazil

2 UFRGS - Universidade Federal do Rio Grande do Sul - Departamento de Engenharia EletricaAv. Osvaldo Aranha, 103. CEP : 90035-190, Porto Alegre, Brazil

Abstract. In nanometer scale CMOS parameter variations are a challenge for thedesign of high yield integrated circuits. Statistical Timing Analysis techniques re-quire statistical modeling of logic blocks in the netlist in order to compute meanand standard deviate for system performance. In this work we propose an accurateand computer efficient methodology for statistical modeling of circuit blocks. Nu-merical error propagation techniques are applied to model within-die and die-to-die process variations at electrical level. The model handles co-variances betweenparameters and spatial correlation, and gives as output the statistical parametersthat can be applied at higher level analysis tools, as for instance statistical timinganalysis tools. Moreover, we develop a methodology to compute the quantitativecontribution of each circuit random parameter to the circuit performance vari-ance. This methodology can be employed by the designer or by an automatic toolin order to improve circuit yield.The methodology for yield analysis proposed in this work is shown to be a solidalternative to traditional Monte Carlo analysis, reducing by orders of magnitudethe number of electrical simulations required to analyze memory cells, logic gatesand small combinational blocks at electrical level. As a case study, we model theyield loss of a SRAM memory due to variability in access time, considering vari-ance in threshold voltage, channel width and length, which may present both die-to-die and within-die variations. We compare results obtained using the proposedmethod with statistical results obtained by Monte Carlo simulation. A speedup of1000 is achieved, with mean error of the standard deviate being 7% comparedto MC.

1 Introduction

Performance and reliability of deep-sub-micron technologies are being increasingly af-fected by process variations and leakage current [24]. Variability in the manufacturingprocess imposes limitations to the design of circuits in recent technologies. Processvariations are related to machinery limited precision and process methodology varia-tions like temperature and lithography exposure time, and discreteness of the material.These variations are stochastic and the prediction of the percentage of manufacturedcircuits which will achieve a given performance becomes a major problem for the cir-cuit designer. Therefore, the use of statistical methods in circuit design is of increasingrelevance.

Please use the following format when citing this chapter:

291; VLSI-SoC: Advanced Topics on Systems on a Chip; eds. R. Reis, V. Mooney, P. Hasler; (Boston: Springer), pp. 151174. Brusamarello, L., Silva, R.da., Wirth, G.I. and Reis, R., 2009, in IFIP International Federation for Information Processing, Volume

Lucas Brusamarello, Roberto da Silva, Gilson I. Wirth, and Ricardo Reis

Electrical parameter variabilitymay be decomposed into die-to-die variations (D2D)and within-die variations (WD) [27]. Within-die variations may arise from differentsources, for instance the discreteness of matter and energy (dopant atoms, photo resistmolecules, and photons). A well known example of a WD parameter is threshold volt-age (VtMahmoodi2005Estimation-of-d. Random Dopant Fluctuations (RDF) is mainlycaused by the irregular distribution of doping atoms in the channel, and this effect nowa-days represents one of the greatest challenges for the industry [10]. Consider vt0 thestandard deviation in threshold voltage for minimum sized transistors, then the depen-dence of vt on transistor size is given by [25]:

vt = vt0

LminWminLW (1)

Die-to-die variations may arise from equipment asymmetries (like asymmetries inchamber gas flows, thermal gradients and so on) or imperfections in equipment oper-ation and process flow. These asymmetries and imperfections affect the average valueof a parameter from die to die, wafer to wafer, and lot to lot. Variations may also beoriginated by the pattern or layout induced deviation of a parameter from its nominalvalue [6]. Parameters such as oxide thickness, transistor channel length and channelwidth may show systematic variations [12]. In the case of a D2D parameter k, transis-tors close to each other are affected by the same constant fluctuation k.

Statistical Static Timing Analysis (SSTA) gives at logic level a quantitative riskmanagement for the design as a function of the circuit topology, the electrical parame-ters and the variations [26]. In order to apply a SSTA methodology, the cell libraries arecharacterized at electrical level, for which nowadays Monte Carlo simulation is com-monly employed. Larger designs, composed by many hundreds of transistors, may bedecomposed in functional blocks and treated at different levels of abstraction. A blockmay be a simple or complex gate, a sequential block (e.g. flip-flop) or a memory cell. Atthe block level the variability may be evaluated using the methodology proposed in thismanuscript. The result provided by this methodology (mean, standard deviation) maythen be used by higher abstraction level techniques, as for instance Statistical StaticTiming Analysis (SSTA), to provide risk management at this higher abstraction levels.

In [12] cell characterization using numerical error propagation is proposed. How-ever, their cell modeling methodology does not include D2D variation, although theirproposed SSTA algorithm considers spatial correlation at gate level. Furthermore, thequantitative contribution of each random parameter to the circuit performance varianceis not analyzed. As shown further in our work, this analysis may help to improve yield.Finally, in that work only first order approximation for numerical derivatives is em-ployed, and the algorithm complexity and accuracy are not analyzed. In our work weshow that the model accuracy may be very sensitive to numerical derivative approxima-tion. Higher order approximations may lead to a better accuracy.

Yield analysis of SRAM memories using Monte Carlo has been studied in [2], [3]and [4]. Error propagation at electrical level for yield analysis of SRAM memory hasbeen explored in [14] and [15], but Vth is the only random variable analyzed (MonteCarlo is performed to simulate D2D). Sensitivities are computed using first order nu-merical approximation. In these works failures in SRAM cell are statistically modeled

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Statistical and numerical approach for a computer efficient circuit yield analysis

(access time failure, read failure, write failure and hold failure), and yield of SRAMmemory is given as a function of redundant columns employed in the design. Simula-tions in these works show that the most significant source of failures in SRAM cell isaccess time failure. In [9] an electrical-level analysis of SRAM cell static noise marginis presented, which is based in the extraction of the electric parameters by an atomisticdevice simulator. This method is robust because the transistor cards are the most con-sistent and closely related to the device variations, but still a huge number of device andelectric-level simulations must be run (200 runs in that case).

This manuscript presents a general methodology for analysis of circuit blocks atelectrical level which is able to considerWD and D2D variations, as well as co-variancesbetween electrical parameters. Also, we implement a method to point out the parame-ters which most contribute to circuit performance variance. The methodology is generalbecause it is independent of circuit topology (SRAM cell, multiplexer block, complexgate, etc), and circuit performance parameter of interest (delay, leakage current, power,etc). It maintains the generality of the traditional Monte Carlo techniques, still largelyemployed in commercial electrical simulators [23].

As a case study we discuss yield analysis and optimization of a SRAM memory.SRAM memory is a good case study because memory yield is directly dependent onSRAM cell yield, and SSTA is not required to analyze critical paths and signal correla-tions. For this case study we develop a methodology of yield improvement based on theanalysis of parameter contribution to variability. We resize the transistors that presentthe major contribution to the access time variance.

The paper is organized as follows. Section 2 presents a high-level introduction tothe methodology. Sections 3 and 4 formally define the problem of statistical analysis ofintegrated circuits at electrical level and describe the mathematical foundations of theproposed methodology. Section 5 exposes a formulation for the sensitivity of the vari-ance to the electrical parameters. Section 6 gives formulations for numerical compu-tation of derivatives using higher order approximations. Section 7 details the proposedalgorithm, and presents a study on its complexity. Section 8 focuses on the methodol-ogy applied to yield analysis and yield maximization of a SRAM memory, consideringvariability in the SRAM cell access time. Finally, last section presents our conclusions.

2 Methodology

This work describes a framework to compute variability in circuit electrical behaviorand its dependency on the design and process parameters. The methodology is based onthe computation of variance using error propagation, where derivatives are numericallycomputed using electrical simulations in this work HSPICE[23] is employed.

Both circuit netlist and the set of circuit parameters which are modeled as randomvariables are user inputs. Each random variable has its mean and standard deviation, aswell as its kind (WD or D2D).

A first script generates a set of runs for the electrical simulator in our the caseHSPICE .DATA command [23]. This library is included in the netlist file, and HSPICEis run in SWEEP mode.

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Lucas Brusamarello, Roberto da Silva, Gilson I. Wirth, and Ricardo Reis

Fig. 1. High level flowchart

One value (circuit response) is computed at each run. These values are gatheredin order to compute the partial derivatives for each electrical parameter. Finally, errorpropagation is employed to compute the variance. An approximation for the mean isobtained by simulation using nominal values.

3 Model

Consider an electric circuit denoted by , composed of n transistors represented as com-ponents of the vector = (1, . . . ,n), interconnected according to a topology . Bydefinition, the circuit response is given by the function F( 1, . . . , n,

1, . . . ,

n,),

where the vectors i = ((1)i , ...,(p)i ) and i = (

(1)i , ...,

(q)i ) represent respectively

the WD and D2D parameters of transistor i, p is the number of WD parameters and q

the number of D2D parameters. For instance, the case 3 = (Vt) and 3 = (Tox,L,W )

represents typical input parameters for transistor 3, including oxide thickness (Tox),threshold voltage (Vt) and dimensions (L andW ) of the transistor.

In the presence of variability in the fabrication process, electrical characteristics andphysical dimensions of the circuit can be considered random variables and consequentlythe output is a random variable. Consider, without loss of generality, that parameters(as for instance Tox, Vt, L,W ) are Gaussian variables with mean () and variance (2),

i.e, k1i = N(

(k1i ),2(k1)

)

and k2i = N(

( k2i ),2( k2)

)

, where i = 1, ...,n,

k1 = 1, ..., p and k2 = 1, ...,q.

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Statistical and numerical approach for a computer efficient circuit yield analysis

The circuit statistical response S is a function that depends on N = n (p+ q)random variables (includingWD and D2D parameters), given by the functional relation

S = F( 1, . . . , n, 1, . . . ,

n,) (2)

3.1 D2D and WD random variables

In order to model the impact of process variations on the electric circuit response, D2Dand WD are treated differently. In the case of a D2D parameter, the same fluctuation af-fects transistors close to each other. Still their absolute values may be different becausethey may have distinct averages.

Other random variables are modeled as Gaussian random variables, which are de-noted in this work as WD parameters. A WD variable assumes a random value for eachtransistor, although it can be subject to covariance coefficients (i j).

Notice that both D2D and WD parameters are random variables. The differencebetween them is the randomness context: each instance of a WD variable assumes adifferent random value, while a D2D parameter has a single random fluctuation thatapplies to a set of devices.

D2D parameters Spatial correlation impels the D2D electrical parameter of all tran-sistors to change in a synchronized way. For instance, if the dimensionW is assumed topresent D2D variations andW1 of transistor 1 changes by a quantity W , the dimen-sionW2 of a transistor 2 changes by the same quantity W although their mean ((W1)and (W2)) in the standard sampling process can be different. The parameterW is thendefined as a variable that presents

1. exactly the same variation W inside an single electrical block;2. but different variation in different electrical blocks, as for instance variation W1 inblock 1 and variation W2 in block 2.

The reader should notice that the position (x,y) of a device is not taken into account.Parameters that present D2D variations can be modeled as

ji = (ji )+ j ( j)

where j = N(0,1) is a standard normal variable which is independent of the transistor1 i n. It means that the same variable j will have the same shift of magnitude j ( j) independent of the transistor to which it is applied. In other words, the variables j1 , ...,

jn are the same random variable except by their mean values. Looking at the

contribution of this variables for error estimation, it is important to define the generalvariable j = ( j) + j ( j), where ( j) is a transistor-independent constant.Then it can be written as

ji (k) = (ji )+ j ( j) = ( ji )+ j ( j) (3)

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Lucas Brusamarello, Roberto da Silva, Gilson I. Wirth, and Ricardo Reis

Which leads to suitable simplification

F( 1, . . . , n, 1, . . . ,

n,)=F(

1, . . . , n, 1, . . . , qthe computation of partial derivatives becomes

F j

=n

i=1

F

ji

ji j

(4)

=n

i=1

F

ji(5)

because according to equation 3 it is true that ji /j = 1, for all i {1, ...,n}.

4 Error propagation and Monte Carlo

When measuring a quantity denoted by f which depends of n variables, x1, x2, ..., xn,an important point is to determine the uncertainty in f given the uncertainty in eachvariable. A general formula is known if we suppose that {xi}ni=1 are random Gaussianvariables, which is a widely accepted procedure [6]. In this case the uncertainty in f( this is an error estimate, including systematic...