J Comput ElectronDOI 10.1007/s10825-014-0580-1

Static and dynamic characteristics of dual gate organicTFT based NAND and NOR circuits

Brijesh Kumar · Brajesh Kumar Kaushik ·Yuvraj Singh Negi

© Springer Science+Business Media New York 2014

Abstract This research paper analyzes the static anddynamic behavior of dual-gate organic thin film transistors(DG-OTFTs) based universal logic gates using the Atlas 2-D numerical device simulator. The electrical characteristicsand performance parameters of pentacene based DG-OTFTis evaluated and verified with respect to the reported experi-mental results. The NAND and NOR logic gate circuits arerealized using p-type designs in diode-load logic (DLL) andzero-Vgs-load logic (ZVLL). The results show that the logicfunctions in ZVLL configuration outperforms the DLL onesmainly in terms of noise margin, gain and voltage swing;however, there is a trade-off in terms of speed. The ZVLLNAND gate demonstrates an increment of 16 and 32 % involtage swing and noise margin, respectively in comparisonto the DLL one. Besides this, the gain also increases by 1.5times in ZVLL mode. On the contrary, the DLL configurationdemonstrates a significant reduction of 64 % in the propaga-tion delay in comparison to the ZVLL. Similarly, NOR gateshows an increment of 24 and 30 % in voltage swing andnoise margin, respectively under ZVLL configuration. How-ever, the propagation delay for DLL NOR configuration isone-fourth of that of its ZVLL counterpart.

B. Kumar · Y. S. NegiDepartment of Polymer and Process Engineering, Indian Instituteof Technology, Roorkee 247667, Uttarakhand, Indiae-mail: ynegifpt@iitr.ac.in

B. KumarDepartment of Electronics & Communication Engineering,Graphic Era University, Dehradun 248001, Uttarakhand, Indiae-mail: bk228dpt@iitr.ac.in

B. K. Kaushik (B)Department of Electronics & Communication Engineering,Indian Institute of Technology, Roorkee 247667, Uttarakhand, Indiae-mail: bkk23fec@iitr.ac.in; bkkaushik23@gmail.com

Keywords Organic NAND gate · NOR gate · Diode loadlogic (DLL) · Zero-Vgs load logic (ZVLL) · Organic thinfilm transistor (OTFT)

1 Introduction

Organic thin film transistor (OTFT) technology have rapidlydeveloped through several generations and now demonstratesclear-cut advantages in terms of mechanical flexibility andstraightforward fabrication at low temperatures. Advance-ments in organic TFTs based fabrication techniques certainlymotivate researchers to utilize various flexible substrates suchas paper [1], plastic [2], glass [3] and fiber [4] for low cost andlight weight electronic applications. Undoubtedly, an organictransistor foresees applications in sensors [5], organic mem-ory [6], e-paper [7], RFID tags [8] and flexible integratedcircuits [9]. Moreover, it has turned out to be a promisingbackplane driver in an organic LED based large area flexibledisplays [10].

Integrated circuits are the backbone of the modern VLSIsystem design that comprises of mainly logic gates. The per-formance of conventional semiconductor based logic gatesis unquestionably superior; however, the production cost andflexibility of silicon based logic gates is an obvious con-straint. Organic logic gates are inexpensive, flexible andpromising enough to achieve a reasonable performance.Although, logic gates are essentially required in severalOTFT based applications, but only few logic gate designsbased on organic TFTs have been reported till date. Recently,Guerin et al. [11] reported organic NAND and NOR gatesoperating at enormously high supply voltage of ± 20 V, usingPolytriarylamine based p-type and Acene-diimide based n-type OTFTs. The operating frequency of these logic gateswas limited to 450 Hz due to 26 % lower mobility of the n-

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type transistor in comparison to the p-type. Undoubtedly, acomplementary design is beneficial in terms of lower powerconsumption. Nevertheless, for such designs both p- andn-type transistors should exhibit comparable mobility andthreshold voltage.The mobility of n-type organic semicon-ductors (OSCs) is often lower in comparison to p-type dueto their large band gaps. Moreover, the n-type OTFT perfor-mance degrades more rapidly due to its susceptibility to waterand oxygen under ambient conditions [12,13]. Most of then-channel transistors can be operated only when processedunder the inert condition that makes them technologicallyunattractive. In addition to this, most of the commonly usedcontact metals exhibit the work functions better suited toinject the holes into HOMO (highest occupied molecularorbit) than the electrons into LUMO (lowest unoccupiedmolecular orbit) that creates another bottleneck in achiev-ing high performance n-type transistors. Burgi et al. [14]reported a large barrier height of 1.2 eV for n-type OSCswith commonly used gold, aluminium and copper metals.The effect of metal/OSC interface is less pronounced in p-type materials due to their lower barrier height (0.1–0.2 eV).Moreover, the mobility of n-type OSCs is much lower thanthe p-type OSCs. Therefore, most of the organic circuitsmake use of only p-type transistor based designs instead ofn-type, thereby exhibiting superior performance in terms ofbetter stability, higher mobility and lower barrier height.

Dual gate (DG) transistors have overwhelmingly demon-strated their superiority to single gate transistors in silicontechnology. Similarly, the characteristics of organic tran-sistors can also be improved using double gate. Comparedto a single gate transistor, the dual gate organic transistorexhibits improved performance due to charge carrier mod-ulation [15] with biasing of both the gates. Moreover, anincrease in gate oxide charge density helps in improving thetransistor performance. The DG transistors exhibit numerousadvantages such as, higher mobility (μ), higher on/off cur-rent ratio (Ion/Ioff), higher transconductance (gm), steepersub-threshold slope and most importantly, a better controlon the threshold voltage (Vt ) in comparison to the singlegate. Cui et al. [15] reported five times higher mobility andan improvement of 35 % in sub-threshold slope for the dualgate OTFT in comparison to the single gate. Similarly, Koo etal. [16] demonstrated an improvement of 70 % in thresholdvoltage for pentacene based dual gate OTFT. Besides this,the mobility and on/off current ratio also improved by twotimes when the TFTs operated in a dual gate mode. Almostall organic logic gates till date have been realized using singlegate transistors only. The characteristics of organic transis-tors can be certainly improved using double gate, therebyimproving the performance of digital circuits as well.

Analysis and comparison of inverter circuits using sin-gle and dual gate OTFTs was reported in earlier publication[17], wherein the dual gate based inverter design showed

an improvement of 7, 19 and 42 % in voltage swing, gainand propagation delay, respectively. Motivated by the prioroutcomes demonstrating remarkable merits of DG-OTFT,this research paper analyzes dual-gate OTFTs based NANDand NOR gates. The logic gate circuits based on only p-type designs are implemented under diode-load logic (DLL)and zero-Vgs-load logic (ZVLL). Furthermore, the static anddynamic behaviors of these gates in the DLL and ZVLL con-figurations are evaluated and compared. It is observed thatZVLL configuration outperforms the DLL configuration interms of noise margin, voltage swing and gain.

This paper is arranged in five sections, including the cur-rent introductory Sect. 1. Thereafter, Sect. 2 analyzes theelectrical characteristics and performance parameters of pen-tacene (p-type) based dual gate OTFT. Additionally, this sec-tion also discusses the fabrication flow for dual gate organicthin film transistor. Section 3 describes the static and dynamicbehavior of p-type organic NAND and NOR gate circuits inDLL and ZVLL configurations whereas, Sect. 4, presentssome important recommendation for future work. Finally,Sect. 5 summarizes the important outcomes of the proposedwork.

2 Organic dual gate transistor

Organic transistor is realized in a dual gate configuration toachieve better charge carrier modulation in the semiconduc-tor layer. In 1981, the first DG-TFT was demonstrated by Luoet al. [18], that was based on the Cadmium Selenide inor-ganic material. Subsequently, Tuan et al. [19] and Kanekoet al. [20] reported amorphous silicon hydrogenated basedDG-TFTs in 1982 and 1992, respectively. In 2005, Cui etal. [15] demonstrated the first organic dual gate TFT basedon pentacene OSC. Since then, the performance of dual gateOTFTs has undergone spectacular improvements [21,22]. Inthis work, a pentacene based DG-OTFT is used to realizeall-p type organic NAND and NOR logic gates. Simulationset-up, electrical characteristics of DG-OTFT and fabricationflow for dual gate organic thin film transistor are discussedin following sub-sections.

2.1 Simulation setup

A dual gate TFT structure consists of a gate in the bot-tom along with its bottom dielectric, source (S)/drain (D)contacts, organic semiconductor and a top gate with a topdielectric. Bottom (or front) gate accumulates the carriersin the channel while the bias on the top (or back) gate fur-ther increases the conductivity of the channel electrostatically[21,22]. Therefore, Vt can be controlled by using back gate,but at the cost of an extra gate material and increased fabrica-tion steps. Although, Vt determines the switching behavior

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of any device and is dependent on doping concentration, butan external bias control on Vt itself can bring out highly con-trolled operation of the device.

A DG-OTFT structure, shown in Fig. 1 consists of chan-nel width (W ) and length (L) of 800 and 25 µm, respec-tively. The top and bottom gate electrodes are of aluminiumand heavily doped silicon, respectively, each with a thick-ness of 150 nm. Furthermore, the SiO2 of thicknesses 300and 100 nm is used as the top and bottom gate dielectrics,respectively. The thicknesses of pentacene semiconductinglayer and gold S/D contacts are 200 and 80 nm, respectively.

The organic dual gate device and logic gate circuits areanalyzed using finite element based Atlas 2-D numericaldevice simulator [23]. The NAND and NOR gate in the DLLand ZVLL configurations are simulated under mixed-mode,wherein, each input file is split into two parts; one of themdescribes the circuit net-list, and the other explains devicesimulation and model parameters. It incorporates Poole–Frenkel mobility model that effectively analyzes static anddynamic behavior of the analog and digital circuits that canbe expressed [23] as

μ(E) = μ0 exp

[− �

kT+

(β

kT− γ

) √E

](1)

where, μ(E), E and μ0 represent field dependent mobility,electric field and null field mobility respectively. The acti-vation energy and hole Poole–Frenkel factor are specifiedby Δ and β respectively, whereas, γ is used as the fittingparameter. This model demonstrates the conduction due tofield enhanced thermal excitation of trapped charge carri-ers. The mobility increases with an increase in gate volt-age and thus justifies the hopping transport phenomenon inOTFTs [24]. The values of Δ and β for pentacene materialare 1.792×10−2 eV and 7.758×10−5 eV (cm/V)0.5, respec-tively [25]. Effective density of states in both conduction andvalence band is considered as 1021 whereas, the relative per-mittivity of pentacene is 4 [26].

Bottom Gate (n+ Si)

Bottom Dielectric (SiO2)

PentaceneD (Au)

Top Dielectric (SiO2)

Top Gate (Al )

S (Au)

Fig. 1 Schematic of dual gate OTFT

2.2 Electrical characteristics and parameter extraction ofDG-OTFT

The simulated and experimental [15] output characteristics(Ids−Vds)of pentacene based DG-OTFT as a function of gatevoltage is shown in Fig. 2, whereas, its transfer characteristics(Ids − Vgs) at Vds of −2.5 V is illustrated in Fig. 3. Basedon the bias conditions, a dual gate transistor can be operatedin top, bottom and the dual gate modes. In top-gate mode,a voltage at the top gate is applied, while the bottom gate iskept at ground potential, however, the biasing is reversed inbottom-gate mode.

In single-gate bias mode, the second gate has no effecton the conduction, whereas, both the gates play a vital rolein accumulating the charge at the OSC/insulator interface indual-gate mode. Total charge (QT otal) produced by both thegates in dual-gate mode is expressed as [27]

0 -2 -4 -6 -8 -10

0.0

-0.4

-0.8

-1.2

-1.6

Vgs

= 0V Vgs

= -2.5V

Vgs

= -5.0V

Vgs

= -7.5V

Vgs

= -10V

Experimental

Simulated

I ds (

μA)

Vds

(V)

DG

Fig. 2 Output (Ids −Vds) characteristics of pentacene based dual-gateOTFT

5 0 -5 -10 -15

0.0

-0.4

-0.8

-1.2DG

I ds (

μA)

Vgs

(V)

Experimental

Simulated

Vds

= -2.5V

Fig. 3 Transfer (Ids − Vgs) characteristics of pentacene based dual-gate OTFT

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0 -5 -10 -15

0.0

-0.4

-0.8

-1.2

-1.6

VBG

= -60V

I ds (

μA)

VFG

(V)

VBG

= 60V

Vds

= -2.5 V DG

Fig. 4 Ids −Vgs characteristics of DG transistor with VBG swept from−60 to 60 V in steps of 20 V

QT otal = CT.VT + CB. VB (2)

where, CT , VT and CB , VB are the capacitance and voltage ofthe top and bottom gate electrodes respectively. The currentin the DG-OTFT at a given Vds is determined by interplaybetween the biases at two gate electrodes. A positive biasingat the back gate partially depletes the front accumulationchannel that is compensated by an equal shift in front gatebiasing [28–30]. On the other hand, a negative back gatebias produces an additional current by introducing a secondchannel at the top interface. Transfer characteristics of DG-OTFT with the change of biasing at the back gate (VBG) arepresented in Fig. 4. The threshold voltage of DG transistorshifts towards more negative, when the back gate voltage isswept from negative to positive. This changes the transistoroperation from the depletion to enhancement mode.

The electrical parameters, such as μ, Vt , Ion/Ioff, SS andgm tabulated in Table 1 are extracted from the transfer char-acteristics. The transconductance gm is obtained from theslope of Ids − Vgs curve that is further used to compute themobility as

gm = ∂ Ids/∂Vgs (3)

μ = ∂ Ids

∂Vgs

L

WCox Vds(4)

The electrical characteristics and performance parametersobtained by simulation are verified with reported experimen-tal results [15]. The on-current at Vds = Vgs = −10V is1.25 µA that reasonably matches to the experimental currentwith an error of 3.5 %. Similarly, other parameters includ-ing threshold voltage, mobility, on/off current ratio, sub-threshold slope and transconductance closely matches to theexperimental results with an error of 3.2, 8, 4.2, 3.7 and 7.6%, respectively. As per transfer characteristics of dual gate

Table 1 Simulated and experimental parameters of dual gate OTFT

Parameters DG-OTFT

Simulated Experimental [15]

Threshold voltage, Vt (V) −2.13 −2.2

Mobility, µ(cm2/V.s) 0.092 0.1

On/Off current ratio, Ion/Iof f 3.97 × 103 3.8 × 103

Sub-threshold slope, SS (V/dec) 1.35 1.3

Transconductance, gm(µS) 0.13 0.12

OTFT, the channel transconductance, ∂ Ids/∂Vgs (at constantVds) is higher than the channel conductance, ∂ Ids/∂Vds (atconstant Vgs), which is the pre-requisite for voltage amplifi-cation in a logic gate [31].

2.3 Fabrication flow for dual gate organic thin filmtransistor (DG-OTFT)

This section describes the fabrication steps to achieve thedual gate organic transistors. Commonly used fabricationtechniques for dual gate organic TFTs and their circuitsinclude vacuum evaporation, electron beam [32,33], solu-tion processing [34], physical vapor deposition (PVD) [35],shadow masking [36], lift-off process [37], photolithogra-phy [26], atomic layer deposition, chemical vapor deposition(CVD) and RF sputtering. The logic circuits can be fabricatedin two ways. The first one involves the fabrication of indi-vidual DG-OTFTs that can be further configured to performthe operation of NAND/NOR logic gates through intercon-nections. The second approach involves the deposition ofcomplete logic circuit on a single substrate.

The fabrication flow and steps for obtaining a DG-OTFTare shown in Fig. 5. The performance of a DG-organic TFTgenerally depends on the properties of material, cleanlinessof the substrate and effectiveness of the deposition process.

For the sake of simplicity, the deposition process of lay-ered DG-OTFT structure starts with selecting a highly n-doped silicon (n+Si) substrate serving as the gate electrodewith a 100 nm thick (SiO2) layer that can be thermally grownfor forming the bottom gate dielectric. The heavily doped (n)

silicon wafer acts as the substrate and gate electrode simul-taneously. A layer of positive photoresist is developed on thebottom gate dielectric layer by the lift-off process. A glassmask is used to pattern the S/D contacts on the SiO2 layerthat allows the exposure of S/D area by light, whereas, theportion that remains unexposed is removed through cleaning.Furthermore, the 80 nm thick contact material is depositedon the patterned photo-resist through the vacuum evapora-tion technique prior to the deposition of OSC active layer.Contact metal for the S and D electrodes should be selectedsuch that it should not produce a high contact resistance. Thisimplies that the contact must possess a low interface barrier

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Bottom Gate (n+ Si)

Bottom Dielectric (SiO2)

Bottom Gate (n+ Si)

Bottom Dielectric (SiO2)

S (Au) D (Au)Photoresist

Bottom Gate (n+ Si)

Bottom Dielectric (SiO2)

Photoresist

Bottom Gate (n+ Si)

Bottom Dielectric (SiO2)

Photoresist

Glass

Bottom Gate (n+ Si)

Bottom Dielectric (SiO2)

S (Au) D (Au)

Bottom Gate (n+ Si)

Bottom Dielectric (SiO2)

Bottom Gate (n+ Si)

S (Au) D (Au)OSC (Pentacene)

Top Dielectric (SA-SiO2)

Bottom Dielectric (SiO2)

Bottom Gate (n+ Si)

S (Au) D (Au)OSC (Pentacene)

Top Gate (Al)

Bottom Dielectric (SiO2)

Bottom Gate (n+ Si)

S (Au) D (Au)OSC (Pentacene)

Top Dielectric (SA-SiO2)

Fig. 5 Fabrication flow of DG-OTFT is described in the followingsequence: (i) Heavily doped n-Silicon wafer as substrate and bottomgate electrode. (ii)] Thermal oxidation of Si exposes the wafer toan oxidizing condition for deposition of SiO2 as bottom gate dielec-tric layer. (iii) Developing photoresist film along with photoresistexposed to light. (iv) Uncovered portion of photoresist cross linked.(v) S/D (Au) patterning on top of SiO2. (vi) Cleaning the thin film andfinishing S/D. (vii) Depositing pentacene OSC layer by evaporatingusing shadow masking. (viii) Self assembled layer of SiO2 (SA-SiO2)

as top dielectric. (ix) Deposition of Al layer by thermal evaporation astop gate electrode

with the active layer for enabling a large number of carrierinjection [38,39]. Au metal is often used in p-type OTFTsdue to its high work function (5 eV). It is an appropriatemetal for usage with p-type OSCs as most of them exhibittheir HOMO level near 4.9 eV [40]. Thus, a low interfacebarrier (∼0.1 eV) between the gold and p-type OSCs makesthem suitable for building up contacts with ohmic character-istics. Adding nickel (Ni), titanium (Ti) and chromium (Cr)with gold improves the adhesivity [28,41].

The OSC thin film of 200 nm thick pentacene is depositedby thermal vacuum evaporation using shadow masking at aworking pressure of 6 × 10−7 Torr. Additionally, an OSCactive layer is deposited through either vacuum evaporationor the solution processing method dependent on the typeof organic semiconductor material. Small molecule semi-conductors are commonly deposited by vacuum evaporationprocess, because of the lower solubility in the organic sol-vents. Vacuum deposition techniques are advantageous inachieving highly ordered films with a precise control on thethickness. However, a highly sophisticated vacuum cham-ber is required for an adequate flow of the charge carriers.Moreover, deposition of material at a very high temperaturemakes this technique, inappropriate for the flexible and lowcost devices. Conducting polymers are generally depositedthrough solution processing techniques since they exhibithigher solubility in solvents like toluene and chloroform.Solution processable organic materials are beneficial in real-izing large area electronic circuits at considerably lower tem-perature and lower cost [42,43]. Spin coating is commonlyused solution processing technique, often employed for costeffective and large area production of the organic devices andcircuits.

Until this stage, fabrication of the bottom portion of DG-OTFT is achieved as shown in Fig. 5. The top gate dielectriclayer is formed using self assembled technique with SiO2

nanoparticles [15]. The inorganic dielectric materials aregenerally deposited through vacuum evaporation method. Onthe other hand, commonly used organic dielectric materialsare usually deposited by low cost solution process techniques.To improve the dielectric/OSC interface quality, a gas phaseoctcyltrichlorosilane (OTS) treatment can be applied to thedielectric surface [44]. Finally, a 150 nm thick patterned Allayer, which forms the top gate contact, is deposited by ther-mal vacuum evaporation. The DG-OTFT, finally obtained hasa channel length and width of 25 and 800 µm, respectively.

3 Organic universal logic gates

The performance of logic gates is characterized mainly interms of voltage swing, noise margin, gain and propagationdelay. The output of an all-p type organic circuit does notswing fully due to large threshold voltage of the organic

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transistors. This in turn reduces the noise margin and gain,thereby making it less robust. In order to obtain a sufficientlybetter performance, a zero-Vgs drive load is proposed forthe NAND and NOR gates, wherein, the gate and sourceterminals of the load transistor are connected together. Inthis logic, driver transistor strongly pulls-up the output volt-age, Vhigh towards VDD due to a significantly lower channelresistance in comparison to the load. However, the pull-downtransistor acts as a constant source-drain current source dueto zero-Vgs , therefore, the large W/L ratio is required forthe load to obtain an output, Vlow close to 0 V. The widthof load (2, 000 µm) is therefore taken four times higher thanthe driver (500 µm) in both NAND and NOR ZVLL config-urations. A ZVLL configuration exhibits a high output resis-tance, thereby, providing a higher gain [45]. However, theswitching speed is inherently low, since the pull-down cur-rent provided by the load is quite low that in turn produces alarge pull-down delay.

One of the ways to increase the switching speed is byconnecting the load in diode logic, wherein, the gate anddrain of the load transistor are shorted. This type of logic ismore robust and results in a large pull-down current leadingto a smaller delay, thereby providing faster circuits [46]. Inthis load logic, both transistors (driver and load) operate in theenhancement mode. Therefore, to obtain a logic high output,the W/L ratio of the driver should be large in comparisonto the load transistor. Taking this into account, the widthratio of driver to load is chosen as 4:1 (2, 000 : 500 µm) inDLL configuration. All p−type DG-OTFT based NAND andNOR logic gate circuits in the DLL and ZVLL configurationsare analyzed in the following sub-sections.

3.1 Organic NAND logic circuits

The schematics of NAND gate realized in the DLL and ZVLLconfigurations are shown in Fig. 6a, b, respectively. In all p-type NAND logic gate, the pull-up network consists of twodriver transistors, TD1 and TD2 connected in parallel [31].

This network pulls-up the output voltage (logic ‘1’) whenat least one of the inputs, V1 or V2 is ‘0’ that forms a con-ducting path between the biasing supply, VDD and the out-put terminal, VOU T . The pull-down action is performed byload TFT (TL) when both the driver transistors are turned‘OFF’.

The static and dynamic characteristics of logic gatesdepend on the data input patterns, therefore the analysis ofgain and noise margin is more complex than the inverter.In NAND gate, a logic ‘0’ at V1 or V2 terminal enables thecorresponding transistor to be turned ‘ON’. Thus, the circuitreduces to a simple inverter that enables a logic ‘1’ in theoutput. The transconductance ratio, kR (driver to load) of thecorresponding inverter is expressed as

V1TD1 V2

TD2

VOUT

TL

VDD =10V

V1TD1 V2

TD2

VOUT

TL

VDD =10V

(a)

(b)

Fig. 6 Schematics of NAND gate in a DLL and b ZVLL config-urations

kR = (μ Cox W/L)TD1/TD2

(μ Cox W/L)TL

(5)

where, μ, Cox , W and L corresponds to the mobility, capac-itance per unit area, width and length of the respective DG-OTFT. Combined plots of voltage transfer characteristics(VTC) of NAND gate in DLL and ZVLL configurations areshown in Fig. 7, while sweeping V1 from 0 to 10 V andkeeping V2 = 10 V. Similar characteristics are observed onswapping the two inputs. The NAND gate demonstrates anincrement of 16 % in voltage swing and 14 % in noise marginfor ZVLL configuration in comparison to the DLL. Besidesthis, the gain also improves by 1.5 times in ZVLL mode.

Furthermore, when both driver TFTs (TD1 and TD2) areturned ‘ON’ (V1 = V2 = 0 V), the load current is expressedas the sum of two driver currents

(Ids)TL= (Ids)TD1

+ (Ids)TD2(6)

The NAND logic circuitry with both of its inputs tied to alogic ‘0’ can be replaced by an inverter circuit with driver-to-load ratio given as

kR = (μ Cox W/L)TD1+ (μ Cox W/L)TD2

(μ Cox W/L)TL

(7)

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0 2 4 6 8 10

0

2

4

6

8

10

VIN (V)

V IN,V

OU

T(V

)

V1

V2 ZVLL

DLL

NAND Gate

Fig. 7 VTCs of NAND gate in DLL and ZVLL with V2 = 10 V andV1; 0 → 10 V

The transconductance ratio (kR) is higher by two times (ifboth the driver TFTs, TD1 and TD2 are of same strength) thanthe case, wherein only one driver is turned ‘ON’ [47]. Hence,the magnitude of output voltage (VO H ) is obtained higher.The plots of VTC and gain for the NAND gate (DLL andZVLL) are presented in Fig. 8a, b, respectively, for differentinput combinations. Resulting DC characteristics, while onlyone driver TFT is ‘ON’ demonstrates a significant shift in thetrip point towards left in comparison to the case wherein bothdriver TFTs are ‘ON’. This is due to a weaker pull-up actionin the former case compared to the later one.

Subsequently, the NAND logic with tied inputs demon-strates an increment of 6 and 4 % in the VO H for DLL andZVLL, respectively in comparison to the case, wherein, onlyone of the inputs is swept and other remains in a ‘high’ state.The ZVLL configuration outperforms the DLL ones for allthe combinations of inputs. Compared to DLL, it shows animprovement of 20, 68 and 25 % in the voltage swing, gainand noise margin, respectively while sweeping both inputsV1 and V2.

In order to analyze the dynamic behavior, a square pulse of10 V magnitude is applied at a frequency of 1 KHz. Similarto the static response; the propagation delay is also inputdependent. The transient response of NAND gate in the DLLand ZVLL configurations is shown in Fig. 9a for the pulseapplied at V1, while V2 is consistent at a logic ‘1’. Similarplots for pulse applied at both inputs, V1 and V2 are presentedin Fig. 9b.

The static and dynamic parameters such as output swing(VS), noise margin (NM), gain and delay times for differentinput combinations are summarized in Table 2. Comparedto DLL, the propagation delay is higher in ZVLL mode. ForDLL NAND configuration, it is one-third of that of the ZVLLcounterpart (for V1 = 0 → 1/1 → 0 and V2 = 1) due tosignificantly higher strength of the pull-up network and large

0 2 4 6 8 100

2

4

6

8

10

NAND Gate

DLL (V1=0→1,V2=1)

ZVLL (V1=0→1,V2=1)

DLL (V1=V2=0→1)

ZVLL (V1=V2=0→1)

V OU

T (V

)

VIN (V)

0 2 4 6 8 100

-1

-2

-3

-4

-5

VIN (V)

Gai

n

NAND Gate

DLL (V1=0→1,V2=1)

ZVLL (V1=0→1,V2=1)

DLL (V1=V2=0→1)

ZVLL (V1=V2=0→1)

(a)

(b)

Fig. 8 Characteristics plots of a VTCs and b Gain for NAND gate inDLL and ZVLL configurations with different combinations of V1 andV2

pull-down current in the DLL. When both inputs are sweptsimultaneously, a significant reduction of 26 and 16 % inpropagation delay is observed for DLL and ZVLL, respec-tively, since the strength of the pull-up network is doubled.As observed in Fig. 9b, the output voltage rises quickly sinceboth the drivers are turned ‘ON’. The transient behavior ofNAND gate for all four input patterns is shown in Fig. 10.

The NAND gate, demonstrates improved performanceunder input condition V1 = V2 = 0 → 1, in comparisonto the case when the inputs are V1 = 0 → 1 and V2 = 1.This improvement is due to the doubling of pull-up networkstrength. The NAND gate in DLL (ZVLL) shows an improve-ment of 8(11), 48(58), 30(43) and 26 %(16 %) in voltageswing, gain, noise margin and propagation delay, respectivelyfor the input condition (V1 = V2 = 0 → 1) in comparisonto V1 = 0 → 1 and V2 = 1. During low-to-high outputtransition, the worst-case delay occurs when only one driveris ‘ON’. As a result, the worst-case input-to-output signal

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0.0 0.5 1.0 1.5 2.0

0

2

4

6

8

10

DLL

V IN,V

OU

T (V

)

t (ms)

V1

V2

ZVLL

NAND Gate

0.0 0.2 0.4 0.6 0.8 1.0

-2

0

2

4

6

8

10

V1

DLL

V1=0→1,V2=1

V1=0→1,V2=1

V1=V2=0→1

V1=V2=0→1

NAND Gate

t (ms)

V IN, V

OU

T (V

)

ZVLL

(a)

(b)

Fig. 9 Transient response of NAND gate for a V2=10 V and V1 sweep-ing from 0 → 10 V & 10 → 0 V and b Different combinations ofV1 and V2

delay (τP L H ) is higher by two and three times for DLL andZVLL, respectively in comparison to the condition, whenboth drivers perform the pull-up action together.

3.2 Organic NOR logic circuits

The schematics of two-input NOR gate realized in the DLLand ZVLL configurations is shown in Fig. 11a, b, respec-tively, wherein two dual-gate organic driver transistors (TD1

and TD2) are in series. This series network pulls-up the output

0 1 2 3 4

0

2

4

6

8

10

DLL

V IN, V

OU

T (V

)

t (ms)

ZVLL NAND Gate

V2V1

Fig. 10 Transient response of NAND gate for all four combinationsof V1 and V2

voltage only when both driver transistors are turned ‘ON’.However, if any one of them or both driver transistors are‘OFF’, the load transistor, TL will pull-down the output volt-age.

All three transistors are connected in series, therefore, thecurrent in NOR circuit with both inputs set to ‘0’ can beexpressed as

(Ids)TL= (Ids)TD1

= (Ids)TD2(8)[

μ Cox W/L

2

(Vgs − Vt

)2]

TL

= [μ Cox W/L

{(Vgs − Vt

)

Vds − V 2ds

2

}]TD1/TD2

(9)

Considering both driver transistors of the same strength, anequivalent driver-to-load ratio is obtained as

kR = 0.5 (μ Cox W/L)TD1/TD2

(μ Cox W/L)TL

(10)

Thus, the NOR logic circuitry with both inputs tied to a logic‘0’ is similar to an inverter circuit with driver-to-load ratioreduced to half [47]. The DC characteristics of NOR gate,while sweeping V1(0 → 1) and keeping V2 at ‘0’, is shownin Fig. 12.

Table 2 Static and dynamicparameters of DG-OTFTs basedNAND gate in DLL and ZVLLconfigurations

Input condition Load logic Performance parameters

VS (V) NM (V) Gain τP L H (µs) τP H L (µs) τp(µs)

V2 = 1, V1 = 0 → 1/1 → 0 DLL 6.1 3.7 −2.1 12 50 31

ZVLL 7.1 4.2 −3.3 41 152 97

V1 = V2 = 0 → 1/1 → 0 DLL 6.6 4.8 −3.1 6 40 23

ZVLL 7.9 6.0 −5.2 14 147 81

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V2

VOUT

TD2

TL

V1

VDD=10V

TD1

V2

VOUT

TD2

TL

V1

VDD=10V

TD1

(a) (b)

Fig. 11 Schematics of NOR gate in a DLL and b ZVLL configurations

0 2 4 6 8 10

0

2

4

6

8

10

VIN (V)

V IN, V

OU

T (V

)

NOR Gate

ZVLL

DLL

V1

V2

Fig. 12 VTC of NOR gate in DLL and ZVLL with V2 = 0 V & V1 =0 → 10 V

The NOR gate attains a lower magnitude of output (VO H )

in comparison to the NAND gate due to voltage drop acrosstwo driver transistors connected in series. However, in NANDlogic this drop is less due to only one transistor, therebyresulting in a higher VO H comparatively. Compared to theNAND characteristics (V2 = ‘1′, V1 = 0 → 1), the NORgate (V2 = ‘0′, V1 = 0 → 1) shows a reduction of 9 and6 % in VO H for DLL and ZVLL configurations, respectively.

The plots of DC characteristics and gain for the DG-OTFTs based NOR gate (DLL and ZVLL) are shown inFig. 13a, b, respectively with different combinations of twoinputs. Compared to DLL, the gain is two times higher inZVLL configuration due to larger output swing and sharperhigh-to-low output transition. Similar to the NAND gate, theNOR characteristics are also dependent on the input com-binations. It is observed that the load transistor performs astrong pull down action if both driver transistors are ‘OFF’.

0 2 4 6 8 100

2

4

6

8

10

VIN (V)

NOR Gate

DLL (V1=0→1,V2=0)

ZVLL (V1=0→1,V2=0)

DLL (V1=V2=0→1)

ZVLL (V1=V2=0→1)

V OU

T(V

)

0 2 4 6 8 10

0

-1

-2

-3

-4

VIN (V)

Gai

n

DLL (V1=0→1,V2=0)

ZVLL (V1=0→1,V2=0)

DLL (V1=V2=0→1)

ZVLL (V1=V2=0→1)

NOR Gate

(a)

(b)

Fig. 13 Characteristics plots of a VTCs and b Gain for NOR gate inDLL and ZVLL configurations for different combinations of inputs, V1and V2

Therefore, the magnitude of output (VO L) is slightly higherwhen only one transistor remains ‘OFF’, thereby resulting ina reduction of 9 and 4 % in the voltage swing for DLL andZVLL, respectively. This can be understood on the basis ofthe leakage currents in organic transistors.

For the case, when both transistors are ‘OFF’, the leak-age current is lower due to a significant increase in theequivalent OFF-resistance of the two transistors connectedin series. However, a higher leakage current flows if onlyone of the transistors is turned ‘OFF’ resulting in a compar-atively higher VO L , thereby shifting the trip point towardsthe left side as shown in Fig. 13a. Similar to prior outcomesthe propagation delay of NOR gate is lower in DLL con-figuration in comparison to ZVLL, as shown in Fig. 14a, b.The performance of NOR gate is better in ZVLL configura-tion in comparison to DLL mainly in terms of voltage swing(VS), noise margin (NM) and gain, as summarized in Table 3.Compared to DLL, it shows an increment of 24 and 30 % in

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J Comput Electron

0.0 0.5 1.0 1.5 2.0

0

2

4

6

8

10

DLL

V IN,V

OU

T (V

)

V2

V1

ZVLL

t (ms)

NOR Gate

0.0 0.2 0.4 0.6 0.8 1.0

-2

0

2

4

6

8

10

V1=V2=0→1

V1=V2=0→1

=0→1,V2=0

V1

V1

=0→1,V2=0

t (ms)

V IN,V

OU

T(V

)

DLL

ZVLL

V1

NOR Gate

(a)

(b)

Fig. 14 Transient response of NOR gate for a V2 = 0 V and V1 sweep-ing from 0 → 10 V & 10 → 0 V and b Different combinations of V1and V2

voltage swing and noise margin, respectively in ZVLL (atV2 = 0 and V1 = 0 → 1).

On the contrary, the τP L H in DLL is one-fourth of thatof the ZVLL, due to significantly larger W/L ratios of thedriver transistors in DLL configuration. Besides this, a sig-nificant reduction of 67 % in τP H L is noticed for the DLL incomparison to the ZVLL configuration due to a larger pull-down current. The transient response of NOR gate for all fourcombinations of V1 and V2 is plotted in Fig. 15 that validatesthe NOR logic in both DLL and ZVLL configurations.

0 1 2 3 4

0

2

4

6

8

10

DLL

V IN, V

OU

T (V

)

t (ms)

NOR Gate

V1

ZVLL

V2

Fig. 15 Transient response of NOR gate for all four combinations ofV1 and V2

4 Future perspectives

This section discusses the scope for enhancing the perfor-mance of devices and circuits in the future. Organic mater-ial based devices and circuits are the field of intense acad-emic and commercial interest for more than three decades.A p-type DG-OTFT is technologically more preferable inenhancing the robustness of organic circuits such as inverters,ring oscillators, SRAM, RFID tags [16,27,28,46]. Further-more, some other complex digital integrated circuits suchas flip-flops (FFs), shift-register, counters, arithmetic logicunit (ALU), and differential amplifiers can be realized usingp-type DG-OTFT.

Organic electronics is relatively an exciting and innovativefield of research that requires serious efforts to achieve largercurrent, higher speed, higher density and lower power con-sumption by using novel device structures. Inclusion of mod-ified structures including; multigate, floating gate, nanowireFETs, vertical, cylindrical and Fin-FET are necessary forhigh performance OTFTs.

The electrical and physical properties of active layer mate-rials (conducting polymers or small molecules) are controlledby the way the polymer chains or molecules are placed inthe solid state. Despite of recent developments in p- and

Table 3 Static and dynamicparameters of DG-OTFTs basedNOR gate in DLL and ZVLLconfigurations

Input condition Load logic Performance parameters

VS (V) NM (V) Gain τP L H (µs) τP L H (µs) τP (µs)

V1 = 0 → 1/1 → 0 V2 = 0 DLL 5.9 4.6 −2.1 17 63 32

ZVLL 7.3 6.0 −4.1 66 190 128

V1 = V2 = 0 → 1/1 → 0 DLL 6.5 4.4 −1.7 18 57 36

ZVLL 7.6 5.7 −4.4 68 165 117

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n-type materials, there is an ample scope for synthesizingmaterials with high mobility, large size grain and better sur-face morphology. Some of the primary obstacles in improv-ing the performance of n-type OTFT is the susceptibility ofOSCs to water and oxygen under ambient conditions. Sev-eral n-channel transistors can be operated when processedand tested under inert condition only that makes them tech-nologically unattractive. One can make an effort to optimizethe properties and characteristics of these OTFTs, such ashigh mobility and stability under ambient conditions. Fur-thermore, it is essentially required to look for high perfor-mance dielectric and electrode materials for improving over-all performance of device. For realizing organic devices inportable applications, some novel dielectric materials needto be realized that demonstrates high dielectric constant andlow leakage current. In addition, in-depth investigation ofthe novel contact material is required that can support betterinjection of electrons in the LUMO of n-type materials. Forflexible devices, novel conducting polymers such as PEDOT:PSS and PANI-CSA can find their usage for realizing con-tacts.

Performance optimization of an organic material baseddevice is a big challenge that includes various factors, suchas contact resistance, channel resistance, gate induced drainleakage, process induced variation effects, mobility, impactof semiconductor-dielectric interface and charge injectionat the contact-semiconductor interface. Mobility can beimproved by obtaining large grains of active material byoptimizing the deposition process. A surface treatment andself-assembled monolayer of the dielectric can be helpfulto modify the microstructure of organic semiconductor thin-films chemically. Performance improvement of bottom con-tact structures is still a formidable challenge.

5 Conclusion

This research paper compared the performance of all-porganic NAND and NOR gates in DLL and ZVLL configu-rations. The logic gates are designed using dual gate organictransistors. Favourably, both logic gates demonstrate betterperformance in terms of noise margin, voltage swing andgain in ZVLL configuration than DLL but at the cost ofslower response. The DLL circuits are faster due to largerpull-down current. Compared to DLL, the NAND (NOR)gate (at V1 = V2 = 0 → 10V) in ZVLL mode demonstratesan improvement of 20(17) and 25 %(30 %) in voltage swingand noise margin, respectively. Besides this, the gain is alsohigher by 1.7 and 2.5 times for ZVLL NAND and NOR gates,respectively. On the contrary, NAND and NOR gates in DLLconfiguration demonstrate an improvement of 72 and 69 %in propagation delay in comparison to ZVLL. Realization ofthese gates using organic TFTs demonstrates the possibil-

ity of producing logic circuits on the flexible substrate andthus proves to be a positive step towards low cost organicelectronics.

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