Standard Products Application Note...ber n in the directory name is the decimal equivalent of the selected binary value of the iB50Ctrl bit, while m is the dec-imal equivalent of the

Standard Products

Application Note UT90nHBD 3.125Gbps SerDes IBIS-AMI ModelFebruary 2015www.aeroflex.com/HiRel

1. Introduction

The UT90nHBD 3.125 Gbps SerDes is a quad-lane, full-duplex SerDes macro, designed to provide ASIC and system design-ers with high-speed serial interface capabilities for distributed system solutions. The serial interface consists of four sepa-rate transmit (TX) and receive (RX) current-mode logic (CML) serial lanes, capable of performing high-speed serial signal conditioning with the aim of power-efficient transmission channel loss compensation. The transmitter CML interface is equipped with a two-tap Feed-Forward Equalization (FFE) circuit, which provides for independent control of the transmit-ter output signal amplitude and de-emphasis. Each one configured via an independent 4-bit control register. The receiver CML interface is equipped with a Variable Gain Amplifier (VGA), which provides for post-transmission variable signal amplification (or attenuation), configured via a 4-bit control register. For detailed information on the TX FFE and the RX VGA, please refer to the UT90nHBD 3.125 Gbps Quad SerDes Macro Datasheet.

Beginning with version 5.0, the IBIS standard buffer model incorporates the Algorithmic Modeling Interface (AMI) portion, which provides channel simulator support for the signal conditioning capabilities of the SerDes TX/RX CML interfaces. The TX/RX IBIS-AMI buffer models enable the system designers to accurately and quickly perform high-speed transmission channel analysis, using EDA channel simulator software platforms such as Mentor’s HyperLynx or Keysight’s ADS, allowing for fast identification of the optimal TX/RX signal conditioning settings for maximized far-end signal eye opening and min-imized SerDes macro power consumption.

2. Transmission Line and Signal Integrity Background

Typical high-speed serial transmission channel acts as a low-pass filter that attenuates the high-frequency components of the transmitted signal spectrum. In distributed systems such as routed backplanes and cable-interconnected chassis, the high-speed serial signal is likely to traverse many different transmission media, each one compounding the transmission losses of the previous, resulting in a heavily distorted signal at the input of the far-end RX buffer. Figure 1 illustrates the high-speed serial signal distortions resulting from the transmission channel losses (Stauffer et al. 10-14) .

Figure 1. Typical Transmission Channel Signal Distortion

- 1 -950022-000Ver. 1.0.0 Aeroflex Microelectronic Solutions - HiRel

Figure 2 illustrates the effects of the TX FFE signal conditioning on the far-end received signal waveform. The received sig-nal is shown to have significantly improved signal fidelity compared to the received signal waveform shown in Figure 1 (Stauffer et al. 10-14).

Figure 2. High-speed Serial Signal Waveform with TX FFE

The utilization of the TX FFE results in spectral power redistribution of the transmitted serial signal. The effect is a simulta-neous attenuation of the lower frequency components and boosting of the higher-frequency components, thus equaliz-ing the effects of the signal losses incurred through the transmission channel. Figure 3 illustrates the effects of the post-receive equalization on the received signal waveform. The effects are very similar to those of the TX FFE (Stauffer et al. 10-14).

Figure 3. High Speed Serial Signal Waveform with RX Post-equalization

3. UT90nHBD SerDes IBIS-AMI Transmitter Model Structure and Usage

The UT90nHBD 3.125 Gbps SerDes IBIS-AMI model is compatible with version 5.1 of the IBIS-AMI standard. Due to the large number of amplitude and de-emphasis combinations and flexible TX CML buffer bias control bits yielding 896 possible combinations for the TX CML output waveform, the UT90nHBD SerDes IBIS-AMI model is subdivided into eight separate independent IBIS-AMI model file sets. Each file set corresponds to a specific combination of the iB50Ctrl and TX_IADJ[1:0] macro bias control bits.

The file sets are grouped into individual directories with the following nomenclature: aero_serdes_9sf_nm. The num-ber n in the directory name is the decimal equivalent of the selected binary value of the iB50Ctrl bit, while m is the dec-imal equivalent of the two-bit binary number represented by the TX_IADJ[1:0] bits. For example, a directory named aero_serdes_9sf_13 houses the IBIS-AMI model file set for the case of the binary numbers


iB50Ctrl = 1 (decimal 1) and TX_IADJ[1:0] = 11 (decimal 3). For detailed information on the iB50Ctrl and TX_IADJ[1:0] macro bias control bits, please refer to the UT90nHBD 3.125 Gbps Quad SerDes Macro Datasheet.

The eight separate model directories must be setup in the corresponding model search path of the channel simulator soft-ware in use so they can be independently selected and assigned to the TX buffer model in the channel simulator model scenario. The model selection is done by choosing the appropriate .ibs file that resides in each model directory. For example, to select the model file for the aero_serdes_9sf_13 model, the user should select the aero_serdes_9sf_13.ibs file in the channel simulator buffer/IC model selector.

Each of the eight separate TX IBIS models are subdivided into 10 separate AMI models, with each one being representative of a specific amplitude setting as selected by the TX_AMP[3:0] macro configuration bits. The valid range of selected val-ues for these bits is decimal 6 to 15 (binary 0110 to 1111). The user will select the desired amplitude setting in the AMI model selector section of the given channel simulator. The TX_AMP[3:0] control bits set the TX amplitude of the precur-sor bit, while the TX_PEC[3:0] bits scale the amplitude of the 0-th bit down to a de-emphasis level in the TX serial data stream.

Finally, each of the selected amplitude settings is associated with a specific range of de-emphasis settings, labeled as Equalizer Index numbers (EQ_Index variable) that equate to the TX_PEC[3:0] bit settings. This range of index numbers represents the allowed de-emphasis settings for the given amplitude setting.

A complete summary of all amplitude and de-emphasis settings grouped per the various iB50Ctrl and TX_IADJ bias set-tings is given in the Excel file titled SerDes_90nm_Tx_Step.xls. The individual iB50Ctrl and TX_IADJ combinations are represented by the separate TXnm worksheets where, as in the case of the IBIS-AMI model files, n and m are the corre-sponding decimal values for the selected iB50Ctrl and TX_IADJ bias control bits, respectively. Each of the available trans-mitter amplitude range selections is represented by the corresponding average peak-to-peak differential amplitude value (vpp_pr in the worksheet) for the given range. The average value is calculated from all valid index values (de-emphasis set-tings) for the given amplitude range. The average amplitude calculations for each amplitude range are given next to the index selection table in each of the TXnm worksheets. In addition to this master file, each of the individual IBIS model directories hold the corresponding Excel summary file for that particular IBIS model. The nomenclature for this file is txnm_step.xls where n and m are the corresponding decimal values for the selected iB50Ctrl and TX_IADJ bias control bits, respectively.

4. UT90nHBD SerDes IBIS-AMI Receiver Model Structure and Usage

The UT90nHBD SerDes Receiver IBIS-AMI model represents the Variable Gain Amplifier (VGA) and the Clock-Data Recovery (CDR) functionality of the UT90nHBD 3.125 Gbps SerDes. The VGA of the receiver provides for 16 separate selections of the VGA_Index values with a range from 1 to 16, which correspond to the RX_GN[3:0] control bits with a decimal value range of 0 to 15 of the input gain setting (UT90nHBDDatasheet page 21, Table 9). The receiver IBIS-AMI model varies only slightly with iB50Ctrl change and is embedded in each of the aero_serdes_9sf_nm.ibs files. The model for each .ibs file is summarized in the rxn_step.xls files where n is the value of the iB50Ctrl bit as in the case of the transmitter.

Both the TX and the RX IBIS-AMI buffer models contain an embedded 100 Ohm termination, so no additional termination modeling is needed in the channel simulator model scenario. Additionally, each of the models contains the signal charac-teristics for the typical, minimum, and maximum IBIS speed corners. “Typical” denotes the typical process model, nominal VDD, and 25°C. “Minimum” is the slow process model, minimum VDD, and 125°C. “Maximum” is fast process model, maxi-mum VDD, and -55°C. The receiver IBIS-AMI model provides the user with the option to select the signal output by modify-ing the value of the OutputSelect variable. A value of 0 will select the output of the VGA for displaying of the simulated receiver signal eye diagram, while a value of 1 will select the output of the CDR.


5. UT90nHBD SerDes IBIS-AMI Model Simulation Strategy and Practical Example

To illustrate the use of the UT90nHBD SerDes IBIS-AMI model, we present the Mentor’s HyperLynx channel simulator mod-eling scenario of Aeroflex’s UT90nHBD 3.125 Gbps Quad SerDes evaluation board available to order at www.aeroflex.com/HiRel. The UT90nHBD SerDes evaluation board consists of a high-speed dielectric PCB substrate with a flip-chip mounted UT90nHBD Quad SerDes test chip assembled onto a high-speed application board with parallel and serial interfaces as shown in Figure 4.

Figure 4. UT90nHBD 3.125 Gbps Quad SerDes Evaluation Board

The equivalent S-Parameter channel simulator model of the evaluation board above is shown in Figure 5. This model incor-porates all of the components of the evaluation board and the test chip PCB substrate as well as few additional compo-nents such as a power splitter and the associated SMA cables that enable simultaneous measurement and observation of the far-end receiver signal eye diagram using a jBERT and a high-bandwidth sampling oscilloscope. The receive buffer in the model in Figure 5 does not have an associated IBIS-AMI model and is represented with an ideal 100 Ohm termination of a generic buffer model. This modeling approach allows for subdividing the modeling problem into two separate model-ing scenarios. The first scenario deals only with modeling of the optimal TX amplitude and de-emphasis settings with the aim of obtaining the maximum-opening receive signal eye diagram at the input of the receiver buffer VGA. The second scenario will add the receive buffer IBIS-AMI model with the aim of determining the optimal VGA gain setting selection. This strategy is particularly useful in applications where the channel losses are significant (greater than -10 dB at the fre-quencies of interest).

Figure 5. UT90nHBD SerDes Evaluation Board HyperLynx Model

The ideal termination of the simulation model depicted in Figure 5 is equivalent to the termination of the evaluation board system that is achieved by sending the high-speed serial signal output from the SMA_SHRT S-Parameter block, into a dif-ferential input port of an oscilloscope or a BERT as shown in Figure 4.

To select an approximate starting point for the TX amplitude and FFE analysis, the user should analyze the S-Parameter fre-quency characteristics of the complete transmission channel to determine the total insertion loss at the line frequency of


1.5625 GHz for a data rate of 3.125 Gbps. Figure 6 illustrates the complete channel S-Parameter response up to a frequency of 10 GHz, of the channel model shown in Figure 5.

Figure 6. UT90nHBD SerDes Evaluation Board S-Parameters

The green and the red traces represent the total return loss S11 in dB and the insertion loss S21 in dB respectively, of the complete transmission channel with the associated block diagram shown in Figure 5. The white and the blue traces repre-sent the return loss S11 and is the insertion loss S21 of the power splitter blocks J6 and J7 in the block diagram. The power splitter is a broadband S-Parameter network with an S21 response that doesn’t vary much over frequency and should be subtracted from the complete channel insertion loss, when determining the starting point amplitude and de-emphasis settings. The graph in Figure 6 demonstrates that the insertion loss of the complete channel at 1.5625 GHz is -11.25 dB while the power splitter’s is -6.38 dB, yielding a line rate insertion loss of approximately -4.87 dB. Thus, selecting an EQ_Index setting from a given txnm_step.xls file that yields a TX de-emphasis compensation of approximately 4.87 dB will result in a receiver signal eye diagram with a maximum eye opening for the given IB50Ctrl and TX_IADJ[1:0] bias bit settings. The choice of the actual bias bit settings is dependent on the user’s goal for power consumption, total channel loss compensation and far-end eye diagram opening margins.

To assign the desired aero_serdes_9sf_nm.ibs model file for use, the user should double-click the transmitter buf-fer symbol in the block diagram in Figure 5 and select the appropriate .ibs file from the list of available device libraries.


Once the desired .ibs file has been highlighted, the user should click the “Model Selector” button, and highlight the desired amplitude range setting, as shown in Figure 7.

Figure 7. UT90nHBD SerDes IBIS-AMI HyperLynx Model Selector Options

The amplitude values shown for each amplitude AMI model selector option are the average differential peak-to-peak val-ues for all of the valid de-emphasis index settings in the selected amplitude range (as shown in each of the txnm_step.xls summary files).

To run the transmitter IBIS-AMI channel analysis, the user should configure the following settings in each of the corre-sponding setup steps:

• Choose New/Saved Analysis -> New• Time-Domain or Statistical Analysis -> Time-Domain• Setup Channel Characterizations -> New/View

• Bite rate: 3.125 Gbps• IC Modeling: Typical for Nominal VDD and 25°C (use Slow-Weak for Minimum VDD ad 125°C or Fast-Strong for

Maximum VDD and -55°C)

• Automatic or Manual Characterization: Automatically characterize Channel• Channel response: ISI effects are gone after 1,000 bit intervals, Number of warmup bits before the TX/channel

are stable: 1,000 (these settings imply a use of series DC blocking capacitors in the channel)• Characterization type: PRBS (click Generate PRBS Waveforms).

NOTE: Once the amplitude selection for a given .ibs file has been changed or a new .ibs file has been selected, the user will need to re-characterize the channel for the new .ibs file/amplitude selection

• Configure AMI Models -> Configure Tx AMI• Tx_Jitter -> Format: DjRj (Min Dj: -0.02, Max Dj: 0.02, Sigma: 0.014).

NOTE: The jitter numbers are typical for the Nominal VDD and 25°C operating corner. The numbers will vary with manufacturing process and operating condition variations.

• EQ_Index: The desired index that yields the calculated de-emphasis compensation in dB• CornerCase: This variable is set with the IC Modeling option selection above

• Sweep AMI Model Settings• Select the EQ_Index numbers to sweep for comparison

• Define AMI Stimulus• Bit rate: 3.125 Gbps• Bit pattern - > Type: 8B/10B


The receiver IBIS-AMI simulation is configured as follows:

• Configure AMI Models -> Configure Rx AMI• VGA_Index: The desired variable gain setting (range 1 to 16)• OutputSelect: 0 for VGA, 1 for CDR

6. UT90nHBD SerDes IBIS-AMI Model Simulations and Measurements Comparison

The following section provides an overview of the simulated to measured eye-diagram comparisons for eight different combinations of TX bias settings with amplitude and de-emphasis settings for the UT90nHBD SerDes Evaluation Board shown in Figure 5.

Figure 8. Simulation and Measurement Comparison - iB50Ctrl=0, TX_IADJ[1:0]=00, (IBSI-AMI file aero_serdes_9sf_00.ibs), EQ_Index=114















7. Works Cited

UT90nHBD 3.125Gbs SerDes Datasheet Rev1.2. pg.9-16, 20-21

Stauffer, David A. et. al., High Speed SerDes Devices and Applications. IBM Corporation, 2009. pg. 10-14


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Standard Products Application Note...ber n in the directory name is the decimal equivalent of the selected binary value of the iB50Ctrl bit, while m is the dec-imal equivalent of the