Stacked Horizontal Nanowire based 3-D Integration

for Future High Performance Computing

Mostafizur Rahman (rahmanmo@umkc.edu)

University of Missouri-Kansas City

In Memory

Circuits

Beyond

CMOS Boolean

Gates

Asymmetric

Circuits

Digital FETs

Analog FETs

Detector Receiver

Spin torque

(SFET, ASL,

STO..)

Straintronics

(MESH,MTJ)

Memristor

(TMO, 2-D

insulators..)

PCM

(GST, GES..)TFET

(III-V,

gnTFET..)

3-D

circuits

Approximate

gates

Probabilistic

circuits

Neural Nets

Synaptic

Circuit

Implication

Logic

Majority

Logic

Multivalued

Circuits

Threshold

Gates Binary

Gates

Circuit Layer

Device Layer

Beyond CMOS Opportunities

Ferroelectric

(NCFET, P-

FET..)

Quantum

Gates

Quantum

SearchQuantum

Algorithms

Gates Entangler

Architecture

/Application

Layer

SRC: Intel BCB 2017, SRC NRI, ITRS

FETs

FETs

Spin

RRAM

Qubit

Integrated TSV

Wire Bonding

TSV Stacked Memory

Heterogenous Dies with TSVs

Monolithic 3-D

Single Wafer

Multi-Chip Planar Wire and Pad Bonding

Silicon Interposer

2.5-D

3-D

2-D

Logic Density

Wafer-Wafer

Die-Die

Device-Device

3-D IC Classification

SN3D Fabric Overview

• Architected components to address device, circuit, connectivity, heat management and manufacturing requirements in 3-D

• Stacked nanowires are building blocks

Stacked Horizontal Nanowire based 3-D IC (SN3D) Fabric

Connectivity Comparison

SGI

Substrate

GI

LI

Substrate

SGI

GI

HIHBCGCC

SNW

MIVs

GI

SGI

LI

LI

N-Tier

P-Tier

TSV

GI

LI

Die 2

SGI

GI

LI

SGI

Die 1

2D CMOS

Monolithic 3-D (M3-D)

Multilithic 3-D

SN3D

• SN3D uses nanowires in a single die based process

• Local connectivity through fabric features

Outline

• SN3D Core Components and Logic

• Benchmarking

• Thermal Management

• Cost Analysis

Gate(TiN)

Gate(Ti)

(ii) Common Gate

Core Components

• Fabric assembly by Integration of core components• Intrinsic thermal management – stark contrast to other 3-D direction

Stacked Nanowires

NW ChannelGate Oxide(HfO2) Contact

Gate(Ti/TiN)

Spacer (Si3N4)

(i) Common Contact

Contact(Ni)

Contact(Al)

Junctionless Transistor

Nanowires

(iii) Horizontal Bridge

BridgeHorizontal Isolation

(SU8/SiO2)

Horizontal Insulation(HI)

• CMOS circuit style

• Uses both n- and p-type V-GAA Junctionless transistors

• Fabric specific physical mapping

• Local interconnection, noise and delay mitigation through utilizing fabric features and circuit optimizations

Full Adder Design in SN3D

• Fabric specific physical mapping

• High drive strength transistors

• Stacked(series) Inverters – CC-CG

SRAM Cell Design in SN3D

Parallel Nanowires (3xTpd) Inverter(X1) – 1xTpu:3xTpd

CGCC CCCG

CC CC

D

D

Vdd

Gnd

Vdd

Gnd D

D

X1

X2

Gnd

Gnd

Vdd

Vdd

DD

DD

TA1

WlBl

Bl Wl

TA2

Sp-nw

St1 St2

HB-CC

HB

HB

Wl

Wl

Bl

Bl

Bl Bl

Tpd

Vdd

Vdd

Vdd

Gnd

Gnd

D

D

X1

X2

Gnd

Tpu

Tpu

Tpd

Tpd

TA1

TA2

SN3D SRAM Array Organization and Benefits

Two Adjacent Cells

21

34

55

Top view

C2

5 54

3

12

4

C1

C1 C2

Bl

Gnd

WlVddWl

Bl

Bl

Gnd

Bl

- Metal 2- Metal 1

Metal Routed Layout

• Sharing FVs (BL, BL, Wl, Vdd, Gnd)– 2 Effective FVs for each cell• 3D Abutment of adjacent Cells

SRAM Array in SN3D

Bl

Bl

Gnd

Wl Vdd Wl

Bl

Bl

Gnd

Bl

Bl

Gnd

Bl

Bl

Gnd

Bl

Bl

Gnd

Gnd

Wl Vdd Wl Wl Vdd Wl Wl Vdd Wl

3D View of SRAM Array

Design Benefits

Gnd

Gnd

Bl

WlVdd

z

45 l

26 l

Bl

6T-Cell 2D-CMOS Layout

PMOS t ier

Wl

Bl

NMOS tier

Vdd Gnd VddBl

27 l

30 l

6T-Cell M3D Layout

Bl

Gnd

VddWl

Bl

Bl

Gnd

Bl27 l

14 l

6T-Cell SN3D Layout

• 3:2:1 ratio for all designs• TSVs add additional area overhead • M3D is limited to two tier design, only 30% reduction in footprint• M3D needs high precision alignment of inter-tier-vias

Benchmarking : Methodology Experimental

Results

SN3D TCAD ProcessSimulation

3-D TCAD Device I-V Simulation

3-D TCAD Device C-V Simulation

Device Modeling for HSPICE simulation

SN3D Circuit and Layout Design: Logic, SRAM etc.,

Interconnect Extraction (PTM Model)

RC calculations

Density Evaluation

Design Rule

SN3D Circuit (Logic, SRAM) HSPICE Simulation

Functionality, Power and Performance Evaluation

Benchmarking Results

Performance/power for SN3D and M3D vs. 2-D

• 6.4x performance/power, 67% area reduction for SRAM

• >10x area reduction, 19% and 18% performance and power improvements for logic

0

20

40

60

80

100

120

PER

CEN

TAG

E

2-D MONOLITHIC 3D SN3D

Percentage Reduction in SRAM Footprint

30.7%

67.8%

Logic Benchmarking Results

RM =175.87mV

D (V)0.0 0.2 0.4 0.6 0.8 1.0

1.0

0.2

0.4

0.6

0.8

0.0

D (

V)

WM =380.25mV

D (V)0.0 0.2 0.4 0.6 0.8 1.0

1.0

0.2

0.4

0.6

0.8

0.0

D (

V)

HM =325.54mV

0.0 0.2 0.4 0.6 0.8 1.0

1.0

0.2

0.4

0.6

0.8

0.0

HM =325.54mV

D (

V)

D (V)

Noise Margin

0 1 2 3 4 5 6 7

1

SN3D M3D 2-D

6.4X

1.2X

[2] Naveen Macha, Sandeep Geedipally, Mostafizur Rahman, NANOARCH 2017, pp. 155-161, 2017.

[3] N. K. MacHa, and M. Rahman, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017, submitted.

[1] N. K. MacHa, M. A. Iqbal, and M. Rahman, NANOARCH, 2016, pp. 51-152.

Outline

• SN3D Core Components and Logic

• Benchmarking

• Thermal Management

• Cost Analysis

Thermal Effect

[5] R. Rhyner, Mathieu Luisier., Nano Lett., 2016, 16 (2), pp 1022-1026, DOI: 10.1021/acs.nanolett.5b04071.

[6] Md Arif Iqbal, Mostafizur Rahman, IEEE S3S Conference, San Fransisco, CA, 2017.

300

nm

Transistor(P-Type)

Interconnects

W (Via)

Substrate/Heatsink

SiO2 (Dielectric)

Transistor(N-Type)

Heat Flow

415

410

405

400

395

390

385

380

• Self-heating exacerbates for vertical/SOI FETs• Lack of heat dissipation paths in 3-D is a key problem for hotspot

Monolithic 3-D circuit’s thermal profile

Thermal Simulation Methodology

• The Conductive heat transfer in solids is obtained by:ρCp ∂T/∂t+ ∇ .(-k∇T) = Q

• Finite Element Based Method (FEM) for fine-grained modeling

Region MaterialDimension

(LxWxT)nm

Thermal

Conductiv

ity

Wm-1 K-1

Drain Silicide 10 x 16 x 16 45.9

Drain

Electrod

e

Ti 10 x 16 x 12 21

Channel Doped Si 16 x 16 x 16 13

Source Silicide 10 x 16 x 16 45.9

Gate

OxideHfO2 16 x 18 x 2 0.52

Gate

Electrod

e

TiN 10 x 16 x 6 1.9

Spacer Si3N4 10 x 16 x 16 1.5

DEVICE MATERIALS AND THEIR

DIMENSIONSThermal Modeling of Interconnects, Contacts. Power rails, Signal Nanowires, Devices

and Power Pillars

Thermal Modeling of 3-D Circuit

3-D Circuit Layout

Heat Flux from HSPICE

Electrical Simulations

Calibration

3-D Thermal Profile

Equivalent Electrical Representation and HSPICE Simulation

FEM Thermal Simulations

FEM MethodThermal Circuit Simulation Method

Thermal Simulation Results (FEM)

• Temperature reduction by 53% to 375K from 700K

• Heat Pillar was effectively dissipating heat from heated region

• Heat Pillar can be shared among neighboring FETs

• Highest temperature was 375K for top transistors

FET based Circuit with Features Transient Thermal Behavior of each FET with and without FeaturesSeveral FETs Connected to Single Pillar for Heat Dissipation

Effectiveness of Heat Extraction Features

• SN3D’s connectivity features enable heat extraction

• Heat Junction and Heat Pillar reduces heat further– Can be customized to meet

thermal requirements

Heat Flow

Nano-Pillar

Substrate/Heatsink

SiO2 (Dielectric)

CC

CC

CG

CC

CG

CC

CC

CC

Transistor

Transistor

HB 378

377.5

377

376.5

376

375.5

SN3D circuit’s thermal profile

[6] Md Arif Iqbal, Mostafizur Rahman, IEEE S3S Conference, San Fransisco, CA, 2017.

Outline

• SN3D Core Components and Logic

• Benchmarking

• Thermal Management

• Cost Analysis

Early Cost Estimation Methodology

(TSVs 3D and M3D)

Die Area

# Metal Layers

#ProcessSteps

Temperature

CoolingCost

BondingCost

Metal LayerCost

Die-Cost

Processdependency

𝐶𝑑𝑖𝑒 = 𝑐𝑝𝑑𝐴𝐷𝑖𝑒

𝐶𝑚𝑒𝑡𝑎𝑙 = 𝑐𝑝𝑚𝑛𝑚𝐴𝐷𝑖𝑒

𝑐𝑝𝑑 , 𝑐𝑝𝑚T

Inter-connects

Circuit Density

Fabrication Process

Die Bonding

Cooling

Design phase information

Cost variables

Major Cost Dictating Aspects

SN3D Design Rules, Guidelines

SN3D Circuit Design Principles

Area Estimation(2D,3D,M3D,SN3D)

Interconnect Estimation(2D,3D,M3D,SN3D)

Metal Layer Estimation(2D,3D,M3D,SN3D)

Cost Estimation

(2D,3D,M3D,SN3D)

3-D Interconnects(TSVs, MIVs, FIs)

Cooling Cost

(2D,3D,M3D,SN3D)

Bonding Cost

(3D,M3D)

Cost Model

Die Area Estimation4

3.5

3

2.5

2

1.5

1

0.5

Are

a (

mm

2 )

5.0E+06 10.0E+06 20.0E+06

Ng-Number of gates in the design

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5.00E+06 1.00E+07 2.00E+07

A2D

A3D

AM3D

ASN3D

SN3D Area

2D Area

3D Area

M3D Area

Average Gate Area 2-D :

Average Gate Area 3-D/M3D :

SN3D Average Gate Area:

86%, 72% and 74% reduction in footprint compared to 2D, T3D and M3D respectively [7]

3125 l2 [8]

Area Comparison

3125 l2

2

432l2

𝐴2𝐷/𝑆𝑁3𝐷 = 𝑁𝐺𝐴𝐺,2𝐷/𝑆𝑁3𝐷𝐴3𝐷/𝑀3𝐷 = 𝑁𝐺𝐴𝐺,3𝐷/𝑀3𝐷 + 𝑁𝑇𝑆𝑉/𝑀𝐼𝑉𝐴𝑇𝑆𝑉/𝑀𝐼𝑉

SN3D Gate Area

[7] N. K. MacHa and M. Rahman, IEEE S3S Conference, San Fransisco, CA, 2017.

[8] X. Dong, J. Zhao, and Y. Xie, IEEE Trans. Comput. Des. Integr. Circuits Syst., vol. 29, no. 12, pp. 1959–1972, 2010.

Rent’s Correlation for Terminal Count:

Interconnect Estimation

[2] N. K. MacHa and M. Rahman, Available: https://arxiv.org/abs/1709.01965.

[7] N. K. MacHa and M. Rahman, IEEE S3S Conference, San Fransisco, CA, 2017.

൯𝐼𝑇 = 𝛼𝑘𝑁𝐺(1 − 𝑁𝐺𝑝 [2]

𝑇𝑆𝑁3𝐷 =

𝑖=1

𝑛

𝑇𝑖 = 𝑛𝑘𝑁𝐺𝑛

𝑝

Total Interconnect

ሻ𝑖 𝑙 = 𝑓(𝑁𝐺 , 𝑙, 𝑘, 𝑝[7] ;Distribution

Inte

rco

nnec

t D

ensi

ty F

unct

ion

, i(l

)

1.0E-01

1.0E+00

1.0E+01

1.0E+02

1.0E+03

1.0E+04

1.0E+05

1.0E+06

1.0E+07

1 10 100 1000 10000

1E7

1E6

1E5

1E3

1E2

1E1

1E0

0 10 100 10001E-1

1E4

i(l)2D i(l)3D i(l)SN3D

Interconnect length, l [Gate pitches]

1.0E-06

1.0E-04

1.0E-02

1.0E+00

1.0E+02

1.0E+04

1.0E+06

1 10 100 1000Interconnect Length, l (gate pitches)

Inte

rco

nnec

t D

ensi

ty F

unc

tio

n,

i(l)

1.0E-06

1.0E-04

1.0E-02

1.0E+00

1.0E+02

1.0E+04

1.0E+06

1 10 100 1000 10000

Metal 1

Metal 2

.

.

Metal i

.

Metal n

Lav,1

Lav,2

. . .

Lav,i

. . .

Lav,i

METAL LAYER ESTIMATION

Ng 2-D CMOS TSV 3D M 3D SN3D

5 M 5 5 3 3

10 M 6 5 4 3

20 M 7 6 5 4

Metal Layer Estimates

12%

32%16%

18%22%

PhotolithographyDiffusion EtchingDepositionImplantation

nPL= number of Photolithography steps

nDF= number of Diffusion stepsnET= number of Etching stepsnDP= number of Deposit ion stepsnIM= number of Implantation steps Unit Process Constant (kc)

cPD=kc

nPL=1

nIM=1 nDF=1 nET=1 nDP=1

11

Parameterizing Process Steps

SN3D Process Constant(26.54kc)

nPL=2

nIM=0 nDF=40 nET=51 nDP=2

11

cPD=26.54kc

PROCESS STEPS Process 2D [10] 3D/M3D SN3D Metal [6]

Photolithography(nPL) 9 19 2 2

Diffusion(nDF) 4 8 2 -

Implantation(nET) 7 14 - -

Deposition(nDP) 4 10 40 4

Etching(nIM) 5 13 51 4

Arbitrary unit process constant: Relative Cost of the Major Process steps[5]:

Typical Process steps Count:

Quantifying Process Sequence Major Processes:• Photolithography• Diffusion• Etching • Deposition• Implantation

Relative Cost Statistics[9]

𝐶𝑆𝑁3𝐷= 26.54𝑘𝑐𝐴𝑆𝑁3𝐷 +

2𝑘𝑐𝑛𝑚𝐴𝑆𝑁3𝐷 +𝐶𝑐𝑜𝑜𝑙𝑖𝑛𝑔

𝑐𝑝 = 0.32𝑛𝑃𝐿 + 0.22𝑛𝐷𝐹 + 0.18𝑛𝐸𝑇 + 0.16𝑛𝐷𝑃 + 0.12𝑛𝐼𝑀 𝑘𝑐

𝑘𝑐 = 𝑘𝑃𝐿 + 𝑘𝐷𝐹 + 𝑘𝐸𝑇 + 𝑘𝐷𝑃 + 𝑘𝐼𝑀 𝑘𝑃𝐿 = 0.32𝑘𝑐; 𝑘𝐷𝐹 = 0.22𝑘𝑐; 𝑘𝐸𝑇 = 0.18𝑘𝑐;𝑘𝐷𝑃 = 0.16𝑘𝑐 ; and 𝑘𝐼𝑀 = 0.12𝑘𝑐

[6] N. K. MacHa and M. Rahman, Available: https://arxiv.org/abs/1709.01965.

[9] Y. Lai, “Cost Per Wafer,” Imid 2009, pp. 1069–1072, 2009.

[10] James D. Plummer, et al., ed. New Jersy: Prentice-Hall, 2000, ch. 2, pp. 49–92.

Cost Estimation Results

𝐶2𝐷 = 6.26𝑘𝑐𝐴2𝐷 + 2𝑘𝑐𝑛𝑚𝐴2𝐷 + 𝐶𝑐𝑜𝑜𝑙𝑖𝑛𝑔𝐶3𝐷/𝐶𝑀3𝐷 = 7.26𝑘𝑐𝐴3𝐷 + 2𝑘𝑐𝑛𝑚𝐴3𝐷 + 𝐶𝑏𝑜𝑛𝑑𝑖𝑛𝑔 + 𝐶𝑐𝑜𝑜𝑙𝑖𝑛𝑔

𝐶𝑆𝑁3𝐷 = 26.54𝑘𝑐𝐴𝑆𝑁3𝐷 + 2𝑘𝑐𝑛𝑚𝐴𝑆𝑁3𝐷 + 𝐶𝑐𝑜𝑜𝑙𝑖𝑛𝑔

• No Bonding Cost for SN3D• Bonding Cost for TSV 3-D and M3-D are

taken as a relative cost from [11]

• Cooling Cost: 1 𝐶𝑐𝑜𝑜𝑙𝑖𝑛𝑔 = 𝐾𝑐𝑇 + 𝑐

Final Cost Models:

0

10

20

30

40

50

60

70

80

90

100

COST 2D COST 3D COST M3D COST SN3D2D0

10

20

30

40

50

60

70

80

Ng-Number of gates in the design

Pri

ce in

un

its

of K

c

90

3D M3D SN3D

Die cost

Cooling cost

Bonding cost

Metal cost

Cost Comparison Results

[11] X. Dong, J. Zhao, and Y. Xie, IEEE Trans. Comput. Des. Integr. Circuits Syst., vol. 29, no. 12, pp. 1959–1972, 2010.

83% and 81% reduction in total cost compared 2-D CMOS Monolithic 3-D integration

[7] N. K. Macha and M. Rahman, IEEE S3S Conference, San Fransisco, CA, 2017.

[13] D. Sacchetto, et al., ESSDERC, Athens, Greece,September 14-18, 2009.

SN3D Implementation Aspects

[12] M. Rahman, et al., “Skybridge : 3-D IntegratedCircuit Technology Alternative to CMOS,” pp. 44.

[14] Ricky M. Y. Ng et al., IEEE ElectronDevice Lett., vol. 30, no. 5, pp. 520–522,2009.

[15] M. Rahman, et al., IEEENANO 2015 -15th Int. Conf. Nanotechnol., pp. 1214–1217, 2016.

Summary

• Beyond CMOS opportunities span different application domains

• 3-D Integration is obvious choice for moving forward

– Highest advantage with monolithic 3-D

• SN3D is a new stacked nanowire based 3-D IC technique

– Integrated device, circuit, connectivity and heat management

– Possibility of >10x density benefits

– 83% cost reduction compared to 2-D CMOS

Acknowledgements

• Csaba Andras Moritz (Umass Amherst)

• Santosh Khasanvis (Bluerisc)

• Pritish Narayanan (IBM)

• Masud Chowdhury (UMKC)

• Kelin Kuhn (Cornell, prev. Intel)

Sponsors

NSF, Univ. of Missouri Research Fund