SSI Gate Level Designs

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Verilog structural Modelling

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1) 4-bit FULL ADDER

2) 3-BIT COMPARATOR USING 1-BIT FULL ADDER

3) AYNCHRONOUS 3 BIT COUNTER USING T-FF

4) ASYNCHRONOUS RESET 3BIT COUNTER

5) ASYNXHRONOUS 3 BITCOUNTER WITH MANY ALWAYS BLOCK

6) SYNCHRONOUS 3 BIT COUNTER

7) SEQUENCE GENERATOR 11101110