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8/13/2019 Srikanth Reddy Paramaiahgari 1206321047 Project Part2
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Srikanth Reddy Paramaiahgari EEE591:AIC Lab Final Project ASU ID# 1206321047
PART 2
LDO Schematic:
Buffer PMOS Selection:
PMOS buffer is used because there will be better matching between the cascade amplifier stage and the Buffer
stage.PMOS buffer is preferred as substrate and source are at same potential and in NMOS source and bulk are
at different potential.
Pass Transistor PMOS Selection:
PMOS pass transistor is used since Vin and regulated voltage vary by small amount (.25V) and NMOS cannot
be used as gate voltage (2.25+Vtn) needed in this is greater than maximum voltage available i.e. 2.5V and it
requires additional charge .
8/13/2019 Srikanth Reddy Paramaiahgari 1206321047 Project Part2
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Srikanth Reddy Paramaiahgari EEE591:AIC Lab Final Project ASU ID# 1206321047
Pass Transistor Design:
Hand analysis:
8/13/2019 Srikanth Reddy Paramaiahgari 1206321047 Project Part2
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Srikanth Reddy Paramaiahgari EEE591:AIC Lab Final Project ASU ID# 1206321047
8/13/2019 Srikanth Reddy Paramaiahgari 1206321047 Project Part2
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Srikanth Reddy Paramaiahgari EEE591:AIC Lab Final Project ASU ID# 1206321047
Theoritical Gain= -gm*rds= -gm/gds = 194.9 mA/V/3.412 mA/V= 64.66 V/V = 36 dB
8/13/2019 Srikanth Reddy Paramaiahgari 1206321047 Project Part2
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Srikanth Reddy Paramaiahgari EEE591:AIC Lab Final Project ASU ID# 1206321047
8/13/2019 Srikanth Reddy Paramaiahgari 1206321047 Project Part2
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Srikanth Reddy Paramaiahgari EEE591:AIC Lab Final Project ASU ID# 1206321047
Simulations:
Width of pass transistor for different I loads are shown in simulations below (1 mA, 25m A, 50 mA)
8/13/2019 Srikanth Reddy Paramaiahgari 1206321047 Project Part2
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Srikanth Reddy Paramaiahgari EEE591:AIC Lab Final Project ASU ID# 1206321047
Gain plot for I Load=25 mA
8/13/2019 Srikanth Reddy Paramaiahgari 1206321047 Project Part2
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Srikanth Reddy Paramaiahgari EEE591:AIC Lab Final Project ASU ID# 1206321047
Rin: for f= 1KHz = 1/ 4*10^-8 =25 M Ohms
Rout: for f=1 KHz= 1000/7.15 = 139.8 Ohms
8/13/2019 Srikanth Reddy Paramaiahgari 1206321047 Project Part2
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Srikanth Reddy Paramaiahgari EEE591:AIC Lab Final Project ASU ID# 1206321047
Buffer Design:
Hand Analysis:
8/13/2019 Srikanth Reddy Paramaiahgari 1206321047 Project Part2
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Srikanth Reddy Paramaiahgari EEE591:AIC Lab Final Project ASU ID# 1206321047
8/13/2019 Srikanth Reddy Paramaiahgari 1206321047 Project Part2
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Srikanth Reddy Paramaiahgari EEE591:AIC Lab Final Project ASU ID# 1206321047
8/13/2019 Srikanth Reddy Paramaiahgari 1206321047 Project Part2
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Srikanth Reddy Paramaiahgari EEE591:AIC Lab Final Project ASU ID# 1206321047
Simulations:
Rin: Rin= 10^9/1.37= 0.729 G Ohms
8/13/2019 Srikanth Reddy Paramaiahgari 1206321047 Project Part2
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Srikanth Reddy Paramaiahgari EEE591:AIC Lab Final Project ASU ID# 1206321047
Rout: 10^5/1.46= 68.4 K Ohms
Gain of the buffer is approximately equal to one.
8/13/2019 Srikanth Reddy Paramaiahgari 1206321047 Project Part2
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Srikanth Reddy Paramaiahgari EEE591:AIC Lab Final Project ASU ID# 1206321047
Full system Schematic:
8/13/2019 Srikanth Reddy Paramaiahgari 1206321047 Project Part2
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Srikanth Reddy Paramaiahgari EEE591:AIC Lab Final Project ASU ID# 1206321047
Gain Vs Frequency plot:
Gain of differential amplifier with RC load as observed from the part 1 was 56.02 dB
Gain with the buffer is now 51.23 dB.
And bandwidth with RC load was 817.8 KHz and bandwidth with Buffer is 1.51 MHz.
So the RC load assumption we made in part 1 was fairly reasonable.
Observations:
The input resistance of PMOS buffer is very high and the output resistance is low. So the input resistance of
buffer is matched with the output resistance of the Differential amplifier and the output resistance of buffer is
matched with input resistance of pass transistor. So there will be efficient transfer of power from one stage to
other.
Hand analysis calculated gain for pass transistor is 36 dB which is close to simulated value of 32 dB.