SRAM Generator

-Satya Nalam

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Motivation

SRAM is an integral part of most SoCs

Goal: Automate SRAM design process Technology-independence User-independence

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Overview

SRAM Optimizer

Schematic script

Layout script

SRAM schematic

SRAM layout

leaf cells

Designparams

leaf cells

DESIGNER

(Cadence SKILL)

Project Scope

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SRAM Architecture SRAM specs

Single bank Capacity – 8-32kb Col-mux – 1,2,4,8 #Rows – 8-512 #Rows and #cols

power of 2 Timing block using

encounter Schematic/Layout

script for tiling each block

Wrapper script to generate final SRAM

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Programmable leaf-cell design

E.g. Vias programmed in SKILL for decoder/WL Driver

Sized by SRAM optimizier

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Routing by abutment

Routing taking care of internal to leaf cell

Leaf-cell 1

Leaf-cell 2

Signal between two leaf cells – E.g. WL between WL Driver and Bitcell

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ExampleDifferent column circuitry layouts generated

Default, Col-mux=1

Different SA

Col-mux=4

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Status Completed:

Full schematic-generation scripts Leaf-cell layout scripts

To do: Top-level layout script

Usage/Testing: Schematic generation (FreePDK)

STT-RAM (Anurag) Schematic + Layout generation (ST 65)

BL-leakage cancelling SA (Sudhanshu) Single-ended SA (Joe)

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Future work

Automating leaf-cell layout design Py-cell approach

Tie optimizer with SRAM generator E.g. Write optimizer output to config Reduce human intervention

Further improve user/technology-independence