SR: 599 report

Channel Estimation for W-CDMA on DSPs

Sridhar Rajagopal ECE Dept.,

Rice University

Elec

599

SR: 599 report

Organization

W-CDMA.

DSPs in Wireless Communications.

Channel Estimation.

Aim of the 599 Project.

Implementation Issues and Results.

Future Architectures for Wireless systems.

Conclusions and Future Work.

SR: 599 report

W-CDMA

Third Generation Communication Systems.

Multimedia Capabilities.

Multirate Services.

Quality Of Service.

Higher Data Rates.

– 2Mbps, 384kbps, 144kbps.

SR: 599 report

DSPs in Wireless Communications

Digital Signal Processor.

Signal Processing Communications.

Features :– Low Power Consumption (1.2 V, 100 mW).

– Low Cost (15$).

– High Performance (100 MIPS).

SR: 599 report

The Wireless Channel : Multiuser, Multipath

Direct PathReflected

Paths

Faces Attenuation, Delays and Doppler Effects : Unknown Channel Parameters

Antenna

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At the Receiver

DECODER DETECTOR DEMODULATOR

RCHANNEL ESTIMATOR

A, UZ

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ML Channel Estimation

Send a Preamble.

Channel properties embedded in received signal.

Compare and estimate.

Keep estimate for remaining data bits (static).

Repeat preamble every frame, if no tracking.

SR: 599 report

Data Transmission in W-CDMA

Mobile #

1.

2.

3.

4.

5.

: time

C1

C7 C3

C2

C2

C8

C4

C4

C1

C2

Packet Preamble for AcquisitionPacket for Data Transmission

DS-CDMA with Slotted ALOHADS-CDMA with Slotted ALOHA

SR: 599 report

W-CDMA- Implementation Issues

Computationally intensive algorithms.

Stringent Time, Power, Size constraints.

Pressure on existing hardware resources.

Real -time Requirements :

1ms 10ms

0.25

ms

Preamble Message

Random Access Burst in Slotted ALOHA

SR: 599 report

Aim of the 599 Project

Get a grasp of– W-CDMA.– DSPs.– Channel Estimation.

Implement ML Channel Estimation on DSPs.

Evaluate its performance (“Execution Time”).

Ways to improve the performance.

Future Architectures for Wireless Communications.

SR: 599 report

COMMON

The ML Algorithm Complexity

Complex -Real Dot Product.

Complex-Real Matrix Product.

Complex -Real Product.

Real Square roots.– Solving quadratic equation for least squares fit.

r.bL1

Rbr

1

bbbr RRY

1''

212)(*)(

UUUUUyUyz L

k

L

k

R

k

R

k

L

k

H

k

R

k

H

k

H

k

Assuming Unity Noise CovarianceAssuming Unity Noise Covariance

Offline

SR: 599 report

TI TMS320C6701 EVM

32-bit Floating Point DSP at 133MHz.

– VLIW Architecture (8 IPC).– 8 Functional Units ( 2 Multipliers).– 32 registers in 2 files.– 64 Kb each Internal Program and Data Memory.

External Memory.– 256 Kb SBSRAM (Static RAM : faster).

– 8 Mb SDRAM (Dynamic RAM : slower).

SR: 599 report

Steps in DSP Implementation

Original Floating Point Code.

Remove File I/O.

Minimize use of functions.

Minimize use of temporary variables. Pre-computed Data (Offline).

Use Specialized Approximate Instructions.

Use Assembly Code for critical part.

SR: 599 report

Use of Approximate Instructions

0 5 10 150

20

40

60

80

100

120

140 Use of Approximate instructions in the DSP

Number of users -->

Exe

cutio

n tim

e (in

mill

isec

onds

) -->

Base C67 code C67 Code with Approximations

TMS320C67x DSP Cycles

Approx. FPReciprocalinstruction

1

FP reciprocalfunction

28

Approx. FPReciprocal Sq. root

Instruction

1

FP Reciprocal Sq.root Instruction

34

L = 150, P =3, N= 31, SNR = 5dB, SINR = -10 dB

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Use of Assembly Code

0 5 10 150

20

40

60

80

100

120

140

Number of users -->

Exe

cutio

n tim

e(in

mill

isec

onds

) -->

Use of Assembly code in the DSP

C67: Original C67: with approximationsC67: with Assembly C67: potential

Assembly Codeused

Dot Product

Matrix VectorMultiplication

L = 150, P =3, N= 31, SNR = 5dB,

SINR = -10 dB

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Comparison with UltraSPARCII

0 5 10 150

10

20

30

40

50

60

Number of Users -->

Exe

cutio

n tim

e (in

mill

isec

onds

) -->

Execution time for DSP and GPP for ML Channel Estimation (Parameter Extraction)

C67: Assembly C67: Potential UltraSPARC II UltraSPARC II with VIS

UltraSPARCII

•Super-scalar

•4-way in-order

•250 MHz

•VIS support

L = 150, P =3, N= 31, SNR = 5dB,

SINR = -10 dB

SR: 599 report

Joint Estimation and Detection

•Improvement in performance as only subset of parameter extraction.

•Improvement in detector also?.

L = 150, P =3, N= 31, SNR = 5dB, SINR = -10 dB

0 5 10 150

5

10

15

20

25

30

Number of users

Exe

cutio

n tim

e(m

illis

econ

ds)

Performance of Channel Estimation using joint estimation and detection on "C67

Joint Method Parameter extraction

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Memory Issues

•Data sizes do not fit in Internal memory.

• Onus on Programmer.

•External Memory Latencies.

•Affects performance

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Improvements in Architecture

Internal Memory.– More internal memory required - On-chip DRAMs.

Data Prefetching.– Matrix oriented operations - Prefetch Buffers.

ASIC/FPGA Support.– Offload critical computations (Viterbi Decoder in C54)

Specialized Instructions.– Array Based instructions, Complex Arithmetic.

SR: 599 report

Improvements in Compilers

Compiler Efficiency.

– VLIW Compilers unable to extract all parallelism.– Assembly language subroutines.– Advantages of Architecture not used fully.

OS Support.– Memory Allocation by Programmer.– May not be optimal / Leads to Errors.– Compiler should assist.– Suggestions acknowledged by TI.

SR: 599 report

Future Architectures for Wireless

Large On-chip Memory.

Low Cost / High Performance.

Low Power Consumption.

Multiple DSPs.

GPP-DSP-Coprocessor-ASIC-FPGA.

Vector IRAMs.

SR: 599 report

Conclusions

Studied ML Channel Estimation on DSPs.

Effect of Approximations (1.1X).

Effect of Assembly (2X).

GPP Comparison (0.2227 X for 15 users).

Joint Estimation and Detection (2.92X for 15 users).

Memory issues: Does not fit in Internal Memory.

Real-time Requirements: Application Dependant.

SR: 599 report

Future Work

Effects on Downlink.

Effects of A/D Converter.

Tracking, Multiple sensors, Doppler effects.

Subspace Based Channel Estimation.

Real-time Performance.

Architectures for Wireless Communications.