Chapter 7Conclusions and Future Directions

This book investigates challenges associated with TSVs in 3-D ICs. This workis innovative as it explores design and technology challenges, evaluates potentialbenefits, and proposes novel solutions. The results presented in this book advancethe understanding of TSV-based 3-D IC design and guide designers in selectingdesign and technology parameters.

7.1 Summary

This book offers original contributions in several key areas. First, a new technique inmitigating TSV-induced substrate noise is presented. We develop a realistic frame-work to study TSV-induced substrate noise. This framework uses a finite-elementthree-dimensional tool to extract lumped parasitics of the design setups. We use thisframework to evaluate the performance of different noise mitigation techniques interms of noise isolation and substrate area penalty. We report that shielding TSVsfrom devices using a dielectric liner is not sufficient to mitigate noise; substrategrounding is required. For this purpose, we propose a new technique, the GNDplug, to effectively ground the substrate. We show that the GND plug is a superiortechnology in reducing substrate noise while utilizing small area and minimizingthe keep out zone. For a 2 μm TSV in a 20 μm thick substrate, four GND plugsof diameter 0.5 μm fabricated around the TSV at a distance of 1 μm result insubstrate noise less than 8 % of the input voltage. We analyze the size and placementconsiderations of GND plugs to maximize noise isolation and to minimize areapenalty. The GND plug is a better technique than increasing the thickness of thedielectric liner or using a backside GND plane. Compared to using a 1.5 μm thickliner, a GND plug reduces substrate noise by 4.3× and reduces the area by 0.67×.Compared to a backside GND plane, the GND plug technique is simple and resultsin 4.3× performance improvement.

N. Khan and S. Hassoun, Designing TSVs for 3D Integrated Circuits, SpringerBriefsin Electrical and Computer Engineering, DOI 10.1007/978-1-4614-5508-0 7,© The Authors 2013

63

64 7 Conclusions and Future Directions

Second, we develop a trace selection strategy to speed IR power delivery analysiswithout compromising quality. This strategy utilizes an architectural model of theIC to extract block-level current traces and picks only representative ones. We usethis approach on 10 million traces from four benchmarks (apsi, bzip, equake, andmcf). We reduce the number of traces to 1,428.

Third, we perform the first architectural-level power delivery analysis for 3-DICs utilizing realistic workloads. Within this study, we analyze the impact of TSVsize and spacing to assess the trade offs between TSV area and PDN performance.We observe that PDN performance saturates for a TSV size of 25 μm and aTSV granularity of 32×32. Increasing the granularity of C4 bumps significantlyimproves PDN performance. In addition, we show that coaxial TSVs improve PDNperformance by providing additional decoupling capacitance, and that coaxial TSVsreduce interconnect and device blockage by overlaying power/signal routing withina single coaxial TSV.

Fourth, we investigate the problem of PDN design at early design stages toestimate required TSV area, allowing designers to arrive at total area and costestimates for 3-D implementations. To compare the performance of the TSV-estimation algorithms, we use a practical design consisting of three dies. Startingwith a minimal TSV area estimate and incrementing iteratively produces thesmallest number of TSVs compared to starting with a larger estimate and decreasingiteratively. This technique, IMPROVE WORST VIOLATION (IWV), resulted in a 40 %improvement in our evaluation framework.

Finally, we evaluate the use of carbon nanotubes for power delivery in 3-D ICsfor the on-chip power grid and for TSVs. We use a practical CNT model to calculateRLC values of CNT bundles. We use the IWV algorithm to estimate the total numberof TSVs required to deliver power within the noise budget. Our results show thatusing CNTs as TSVs provides at least 40 % reduction is TSV area when comparedto a Cu TSV implementation. A reduction of 71 % is achieved when CNTs are usedfor both on-chip power grid and TSVs. For the same substrate area dedicated toTSVs for power delivery, CNTs in a 3-D PDN perform better than Cu. CNTs arecapable of improving the average voltage drop by 40 % and 18 % for IR and Ldi/dtanalysis, respectively.

7.2 Future Research Directions

Stacking of 3-D ICs is a new and emerging technology. This book covers a fewaspects of TSV-based 3-D IC design. A large number of design and technologychallenges still need to be met to bring 3-D IC technology to mainstream VLSIdesign. A few possible extensions and some future challenges include:

• The GND plug technique proposed in this book was evaluated using onlysimulations. Test chips with different configurations of TSVs and GND plugsare the next logical step in evaluating this technology. More complex couplingscenarios must be investigated to assess the impact of coupling.

7.2 Future Research Directions 65

• Analytical models and layout extraction tools are required to efficiently analyzedevice-to-TSV and TSV-to-TSV coupling.

• TSVs create thermal stress, which impacts the performance of neighboringdevices. Analysis tools to quantify the impact of thermal stress on deviceperformance and techniques to reduce this impact are required. Both TSV-induced noise and TSV-induced stress dictate the size of keep out zone fordevices. Further analysis of these two phenomenon needs to be performed tocreate new design rules for devices in 3-D ICs.

• Thermal management is a challenge in 3-D ICs. TSVs are proposed to extractheat from dies away from the heat spreader. Detailed analysis that considerdielectric liner and practical TSV placement are needed. Coupled thermal andpower delivery analysis is are required to estimate the substrate area needed forTSVs.

3-D integration is poised to deliver improved IC performance and heterogeneousdie integration. Solving 3-D design challenges will drive this technology, thusadvancing a wide range of medical, consumer, and high performance electronicsystems.