■ 18 IEEE CIRCUITS & DEVICES MAGAZINE ■ SEPTEMBER/OCTOBER 20048755-3996/04/$20.00 ©2004 IEEE

Asingle-ended staticmemory scheme com-bining advantages ofboth a one-transistor

dynamic RAM (DRAM) cell anda six-transistor static RAM(SRAM) cell is proposed in thisarticle. For the first time,optical bias is introduced,converting the classical comple-mentary metal-oxide semicon-ductor (CMOS) RAM to an opto-electronic device. The cellstructure is highly scalable andcost effective.

Various approaches andschemes were applied to combineadvantages of static and dynamicRAM memories, striving to shortenaccess times, lower power dissipa-tion, and decrease cell area. This isparticularly true for system-on-a-chip (SoC) [1] and embedded memo-ries [2], [3]. Here, the novel approachtowards the same goal is proposed andsimulated, introducing standardCMOS technology. A single-ended,three-transistor, fully static RAM cell isdemonstrated.

©DRAGAN JUHAZ

Goran Krilic

19 ■IEEE CIRCUITS & DEVICES MAGAZINE ■ SEPTEMBER/OCTOBER 2004

MEMORY CELL SCHEMEFigure 1(e) shows proposed SRAM cell consisting of onlythree NMOS transistors and one PMOS transistor. OneNMOS transistor acts as select transistor. Two NMOS transis-tors are connected in cross-coupled fashion and generatepositive feedback necessary for bistability. Instead of PMOSloads, two PN photodiodes, which are almost ideal currentsources [see Figure 1(c)] are connected to drains of crosscoupled transistors. Photodiodes are parasitic P + N diodes,representing Nwell − P + drain (source) of unactive PMOStransistors. Similar photodiode structures exist in a chip

form. Photodiode arrays in CMOS (0, 6-µm) are commercial-ly used for spatially distributed light detection for the use inoptical storage systems [4].

The memory cell (the whole chip) is exposed to low wave-length (red—650 nm) light from an LED diode aligned on topof the chip. The introduction of light to chip surface is notnew. In ultraviolet (UV) erasable, programmable read-onlymemory chips (EPROMs), UV light is used to erase memorycells through window on the top of the chip. Figure 1(d)shows equivalent circuits of parasitic photodiodes. Series resis-tance (Rs) is equal to PMOS drain (source) ohmic resistance,

1.(a) Absorption coefficient of photons in silicon. (b) Typical spectral responsivity. (c) Characteristic I-V curves of a typical photodiode(d) Equivalent circuit for the silicon photodiode. Iph is photocurrent, whereas Cj, RSH, and Rs are junction capacitance, shunt resistance

and series resistance respectively. (e) Three-transistor static cell circuit.

106

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/W)

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Reverse Bias (V) IncreasingIllumination

(c) (d)

IphId

Ci Rsh RL

RsI0

V0

+

–

Word Line Bit Line

+

+D2

D1

M5M3

M4C1

C2

C3200 fF

(e)

■ 20 IEEE CIRCUITS & DEVICES MAGAZINE ■ SEPTEMBER/OCTOBER 2004

and junction capacitance (Cj) is equal to zero-bias B-D (B-S)PMOS junction capacitances, which varies with voltage appliedin nonlinear fashion (determined by PMOS parameters MJbulk junction bottom grading coefficient)and MJSW (bulkjunction sidewall grading coefficient). Figure 1(b) shows typi-cal spectral responsivity characteristic (in A/W) for photodi-odes. Figure 1(c) shows typical current/voltage curves for aphotodiode for different light levels. Photoconductive (linear)and photovoltaic (nonlinear) modes exist for reverse and for-ward voltages, respectively.

SIMULATION SETUP AND RESULTSThe memory cell has two stable states, as shown in Figure 2(a)and (b), which shows computer simulation using INTUSOFTICAP/4 SPICE software of write and retention of “1” and “0” inmemory cell. The following NMOS model parameters were used:

✦ ICAP/4 LEVEL1 NMOS: VTO = 0.5 V/KP=3.1E_5A/V’2/GAMMA = 0.37V’0.5/PHI = 0.65 V/ LAMBDA= 0.02V/RD = 3E + 1W/RS = 3E+1W,CBD = 5 fF/ CBS= 5 fF/Is = 1E–15A/PB = 0.87 V/CGSO = 1E–11F/m / C G D O = 1 E – 1 1 F / m / C G B O = 5 E – 1 1 F / m

/MJ = 0.5/TOX = 1E–7 m/TNOM = 50oC/CJSW = 2.5E–8/MJSW = 0.5

✦ L = 1 um✦ Vdd = 3.3 V.

Bit-line capacitance C3 was chosento be moderate 200 fF (short bit lines).Level 3 and Level 6 models should bemore appropriate for simulating inte-grated devices. However, due to thecomplexity of the circuit (includingphotodiodes and bit-line precharge cir-cuitry equivalents) and several pulsegenerators, Level 1 enables much fastertransient analysis and better immunityto convergence problems, although theNMOS model itself is not so accurate.Nevertheless, the feasibility of a pro-posed memory cell at an integratedlevel is proved.

Photodiodes were replaced by anelectrical equivalent, a high-resistanceshunt (100 G�) in parallel with a con-stant current source (300 nA). Bit-lineprecharge and discharge circuitry issimulated by a constant current sourceand NMOS voltage clamping circuitusing a gate-drain connected, (nega-tive) voltage pulsed source NMOS tran-sistor. Output capacitance C1 wascalculated from current and voltagesimulation diagrams. It is approximate-ly 10 fF.

The proposed cell, although static,is operated (read and write) completelydifferently from a standard six-transis-tor CMOS SRAM cell. It has only oneselect transistor, thus, it operates sin-gle ended. Write and read operationsare performed exactly as in a one-tran-sistor dynamic RAM cell. Power con-sumption in read and write, withoutoptical power, which will be consideredlater, is identical as in a DRAM cell.Computer simulation of write 1/reten-tion and write 0/retention operationsshows the feasibility of the single-

2. (a) Write of logical 1 and retention. Photocurrent charges full level to the memory cell after 10 nswrite cycle and initial charging to 2.2 V (logical 1). Lower graph v(3) shows discharging of C2 to 0V.(b) Write of logical 0 and retention. Lower graph v(3) shows charging of C2 to 3.5 V. Photocurrent

linearly charges C2 until photodiode photovoltaic mode.

y1 v(3)

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21 ■IEEE CIRCUITS & DEVICES MAGAZINE ■ SEPTEMBER/OCTOBER 2004

ended operation. Figure 3 shows alternating Write 1 and Write0 operations. After first Write 0 operation, both C1 and C2 areat zero voltage, which results in an abrupt increase of outputvoltage in all subsequent Write 1 operations. Normally, ittakes several cycles for photocurrent to charge C2 to 3.3 V—logical 0 output (C1) is 0 V [Figure 2(b)]. In Write 1, a smallboost above Vdd at the word line, as in standard DRAMs, wouldbe required to enable cell output charging to full logical 1level (3.3 V). However, this is not necessary because photocur-rent from D1 will charge cell output capacitance to full logical1 level after only a few cycles [Figure2(a)]. Simulations also show that, dueto the nonsymmetric cell, after voltageand light switch on, the output statebecomes logical 0.

Read operation is particularly inter-esting because voltage difference on aprecharged bit line is detected by asense amplifier as in DRAM cell. Volt-age change also results from chargeredistribution between output (actingstorage) NMOS gate-source capacitanceand much larger bit-line capacitance.In read operations, word line is pulsedto 1.5 V, and bit line is precharged to0.5 V. When reading logical 0, selecttransistor charges the output capaci-tance of the cell [C1 in Figure 1(e)].The output transistor M4 [Figure 1(e)],has a 3.3-V gate (C2 charged to 3.3 V inlogical 0 output) and draws large cur-rent when output capacitance is evenslightly charged, thus keeping outputlow (100 mV maximum) during read-ing (see Figure 4, where a voltage ver-sus time diagram for cell outputcapacitance and bit line capacitance isshown). After an initial precharge to0.5 V in 10 ns, the bit line is dis-charged, resulting in a voltage swing of200 mV in 10 ns, which is sufficient todrive the sense amplifier.

When reading logical 1, select tran-sistor M3 draws current from the celloutput C1 which is high (3.3 V) and,thus, discharges output capacitance,simultaneously charging bit line capaci-tance. After an initial precharge to 0.5 V(Figure 5), bit-line capacitance voltageincreases for 100 mV in the next 10 ns.Cell output capacitance C1 is temporar-ily discharged to approx. 2.6 V. Afterreading, constant photocurrent fromphotodiode D1 is linearly charging C1back to 3.3 V and full level logical 1 isautomatically restored in next 20–40

ns. Small overvoltage results from photodiode photovoltaicmode operation, which is rapidly decreasing photocurrentexisting in small forward voltages. Considering that NMOSthreshold voltage is 0.5 V, NMOS 5 will not switch off and willcontinue to keep the gate of NMOS4 low, despite constantcharging from Photodiode D2. Figures 4 and 5 show nonde-structive read operation as in standard six-transistor CMOScells. Small bit-line precharge voltage is advantageous due tofast precharge and discharge of bit line. Depletion mode or lowthreshold enhancement mode transistors are suitable in sense

4. Read of logical 0. After 10 ns bit-line precharge to 0.5 V (v6-graph1) , charge redistributiondecreases bit line voltage for 200 mV in 10 ns read time without affecting cell charge which remains

low (y1-graph2). Graph3 –v4 shows word line voltage.

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3. Alternating write 1 and write 0 operations. Graph4 –v6 and graph3 –v4 represent bit line andword line write pulses respectively. Graph1 –y1 shows cell output in write1-pause-write0 multiple

streams, graph2 – v3 shows C2 voltage.

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■ 22 IEEE CIRCUITS & DEVICES MAGAZINE ■ SEPTEMBER/OCTOBER 2004

amplifiers to match low-voltageoperation. Read operation sim-ulation was also performedwith Vdd word line and Vdd/2bit-line voltages, as in moststandard DRAMs, and theresults are almost identical,though larger photocurrents were required. Simulations alsoshow that bit-line precharge voltages from 0.5 V-Vdd/2 areapplicable. Word line voltages 1–1.5 V larger than bit-line volt-age were required for proper operation. However, considerationof precharge voltage selection in relation to optimization of thesense amplifier, as regards sensitivity and its speed of opera-tion, is not subject of this article.

Considering technology issues, photodiodes are incorporat-ed as P+ areas (anodes substitute drain/source function ofPMOS transistor) in N well. Thus, technology for cell manu-facturing is 100% standard CMOS technology. The only differ-ence from a standard six-transistor CMOS static cell is that

one select (NMOS) and oneload (PMOS) transistors areremoved. In the remainingPMOS (load) transistor, N well(N+) is connected to Vdd, andP+ regions (drain and source)are connected to drains of

cross-coupled NMOS transistors. When illuminated, they func-tion as photodiodes. Between metal contacts and poly (gate),light penetrates to P+ drain and source (photodiodes’ anodes)region only, causing photocurrent (Figure 6). Light penetra-tion of low wavelength (red) light in silicon is only a fewmicrons [see Figure 1(a), which shows light attenuationaccording to Beer-Lambert law, which corresponds with ashallow and thin P + N depletion layer]. Figure 7 shows thechip cross-section incorporating classical CMOS inverters con-nection. Figure 6 shows two cross- coupled NMOS transistorsand two photodiodes of the proposed cell. Everything is tech-nologically identical except on Figure 6, N+ (guarding) is con-

nected (metalization) to Vdd and drain(anode) of unactive PMOS to the drainof the opposite NMOS transistor with-out forming new metal layer.

The gate can be left floating or con-nected to Vdd. Since the PMOS transis-tors are standard enhancement mode(standard CMOS), they will not operateunder positive gate-source voltage.

OPTICAL POWERAND TECHNOLOGYCONSIDERATION

In standby power, dissipation is below 1nW/cell, which corresponds to pho-tocurrents having strength in pA–nArange, equal to leakage currents. How-ever, in active mode, due to read opera-tion, particularly in the case of readinglogical 1, photocurrents have to be fewhundred nA (300 nA here) to maintainnondestructive read or automaticrefresh after read cycle. Thus, in activemode, power dissipation per cell is 0.75µW. Considering that photodiodesoccuppy only 25% of chip area that is100% exposed to LED diode light,required optical power is, for 288 kb(32 KB) memory, 860 mW in active and0.1 mW in standby mode, and 0,8 A/Wresponsivity is presumed. Leakage is 40pA (Figure 8). Proper scaling of memo-ry elements would give much betterresults regarding access speed andpower dissipation. Considering relative-ly low (15–30% maximum) standardLED external quantum efficiency, proper

5. Read of logical 1. After 10-ns bit-line precharge to 0.5 V (v6-graph1),charge redistribution increases bit-line voltage for 100 mV in 10 ns

read time without change of stored logical 1 (y1-graph2).Graph3—v4 shows word line voltage. Photocurrent charges cell to full

logical level 1 in just two cycles.

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6. Cross section of three transistor SRAM cell (CMOS). LED diode on top not shown.

Gate GateLight

Nwell

Vdd

Vdd

P-Substrate

P+ P+ N+ N+ P+ P+

Optical bias converts theclassical CMOS RAM to an

optoelectronic device.

LED-RAM chip (silicon diox-ide) alignment and LED sizingis essential in minimizingelectrical power dissipation.The optimization of electrical-optical parameters requiressubstantial experimentalwork. However, analysis ofalignment is similar to that ofoptocouplers except transpar-ent medium is ultrathin com-pared to optocouplers where thick layer is required forgalvanic insulation up to few thousand volts.

Fresnel losses resulting from refractive index mismatchand causing internal reflections are described using

T ′ = 4/ (2 + n2/n1 + n1/n2),

where T ′ is fraction of light transmitted and n1 is a semicon-ductor (3.6 for AlGaAs) and n2 is the oxide (approximately 1.5)refractive index. Thin film, having alarger refractive index, would increaseT ′ . The same equation is used foroxide-silicon (the silicon refractiveindex is 3.5) interface. If that fractionof light is marked T ′ , then totallytransmitted light is T = T ′ × T ′′ . Con-sidering external quantum efficiency,there are special patterned thin filmLED diodes that exhibit high externalefficiency up to 70% [5]. However theyare not suitable for this application.

The previously described memorycell can operate in pulsed mode. Lightsource can be pulsed at low frequency(<1 kHz) in standby and write modesto save energy. Information will not belost, it will be kept dynamicallybetween two light pulses [see Figure 8,which shows optical refreshing with 1-µs (20-nA) pulses applied each 500 µs(duty 1/500)].Without light, appliedphotodiodes act as decoupling diodesand memory cells function as dynamiccells. Hence, term self-refreshingDRAM would be more appropriate inpulsed mode. The most important fea-ture in optical refreshing is that lightcan be applied independently andsimultaneously with other cycle pulses.LED diode (red), which is necessary forlight input (bias), is cheap compared tothe price of memory chips. Averageprices for large volumes rate fromUS$0.10–0.30. The price should beeven lower without unnecessary plastic

encapsulation and lense. Thelow price is a result of LEDsmass production for microdisplays. Small rectangular orsquare LED diode sizes matchtypical chip sizes (few squaremillimeters). LED diodesoperate at 1.5–2.5 V, whichperfectly matches RAM chipsource voltages. Maximumoptical output powers are in

the 50–150 mW range, whereas dc forward currents are 20–40mA. Peak forward currents can reach sevenfold values, usuallyfor 1/10 duty cycle 0.1 ms pulse width. Optical power is linear-ly proportional to the photocurrent. In pulsed mode, opticalpower is larger, which is inversely proportional to the pulsewidth. Some mega bright miniature red LEDs exhibit lumi-nous intensity of 7,000 mcd (1,000 mcd/mm2) with drive cur-rents of 20 mA only. For 650 nm, 1,000 mcd = 13,698 mWoptical power per steradian.

23 ■IEEE CIRCUITS & DEVICES MAGAZINE ■ SEPTEMBER/OCTOBER 2004

8. Optical pulse refreshing, graph shows C1 voltage change. Leakage current linearlydischarges C1 which is refreshed with 1-µs (1/500 duty) light pulses.

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7. Chip cross section of standard inverter (CMOS).

Gate GateGate

Nwell

Metal 1VddVss Vss

P-SubstrateP-Substrate

Contact

P-SubstrateContact

P+ P+ N+ N+ P+ P+

Output 1 Output 1

Increased speed and avoidance ofexternal refresh are advantagestowards dynamic RAMs, while

reduced cell area are advantagestowards static RAM schemes.

Using special drivers to generate overshoots and under-shoots, LEDs can be pulsed to 300 Mb/s and even 1,000 Mb/s.It would enable bias LED diodes to be pulsed by clock signal inread mode. Consequently, read operation would remain non-destructive, whereas the optical power would be considerablyreduced compared to continuous operation. Further (optical)power saving can be achieved if the LED diode is replaced withan active LED matrix (x-y array), which can be activated(pulsed) only for addressed sections of memory chip in readmode. For example, ten LED segments would decrease opticaland electrical power tenfold.

In the CMOS process, after gate oxide growth, poly layer(gate) should not be deposited on the P channel transistor,thus leaving a large transparent area for light penetration inthe N well. After photogeneration of electron-hole pairs in theN well, they will diffuse to the P + N photodiodes’ depletionlayers and separate by electrical field generating photocurrent.This significantly increases the photodiodes’ photocurrents,particularly in relation to parasitic-unwanted photocurrentsthat are generated in drain (N+)-substrate (P) junctions ofactive NMOS transistors.

CONCLUSIONMemory cell operation has been simulated to show the feasi-bility of write, retention, and read operations. It is shown for3.3-V logic (3.3 V power supply). However it can work with 2 Vor less as well. Increased speed and avoidance of externalrefresh are advantages towards dynamic RAMs, while reducedcell area, while maintaining low power dissipation in standbyand pulsed mode, are advantages towards static RAM schemes.If destructive read is an acceptable penalty, rewriting afterread of logical 1 is required; total power dissipation per cell isdetermined by leakage only, which potentially allows gigabitSRAM. Some DRAM schemes [3] solve the problem of write-back impact on cycle time through multibanking and write-back buffers.

This cell circuit and operation are subjects of a U.S. patentissued and additional patent applications filed (patents pending).

REFERENCES[1] W. Leung, F. Hsu, and M. Jones, “The ideal SoC memory 1T-SRAM”

(white paper), MoSys, Sunnyvale, CA, Aug. 8, 2001.

[2] Z. Hu, P. Juang, P. Diodato, S. Kaxiras, K. Skadron, M. Martonosi, andD.W. Clark, “Managing leakage for transient data—decay and quasi-static4T memory cells,” in Proc. ISLPED’02, Monterey, CA, 2002, pp. 52–55.

[3] C.-L. Hwang, T. Kirihata, M. Wordeman, J. Fifield, S. Storaska, D. Pon-tius, G. Fredeman, B.J., S. Tomashot, and S. Dhong (2002). “A 2.9 nsrandom access cycle embedded DRAM with a destructive-read architec-ture,” in 2002 Symp. on VLSI Circuits Digest of Technical Papers[Online]. Available: http://www-306.ibm.com/chips/techlib/techlib.nsf/techdocs/E95CC111124D5A5587256DD6007DE26D/$file/C13p4.pdf

[4] I. Hehemann, E. Ozkan, H. Hofmann, A. Kemna, W. Brockherde, andB.J. Hosticka (2002). “A CMOS photodiode array with linearized spectralresponse and spatially distributed light intensity detection for the use inoptical storage systems,” presented at ESSDERC 2002 [Online].Available: http://www.essderc2002.deis.unibo.it/ESSDERC_web/Ses-sion_D21/D21_1.pdf

[5] M. Boroditsky, T.F. Krauss, R. Coccioli, R. Vrijen, R. Bhat, and E.Yablonovitch, “Light extraction from optically pumped Light-EmittingDiode by thin slab photonic crystals,” Appl. Phys. Lett., vol. 75, no. 8, pp.1036–1038.

[6] J. Genoe, D. Coppee, J.H. Stiens, R.A. Vounekx, and M. Kuijk, “Numeri-cal calculation of the evolution of the carrier distribution in the spatiallymodulated light CMOS detector,” in Proc. SAFE/IEEE Workshop, pp.49–52.

{7} M. Jutzi, K. Eve, W. Vogel, D. Wiegner, and M. Berroth, “Lateral PIN-photodetector in commercial CMOS technology operating at 1.25 Gbit/sand 850 nm,” in Proc. 7th Optics in Computing Technology Workshop,2002, pp. 55–62.

Goran Krilic is a cofounder of TRANSNET consulting compa-ny in Zagreb, Croatia. E-mail: gkrilic@vip.hr.

■ 24 IEEE CIRCUITS & DEVICES MAGAZINE ■ SEPTEMBER/OCTOBER 2004