Spectral PLL Built-In Self-Test for Integrated Transceivers · 2007-11-04 · Christian Münker - 13-Sep-2007 Page 4 of 21 Freq. Domain - Complex signal analysis - High dynamic range

Christian MünkerInfineon Technologies AG

Spectral PLL Built-In Self-Test for Integrated Transceivers

ESSCIRC 2007

Page 2 of 21Christian Münker - 13-Sep-2007

Outline

Stimulus GenerationStimulus Generation

Spectral Response AnalysisSpectral Response Analysis

Concept for Spectral PLL BISTConcept for Spectral PLL BIST

ConclusionConclusion

MotivationMotivation


Test Challenges for RF Systems-On-Chip

System tests now have to be performed by foundryMany circuit blocks are no longer directly accessibleMany RF tests are slow because of dynamic rangeUp to three test insertions for complex chips (D / A / RF)Increasing test costs @ falling production costs

Need to improve testability!


Freq. Domain- Complex signal analysis- High dynamic range

In-Band Spectrum (Phase Noise, Spurs, Modulation Mask)

Freq. Domain- No direct accessLoop Bandwidth

Time Domain - No direct access- Lots of failure modes

VCO / Divider Functionality

??? - Long averaging times- Very high dynamic range

Out-of-Band Spectrum (Phase Noise, Spurs)

Challenge BISTTest

Critical Productiontests for RF PLLs

RF PLL Test is complex and time-consuming!


Targets for PLL Built-In Self Test (BIST)

Speed-up production test No interference with critical RF paths on-chipLittle area overheadNo yield losses due to test circuitryDirect correlation to specification (frequency domain!)Suitable for Deep Submicron CMOS technologies

Digital implementation of BIST circuits!


Outline







Concept for Loop-Bandwidth Measurement

Estimate PLL bandwidth from FM distortion


Spectral PLL Built-In Self-Test (SP-BIST)

DUT is a SD-PLL withdigital modulationFully digital BISTLittle interaction withRF pathsSpectral analysison-chip


Outline







Baseband Test-Tone Generation

Two-tone signal generated with digital resonators

Modulation via digital PLL input, no recovery filter needed due to inherent low-pass characteristic

fSIG = 15 … 180 kHz with SFDR = 60 dB (15 bit WL)

Also useful for DAC and analog filter test (with 1b-DAC)

Lu & Roberts, 1998 CAS II, [ADC BIST]

A = 0.02 mm2


SFDR

: ca.

60 d

B

Two-tone Spectrum of Digital Sine Generator


Outline







Spectral Analysis Using Digital Blocks

Rail-to-rail signal on RF CMOS ICs

Small bandwidth of PLL signal

Carrier frequency is known on-chip

Only FM / PM modulation

Apply DigitalSignal

ProcessingTechniques!


1st Order Frequency Sigma-Delta Modulator

RF demodulation and quantization in one stepBuilding blocks can be copied from actual PLLRe-synchronisation to fref needed (not a big problem)But: Lots of spurious sidebands (1st order SDM)!

A = 0

.005

mm

2


Narrowband Filter and Envelope Detector

Multi-rate filter for lowest hardware requirementsSpectral analysis by narrow-band filtering instead of FFTBands of interest have to be measured sequentially4th order tunable BP with a freq. resolution of 300 HzAmplitude can be read via serial bus as static word

A = 0

.035

mm

2


Digital Resonator as Tunable Bandpass

Robust against coefficient truncation (only 9 bit wide!)Truncation error only influences center frequency, not noise performance or stabilityCenter frequency and BW can be set separately (kf, kbw)Simple structure and low sampling rate enable hardware reuse

Only 1 multiplier for 4th order bandpass!Can be expanded to filter bank for parallel multi-tone analysis


„Frequency Averaging“ Removes FSDM Spurs

Repeat measurements at different carrier freq. (∆f = 10 kHz)Remove data points differing by more than 10 dB“Frequency Averaging” improves spurs by ~ 30 dBTwo-tone stimulus gives much better FSDM spur behavior


Frequency Response Measurements (1)

Stimulus (Baseband) Demod. PLL Response


Frequency Response Measurements (2)

Performance of 1st order FSDM sufficient for loop BW measurement, but not for noise / spur analysis3 ms measurement time per data point Wrong BP type (const. BW instead of const. Q) creates systematic error (can be compensated)Too narrow BP misses spectral maxima (+/- 0.3 dB)

7.5

145

9.7

162

12.54.72.70.30Attenuation (dB)

1771251037364Frequency (kHz)


Conclusion and Results

Robust and compact Spectral BIST for RF PLLs (SP-BIST) has been realized in a 130 nm CMOS technologyTwo-tone test signals are generated with a completelydigital test oscillator FM RF signals are demodulated and analyzed with a digital FM discriminator and narrowband filterSpectral PLL BIST enables on-chip measurement of PLL spectral parametersSome improvements needed for full in-band analysis Additional chip area for BIST blocks 0.06 mm2


Documents

Spectral PLL Built-In Self-Test for Integrated Transceivers · 2007-11-04 · Christian Münker - 13-Sep-2007 Page 4 of 21 Freq. Domain - Complex signal analysis - High dynamic range