RPM Design Considerations2 The University of Queensland,
Australia
3 ASRC Aerospace Corp.
Collection of one or more modular stacks of computing
elements
RPM is core reconfigurable component hosting reconfigurable FPGA
fabric
125/MAPLD'05
RPM Design Considerations
PCI Interface – host to the Peripheral Component Interconnect (PCI)
Local Bus interface, Memory controllers, the Configuration Manager
(CM), and the Back-end interface (SLiP) to the reconfigurable
logic.
Memory Components – SDRAM and Flash devices for volatile and
nonvolatile storage. 3D-Plus (MMSD08256804S-C) 2Gbit (256Mbx8) 100
MHz
- Based on 512 Mbit Elpita part
- Use 3 parts for 4Gbit memory plus EDAC
Reconfigurable Logic – SRAM based reprogrammable FPGA (Xilinx
4VFX60)
Local Voltage Regulation – For 1.2V, 1.5V, and 2.5V supply
voltages. (Also 1.8V for the prototype.)
External I/O Connectors – SMPX, serial interface, discrete
I/O)
Kevin M. Somervill <
[email protected]>
Crossbar logic – potential enhancement to first pass architecture
if greater bandwidth is required
RapidIO – an attractive possibility, but considered to be too
costly and complex for most applications.
Hypertransport – Similar to RapidIO, it was considered to be
excessively more than needed.
125/MAPLD'05
RPM Design Considerations
Another alternative would be to use something like CoreConnect or
AMBA bus structures. This would entail discrete buses for
concurrent datapaths though.
Kevin M. Somervill <
[email protected]>
High Speed Serial Interface
TMR
In the Xilinx with XTMR tool and the Actel is TMR at the die.
Including I/O pins (3x for Unidirectional – 6x for
Bidirectional!!)
Data “Scrubbing”
SDRAM data
Pipelined error correction engine for 32-bit data/16-bit check
field
Single Error Correction Double Error Detection is the fall
back
Shielding for the stacks with overlapping carriers.
Radiation Tolerant components (target of 100krad)
Thorough Design Methodologies and popular development tools…
125/MAPLD'05
RSC
Somervill
Performability considers both reliability and performance aspects
in a unified model.
Petri nets provide a mathematically based rigorous approach to
system evaluation and development
Petri nets converted to SystemC models
Serve as faster lower level system simulation models
SystemC model provides simplified path to software evaluation for
prospective applications.
Operating System Support with uCLinuxTM
Standard development environment (GNU toolchain)
MPI (sort of)
Development Challenges and Issues
TMR of the reconfigurable logic (especially the Microblaze soft
core processor)
Caching architecture across the SLiP interface.
Development of a low latency, tiered cache structure for embedded
soft processors.
Fabrication with fine pitch CGA components (4VFX60)
May require microvias and blind vias
Availability of various technologies
Small form factor, high-efficiency DC voltage regulators
125/MAPLD'05
Currently still working some architectural formulation, but the
base structure is completed.
Reconfigurable nature of the prototype enables architecture trades
post hardware development.
Schematics complete and layout proceeding.
Hardware prototypes expected at the end of the fiscal year.
125/MAPLD'05
