Solid State Storage System for Solid State Storage System for the International Space Stationthe International Space Station

Jake BerlierJake BerlierDavid JacobDavid Jacob

Dr. Jerry TuckerDr. Jerry TuckerDr. James M. McCollumDr. James M. McCollum

OutlineOutline

IntroductionIntroduction

Orion ProjectOrion Project

Solid State Storage System OverviewSolid State Storage System Overview

Progress to DateProgress to Date

ConclusionConclusion

IntroductionIntroduction

Goal: Design and implement a solid state Goal: Design and implement a solid state storage system with data redundancy for storage system with data redundancy for space-applicationsspace-applications

Aerospace Innovations Inc. contract for Aerospace Innovations Inc. contract for NASANASA– Tom Johnson, Bob AkamineTom Johnson, Bob Akamine

Supporting Orion ProjectSupporting Orion Project

Constellation: Ares and Orion Constellation: Ares and Orion SpacecraftSpacecraft

Phase-out older space Shuttle Phase-out older space Shuttle and phase-in new Ares and and phase-in new Ares and Orion spacecraftOrion spacecraftThis project will be This project will be incorporated in a system that incorporated in a system that will capture telemetry and will capture telemetry and video datavideo data– Train “auto-docking” with Train “auto-docking” with

International Space StationInternational Space Station

Images from: http://www.nasa.gov/Atlantis Space Shuttle

Orion Crew Vehicle and Ares Launch Vehicle

RequirementsRequirements

Record data to Solid State drivesRecord data to Solid State drives– Write speed Write speed faster than Aurora faster than Aurora– Data redundancy and recoveryData redundancy and recovery

RAID 6 encoding and decodingRAID 6 encoding and decodingCRCCRC2 Drive recovery may be done on the ground2 Drive recovery may be done on the ground

2 different data sources2 different data sources– Must be able to switch so that the key data is Must be able to switch so that the key data is

collectedcollected

Radiation Hardening/ResistanceRadiation Hardening/ResistanceSolid State DrivesSolid State Drives

Secondary GoalsSecondary Goals

Reading from drivesReading from drives– Single error correctionSingle error correction– Double error correctionDouble error correction

Xilinx ML410 FPGA Selection and Xilinx ML410 FPGA Selection and Personality ModulePersonality Module

ML410 FPGA was ML410 FPGA was selected over newer selected over newer FPGAsFPGAs– Radiation resistance Radiation resistance

(latchup)(latchup)– FunctionalityFunctionality

Personality Module Personality Module – More SATA portsMore SATA ports– Development GPIODevelopment GPIO

Image from: www.xilinx.com

System OverviewSystem Overview

Aurora Aurora InterfaceInterface

SATA SATA ControllerController

PLB PLB ArchitectureArchitecture

Power PCPower PC

Aurora Command Interface

Aurora Data Interface

Aurora PHY

Aurora PHY

PLB

M

S

M

S

PPCS

Interrupt Controller

S

SATA

ControllerM

S

HD HD HD

DA

TA

RE

CO

RD

ER

Aurora InterfaceAurora Interface

Data RecorderData Recorder

Two data sourcesTwo data sources– Primary and secondaryPrimary and secondary– Aurora InterfaceAurora Interface

(outside scope of project)(outside scope of project)

Open IP Core (Free!)Open IP Core (Free!)– Differential signalingDifferential signaling– High speed (multiple Giga-High speed (multiple Giga-

bits)bits)

Command vs. DataCommand vs. Data– User Flow Control with User Flow Control with

embedded commandsembedded commands– Separation of Data from Separation of Data from

CommandCommand

Aurora InterfaceAurora Interface(outside scope of project)(outside scope of project)

Aurora Command Interface

Aurora Data Interface

Aurora PHY

Aurora PHY

M

S

M

S

Aurora InterfaceAurora Interface

SATA/RAID ControllerSATA/RAID Controller

PLB InterfacePLB Interface– MasterMaster– SlaveSlave

SATA IP Core/ SATA IP Core/ Supporting HDLSupporting HDL

Data BufferData Buffer

RAID 6 RAID 6 Encoding/ Encoding/ DecodingDecoding

Master FSM Slave Registers and Address Decoder

“Word Stripe” Buffer

RAID Encode/Decode

SATA IP Core

HD

SATA IP Core

HD

SATA IP Core

HD

SATA IP Core

HD

SATA IP Core

HD

SATA IP Core

HD

SATA IP Core

HD

SATA IP Core

HD

PLBSM

PLB ArchitecturePLB Architecture

Master ComponentsMaster Components– Burst-line SupportBurst-line Support

Slave ComponentsSlave Components– PPCPPC– Control/Status Control/Status

RegistersRegisters

InterruptsInterrupts

PLB

Interrupt Controller

S

Role of Power PC and ChipscopeRole of Power PC and Chipscope

Power PCPower PC– Top-Level ControlTop-Level Control– Debugging and DevelopmentDebugging and Development

Compile time vs. Build timeCompile time vs. Build time

ChipscopeChipscope– View status of signals during operationView status of signals during operation

Spring/Summer Development Spring/Summer Development TimelineTimeline

January February March April May June July

Software SATA

Controller

Working SATA PHY

RAID Planning

System Requirement

Analysis

RAID Simulation

Testing (Proof of Concept)

Aurora-SATA Interface

MGT Side-A

Single Drive SATA

Single Drive

Aurora System

Dual Drive

Aurora System

Six Drive

Aurora System

RAID 6 System

RAID 6 System with Secondary

Goals

SATA OverviewSATA Overview

Command Layer

Transport Layer

Link Layer

Physical Layer

Application Layer

Command Layer

Transport Layer

Link Layer

Physical Layer

Application Layer

HOST DEVICE

Physical Connection(SATA Port)

SATA TopologyApplication LayerApplication Layer

– High-level interface (Wishbone)High-level interface (Wishbone)– Control registers, etc…Control registers, etc…

Command LayerCommand Layer– FSM for parsing commandsFSM for parsing commands

Transport LayerTransport Layer– Frame Information Structure (FIS)Frame Information Structure (FIS)– BufferingBuffering– Error ReportingError Reporting– Flow ControlFlow Control

Link LayerLink Layer– ScramblerScrambler– 8b-10b encoding8b-10b encoding– CRCCRC– Communication PrimativesCommunication Primatives

Physical LayerPhysical Layer– Handles physical transmission of differential signalsHandles physical transmission of differential signals

ASICS WS SATA IP CoreASICS WS SATA IP Core

ProprietaryProprietaryImplements Application, Implements Application, Command, Transport, and Command, Transport, and Link layers (no PHY)Link layers (no PHY)Interface:Interface:– Application layer - Application layer -

WishboneWishbone– PHY connectionsPHY connections– External bufferExternal buffer

ASICS SATA Core

WB FSM

FIFO

PHY

HD

SATA Physical LayerSATA Physical Layer

XAPP 716XAPP 716SATA Host Controller (Linux SATA Host Controller (Linux over Ethernet)over Ethernet)– Implements a basic SATA physical layer using Implements a basic SATA physical layer using

the ASICS WS corethe ASICS WS core– Source code (minus the ASICS WS core) is Source code (minus the ASICS WS core) is

publicly available from Xilinxpublicly available from Xilinx– Physical layer uses MGTPhysical layer uses MGT

Multi-Gigabit Transceiver (MGT)Multi-Gigabit Transceiver (MGT)

High-speed serial data connectionsHigh-speed serial data connections

Functionality:Functionality:– 8b-10b encoding/decoding8b-10b encoding/decoding– ScramblingScrambling– PLL/clock synchronizationPLL/clock synchronization

DRP - threshold detection not automaticDRP - threshold detection not automatic

Side A vs. Side B of MGTSide A vs. Side B of MGT– Can accommodate two SATA connectionsCan accommodate two SATA connections

SATA – Software to Hardware SATA – Software to Hardware (Wishbone Interface)(Wishbone Interface)

Currently, SATA works with software control Currently, SATA works with software control from the Power PCfrom the Power PC– SlowSlow– Serial Writing/ReadingSerial Writing/Reading– Easier and faster for initial implementationEasier and faster for initial implementation

Move to hardware in stages:Move to hardware in stages:– Wishbone interfaceWishbone interface– Multiple Hard DrivesMultiple Hard Drives– RAIDRAID– Etc…Etc…

Current Stage of Development: PLB Current Stage of Development: PLB Master Burst to SATA in HardwareMaster Burst to SATA in Hardware

Master vs. SlaveMaster vs. Slave– Speed improvement through Master BurstSpeed improvement through Master Burst

Will enable throughput testing for read and Will enable throughput testing for read and writewrite– Data for single drive, estimate for multiple Data for single drive, estimate for multiple

drivesdrives

2-Drive System2-Drive System

Implementation for both sides of MGTImplementation for both sides of MGT– Currently, only one side is connectedCurrently, only one side is connected– ConstraintsConstraints

Control for multiple drives (drive-pairs)Control for multiple drives (drive-pairs)– FSMFSM

Management of critical resourcesManagement of critical resources– Digital Clock ManagersDigital Clock Managers– Better estimate of resource usageBetter estimate of resource usage

6-Drive System6-Drive System

Control for multiple drives (for entire Control for multiple drives (for entire system)system)– 6 data drives6 data drives– Word Stripe bufferWord Stripe buffer

Power consumption estimationPower consumption estimation

Throughput testingThroughput testing– Maximum speed of systemMaximum speed of system

8-Drive System with RAID8-Drive System with RAID

Raid encoding/decodingRaid encoding/decoding

Working system!Working system!– Primary goal is writingPrimary goal is writing

Speed criticalSpeed critical

– Secondary goals:Secondary goals:Read with single error correction on the flyRead with single error correction on the fly

Read with double error correction using CRCRead with double error correction using CRC

Higher speed is more desirableHigher speed is more desirable

RAID OverviewRAID Overview

Encoding on the flyEncoding on the fly

Single Error Correction for reads (on the Single Error Correction for reads (on the fly)fly)

Double Error Correction for reads (on Double Error Correction for reads (on Ground or during mission)Ground or during mission)

Other Project MilestonesOther Project Milestones

Solid State Drive TestingSolid State Drive Testing

Radiation TestingRadiation Testing

ConclusionConclusion

Reconfigurable DesignReconfigurable Design– Plan for requirementsPlan for requirements– Debugging and incremental development with Debugging and incremental development with

Power PC and ChipscopePower PC and Chipscope

Working system delivered by the end of Working system delivered by the end of JuneJune

Questions?Questions?