SOI thermal impedance extraction methodology and its significance for circuit simulation

730 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 4, APRIL 2001

SOI Thermal Impedance Extraction Methodologyand Its Significance for Circuit SimulationWei Jin, Member, IEEE, Weidong Liu, Member, IEEE, Samuel K. H. Fung, Member, IEEE,

Philip C. H. Chan, Senior Member, IEEE, and Chenming Hu, Fellow, IEEE

Abstract—The buried-oxide in SOI MOSFET inhibits heat dis-sipation in the Si film and leads to increase in transistor temper-ature. This paper reports a simple and accurate characterizationmethod for the self-heating effect (SHE) in SOI MOSFET. The acoutput conductance at a chosen bias point is measured at severalfrequencies to determine the thermal resistance ( ) and thermalcapacitance ( ) associated with the SOI device. This method-ology is important to remove the misleadingly large self-heatingeffect from the dc – data in device modeling. Not correcting forSHE may lead to significant error in circuit simulation. After SHEis accounted for, the frequency-dependent SHE may be disabled incircuit simulation without sacrificing the accuracy, thus providingfaster circuit simulation for high-frequency circuits.

Index Terms—Self-heating effect (SHE), SOI MOSFET, thermalimpedance.

I. INTRODUCTION

DEEP submicron CMOS on SOI is becoming a mainstreamtechnology, which offers up to 20–35% performance gain

over a comparable bulk technology [1]. SOI MOSFET exhibitshigh transconductance and low junction capacitance due to thepresence of buried-oxide. However, the thick buried-oxide un-derneath the Si film gives rise to the self-heating effect (SHE).In extreme case, SHE results in a negative output conductanceduring dc – measurement. In general, SHE causes significantreduction in drain current. This is because the carrier mobilityand saturation velocity decrease as a result of the increase in de-vice temperature. It must be pointed out that SHE is significantonly in the dc characteristics when the device power dissipation( ) is high. The dynamic operation of low-power circuits,however, is essentially not affected by SHE, because most of thecircuits operate well above the SHE corner frequency. There-fore, it is essential to extract the SHE parameters and subtractthem from the SOI MOSFET characteristics for accurate circuitmodeling.

A complete SOI device model consists of a SHE-free com-pact model plus a model for SHE-induced temperature rise. TheSHE is modeled by an equivalent circuit [2] as shown in

Manuscript received January 12, 2000; revised August 14, 2000. This workwas supported by RGC Earmarked Grant HKUST 6025/97E and NSF underContract ECS-9634217. The review of this paper was arranged by Editor C.-Y.Lu.

W. Jin and P. C. H. Chan are with the Department of Electrical and ElectronicEngineering, Hong Kong University of Science and Technology, Clear WaterBay, Hong Kong.

W. Liu and C. Hu are with the Department of Electrical Engineering andComputer Sciences, University of California, Berkeley, CA 94720 USA.

S. K. H. Fung is with IBM Microelectronics, Hopewell Junction, NY 12533USA.

Publisher Item Identifier S 0018-9383(01)02352-8.

Fig. 1. Model for self-heating effect in SOI MOSFET. AC self-heating issuppressed at high frequency.

Fig. 1. In SPICE, self-heating is implemented by introducingan internal temperature node to the device. This node is con-nected to ground through the and network and the nodal“voltage” is actually the device temperature. SPICE engine willperform the Newton–Raphson iterations until the convergencecriteria are satisfied for both the physical nodes and the temper-ature node of the device. Although an analytical model ofis provided by [3], in fact strongly depends on technologyand therefore needs to be characterized experimentally for eachtechnology. Complex ac [4] and pulse [5] techniques have beenproposed for obtaining SHE-free– data. In this work, wewill use the ac output conductance () data at a chosen biaspoint to characterize both and . With and de-termined, the SHE is subtracted from the dc data and SHE-free– data are obtained. Based on the SHE-free data, accurate de-

vice model parameters can be extracted. In Section II, we applyMEDICI [6] simulation to illustrate SHE in . The ac outputconductance measurement technique is described in Section III.Section IV discusses the extraction methodology for and

of SOI devices. Section V presents the experimental dataand circuit simulation results using the BSIMSOI model.

II. I LLUSTRATION OF SELF-HEATING THROUGHSIMULATION

For SOI MOSFET, the increase in dc device temperature, orthe so-called lattice temperature, is determined by the thermalresistance and power consumption [7]

(1)

where and are the lattice temperature and ambient tem-perature, respectively. The increasedin the SOI film reducesthe mobility and saturation velocity of the carriers, leading to alower . SHE is the most severe at high and . Fig. 2shows the MEDICI simulation results of– characteristicsand ac output conductance () for a fully depleted (FD) SOIMOSFET. A small negative dc differential drain conductance

0018–9383/01$10.00 © 2001 IEEE

JIN et al.: SOI THERMAL IMPEDANCE EXTRACTION METHODOLOGY 731

Fig. 2. MEDICI simulation results for an FD SOI MOSFET. AC drainconductance changes sign at high frequency due to the suppression of SHE.TheI–V characteristics is shown in the inset.

is observed as shown in the inset when the self-heating is in-cluded in MEDICI simulation. When self-heating is turned off,a large positive is observed in the inset. The difference be-tween the two cases contains the desired information regarding

. Experimentally, one cannot turn on or turn off self-heatingat will. However, one can still obtain the same information bymeasuring the frequency response of as shown below. Theincrease of ac lattice temperature as modeled in Fig. 1 is givenby

(2)

where is the thermal time constant, and the SHE character-istic frequency . At low frequency, varies instep with the ac signal, therefore remains at its dc value, i.e.,a small negative value as shown by the main curve in Fig. 2. Inthis paper, refers to the real part of , the drain admittance.As frequency increases, gradually ceases to respond to thesignal so that ac SHE is suppressed, andstarts to increase.What remains at high frequency is the intrinsic, which is al-ways positive and its value is determined by the channel lengthmodulation (CLM), drain-induced barrier lowering (DIBL) ef-fects, etc. Fig. 2 also indicates that when SHE is turned on,athigh frequency (ac SHE-free) is smaller than that when SHE isturned off. This is because dc SHE causes a difference in the qui-escent temperatures in the two cases. When SHE is turned on,the quiescent temperature (device temperature) is higher thanthe ambient temperature. Although ac SHE is suppressed at highfrequency, the dc SHE is still present and it reducesas com-pared with the case where SHE is turned off.

Fig. 3. Measurement setup for self-heating characterization.

III. CHARACTERIZATION OF AC DRAIN CONDUCTANCE

Fig. 3 shows the measurement setup for the SHE characteri-zation. To measure the ac drain output conductance, HP4194AImpedance Analyzer applies the dc bias and ac small-signalacross the drain and source terminals of the device. Gate andsubstrate biases are supplied by HP4156B Semiconductor Pa-rameter Analyzer. The HP4156B also simultaneously monitorsthe drain bias. The experimental data of the drain admittancefor an FD SOI device are shown in Fig. 4(a) and Fig. 4(b).The phase is 180at low frequency, indicating a negative .When frequency increases beyond, the phase crosses 90and eventually becomes zero. This meansbecomes positiveas frequency increases, because ac self-heating is suppressed.Fig. 4(b) shows the real and imaginary parts of. Similar tothe MEDICI simulation result, the transition of from nega-tive to positive value occurs between 100 kHz and 1 MHz. Thiscorresponds to a in the order of microsecond. Interestingly,around 300 kHz, the real part of becomes zero and the tran-sistor behaves as a pure capacitor. Hence, for a single frequencyapplication, a huge on-chip capacitor (around 1 pF/m ) withhigh-Q (quality factor) and small area can be synthesized withan SOI MOSFET.

At a smaller drain bias in the saturation region, SHE may beoverwhelmed by CLM and DIBL effects, so that is posi-tive even at low frequency and dc. For example, in Fig. 5, at

V and V, is positive for the entire fre-quency range even though the same device exhibits negativein Fig. 4(b). The sign of is unimportant. It will be shown thatit is , the difference of between high- and low-fre-quency asymptote that will yield the value.

The experimental data for a partially depleted (PD) SOI de-vice is shown in Fig. 6. Since the floating-body effect (FBE) ismore serious in PD SOI than in FD SOI, the current increase dueto FBE normally overwhelms the decrease due to SHE even athigh . Therefore, negative is not observed in PD SOIdevices. In Fig. 6, the decrease of at 10 –10 Hz is dueto the suppression of FBE [8], while the increase of at 1MHz results from the suppression of SHE. It is worthwhile tonote that the characteristic frequencies associated with FBE arebias-dependent, whereas the SHE characteristic frequency ()is bias-independent. This is an evidence that the latter does havea nonelectricalorigin.


(a)

(b)

Fig. 4. (a) Measured magnitude and phase of the drain admittance for an FDSOI MOSFET biased in the negative dcg region. (b) Measured real andimaginary parts of the drain output admittance for an FD SOI MOSFET biasedin the negative dcg region.

Fig. 5. Measured output conductance of an FD device under smaller drain bias,whereg is positive.

IV. DETERMINATION OF AND

To relate and to the versus frequency plot, isdecomposed, as shown in Fig. 7. The total acconsists of the

Fig. 6. Measured output conductance of a PD device. Note the bias-dependentf and the bias-independentf .

Fig. 7. Interpretation of the output conductance of a PD device. Theconductance consists of the contributions from the intrinsic channel, FBE, andSHE. The difference ofg between Point B and Point C is due to SHE.

intrinsic conductance due to CLM and DIBL effects, etc., plusthe conductance due to FBE and SHE:

(3)

At low frequency (Point A), both FBE and SHE are present.As frequency increase beyond the FBE characteristic frequencysuch as at Point B, the effect of ac FBE on is negligible. Atthe high-frequency end of the measurement (Point C), ac SHEis suppressed. Thus, at Point C is a good approximation tothe intrinsic conductance. Fig. 7 suggests that the difference of

between Point B and C is , the contribution of SHE.The same analysis is applicable to FD devices, irrespective ofthe sign of . can be expressed as

(4)

, the slope of versus temperature, can be deter-mined from the hot-chuck measurement as shown in Fig. 8. The


Fig. 8. Hot-chuck measurement results are used to determinedI=dT .

second term on the RHS of (4) can be derived from (1) as fol-lows:

(5)

(6)

Taking in the saturation region where SHE occurs, (6)is simplfied as

(7)

Therefore,

(8)

Substituting (8) into (4), we have

(9a)

If the term is not negligible in (6), it can be shown that

(9b)

where is the at Point B in Fig. 7. In either case,

(10)

Since it is difficult to precisely determine from the acdata, is extracted by fitting the ac data. Empericallyis the frequency where in Fig. 7.

Fig. 9 shows the thermal time constant and the extractedas a function of channel width. Note that is independentof channel widths, and it is nearly constant for different SOIfilm thickness (PD and FD). This is because and haveinverse dependencies on and . has been modeled as[2]

(11)

Fig. 9. Extracted thermal time constant (� ) and normalized thermalresistance (R W ) vs. channel width.� is basically constant whileR Wis smaller for narrow-channel device due to spreading thermal resistance.

Fig. 10. DAVINCI 3-D simulation results of 1/R for an SOI MOSFET.

wherechannel width;

and thickness of the buried-oxide and SOI film,respectively;

and thermal conductivity of SiOand Si, respec-tively.

This model predicts that scales linearly with , i.e., thenormalized thermal resistance is constant forall channel widths. However, due to the spreading thermal re-sistance nature of the device [9], narrow-width device exhibitssmaller , as shown in Fig. 9. This is further validated byDAVINCI 3-D [10] simulations. Fig. 10 shows that 1/ ex-hibits a linear dependence on for large . As decreases,1/ asymptotically tends to a finite number.

V. VERIFICATION OF SHE CHARACTERIZATION AND

DISCUSSION

Fig. 11 shows the procedure for extracting BSIMSOI [2]model parameters. and are determined to removeSHE from the raw – data before the extraction of the basicmodel parameters and other SOI-specific parameters. With theparameters so extracted, simulation provides an excellent fit tothe measured– characteristics for FD and PD devices, asshown in Figs. 12 and 13, respectively. Since the simulationresults based on the extracted agree with the raw –


Fig. 11. Flow chart of BSIMSOI model parameters extraction.

Fig. 12. R extracted in this work enables an excellentI–V fitting usingBSIMSOI model. More importantly, SHE-free (R = 0) I–V can be deducedfrom the measuredI–V for simple BSIMSOI model parameter extraction.

data, the SHE-free– data can be obtained from simulationby setting . Not correcting for SHE may lead to 20%underestimation of the real (SHE-free) drain current at high

and in high-frequency circuits.Fig. 14 shows that BSIMSOI simulation results also agree

well with the ac data of the FD and PD devices based onthe extracted and . This is important for the accuratesimulation of SOI analog circuits over a wide frequency range.Fig. 15 shows the measured ac data and simulation results ofa FD device as a function of drain bias for several frequencies.At low frequency and high , is negative due to SHE. Asfrequency increases, negative is less likely to appear becauseac SHE is suppressed.

We emphasize that this technique provides a way to recoverthe SHE-free – curves (see Figs. 12 and 13) that are im-portant for modeling transistor characteristics in low-power cir-cuits. For digital circuits, the quiescent average power dissipa-tion is very low and the signal frequency is much higher than

, therefore both dc and ac SHE are negligible. Fig. 16 shows

Fig. 13. Drain characteristics of a PD device. Not correcting for SHE wouldlead to 20% underestimation ofI in low-power circuits.

Fig. 14. Based on the extractedR andC , BSIMSOI simulation resultsagree well with the measured acg data for the FD and PD devices.

Fig. 15. BSIMSOI simulation results agree well with the measured acg asa function ofV for an FD SOI MOSFET.

BSIMSOI simulation results of a 51-stage PD SOI ring-oscil-lator (RO) with m. SHE is negligible, as the opera-tion frequency is around 0.5 GHz, well above. Two observa-tions from the figure are significant for SOI modeling and circuit


Fig. 16. BSIMSOI simulation results of a 51-stage ring oscillator.

TABLE IBSIMSOI SIMULATION TIME FOR A 51-STATE SOI RING-OSCILLATOR

simulation. First, if, perhaps for simplicity, SHE is ignored in thedevice model parameter extraction (as if one were unaware ofSHE in SOI, and the model parameters are obtained by simplyfitting the measured data with minimum RMS error), simula-tion (dash-dot lines) will overestimate the gate delay of RO by

15%. This is because the real drain current in the high-fre-quency circuit, which is SHE-free, is underestimated by the dccurrent not corrected for SHE. Second, as long as SHE is con-sidered (corrected) in model parameter extraction, simulationaccuracy is hardly affected whether the thermal model shown inFig. 1 is used in circuit simulation or not. However, the simula-tion time is reduced by 15% if the self-heating model is turnedoff, as shown in Table I. This suggests that for most of digitalcircuits simulations, once SHE-free model parameters are ob-tained using the extracted and , the SHE model can bedisabled. The simulation-efficiency improvement is expected tobe even more significant for larger circuits.

VI. CONCLUSION

An accurate and simple characterization method for the self-heating effect in SOI MOSFET is reported. Drain output con-ductance data at a selected bias point and several frequencies areused to extract and . The technique is verified with mea-sured data. With and known, the important SHE-freemodel parameters can be easily deduced. This greatly simplifiesthe extraction of SOI compact model parameters. For low-powerdigital circuit simulation, as long as heating-free device charac-teristics (model parameters) is employed, SHE model may usu-ally be turned off to improve simulation efficiency.

ACKNOWLEDGMENT

The authors would like to acknowledge the valuable discus-sions with P. Su and M. K. Y. Cao, both with the Departmentof Electrical Engineering and Computer Sciences, University ofCalifornia, Berkeley.

REFERENCES

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[8] S. K. H. Fung, M. K. Wong, M. Chan, C. T. Nguyen, and P. K. Ko,“Frequency dispersion in partially depleted SOI MOSFET output resis-tance,” inIEEE Int. SOI Conf. Proc., 1996, pp. 146–147.

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Wei Jin (M’00) received the B.S. degree in electrical engineering from ZhejiangUniversity, China, in 1992, the M.S. degree in biomedical engineering from theUniversity of Science and Technology of China in 1995, and the Ph.D. degree inelectrical and electronic engineering from the Hong Kong University of Scienceand Technology in 2000. His Ph.D. dissertation was on the modeling of SOItransistors for low-power and low-noise applications. During his Ph.D. study,he was also involved in BSIMPD development at the University of California,Berkeley.

In April 2000, he joined Motorola, Inc., Austin, TX, where he has beenworking on high-performance SOI modeling and characterization.

Weidong Liu (M’97) received the B.S. degree in applied physics and the M.S.degree in electrical engineering from Hefei Polytechnic University, China, in1988 and 1991, respectively, and the Ph.D. degree in electronics and electricalengineering from Southeast University, China, in 1994.

From 1994 to 1996, he was a Postdoctoral Research Engineer at Instituteof Microelectronics, Tsinghua University, China, working on the sub-0.1–mi-cron bulk/SOI CMOS process, and device design and characterization. In 1996,he joined Electronics Research Lab, University of California, Berkeley, as aPostdoctoral Research Engineer, where he has been a Research Engineer since2000. Since 1996, he has been working with Professor C. Hu and his group asa major developer of the BSIM3v3 and BSIM4 MOSFET models for circuitsimulation, and providing technical support of the BSIM models for industryand research community worldwide. He has since worked as a Coordinator be-tween the Compact Model Council and the BSIM Group for better use and de-velopment of BSIM as the industry standard model. He has also been activelyinvolved in the development of Berkeley’s SOI models. He has authored andcoauthored 50 research papers and one book chapter. His research interests in-clude bulk/SOI MOSFET design and characterization, hot-carrier effects andreliability, and semiconductor device SPICE modeling.


Samuel K. H. Fung(S’95) received the B.Eng. degree in electrical engineeringfrom the University of Hong Kong in 1992, and the M.Phil. and Ph.D degreesin electrical engineering from the Hong Kong University of Science and Tech-nology in 1994 and 1997, respectively. The subject of his master’s thesis wason thin-film SOI device physics and fabrication. During his Ph.D study, he wasinvolved in the development of BSIM3SOI for thin-film SOI MOSFET circuitsimulation, in collaboration with the University of California, Berkeley. Themodel has emerged as BSIMPD later and becomes the most popular partiallydepleted SOI model in the industry.

In 1998, he joined IBM Microelectronics, Hopewell Junction, NY. Currently,he is involved in the device development for high-performance 0.10-�m SOICMOS in IBM. He has authored or coauthored over 30 research papers.

Dr. Fung is a recipient of the Schmidt Award of Excellence.

Philip C. H. Chan (SM’95) received the B.S. degreein electrical engineering from the University of Cali-fornia, Davis (with highest honors and department ci-tation), and the M.S. and Ph.D. degrees in electricalengineering from the University of Illinois at Urbana-Champaign (UIUC), under Prof. C. T. Sah.

After graduation, he remained at UIUC as an IBMPostdoctoral fellow and later as a Visiting AssistantProfessor in electrical engineering. Her engagedin semiconductor device and material research andtaught undergraduate and postgraduate courses in

semiconductor devices. In 1981, he joined Intel Corporation, Santa Clara,CA, as a Senior Engineer in the Technology Development Computer-AidedDesign Department. He later became Principal Engineer and Senior ProjectManager and had the corporate responsibility for circuit simulation tools,VLSI device modeling, and process characterization. In 1990, he transferredto the Design Technology Department of the Microproducts Group, where heled a team of engineers that defined and developed a CAD system to designmultichip module products, an effort which led to the first functional 486-basedmultichip module at Intel. In 1991, he joined the Hong Kong University ofScience and Technology as a Reader, and became Professor in 1997. He servedas the Director of the Computer Engineering Program, the Associate Dean ofEngineering, and Acting Head and then Head of the Department of Electricaland Electronic Engineering. His research interests include microelectronicsdevices, circuits and systems, and integrated sensors and electronic packaging.He is the co-owner of one U.S. patent.

Chenming Hu (S’71-M’76-SM’83-F’90) receivedthe B.S. degree from the National Taiwan University,Taipei, Taiwan, R.O.C., in 1968, and the M.S.and Ph.D. degrees in electrical engineering fromUniversity of California, Berkeley, in 1970 and1973, respectively.

He is Chancellor’s Professor of Electrical En-gineering and Computer Sciences at University ofCalifornia, Berkeley. From 1973 to 1976, he was anAssistant Professor at the Massachusetts Institute ofTechnology, Cambridge. Since 1976, he has been a

Professor of Electrical Engineering and Computer Sciences at the Universityof California, Berkeley. While on industrial leave from the university in 1980and 1981, he was Manager of nonvolatile memory development at NationalSemiconductor. He has served as an advisor to many industry, government,and educational institutions. His present research areas include VLSI devices,silicon-on-insulator devices, hot electron effects, thin dielectrics, electromigra-tion, circuit reliability simulation, and nonvolatile semiconductor memories.He has been awarded several patents on semiconductor devices and technology.He has authored or coauthored four books and over 600 research papers andsupervised 60 doctoral students.

Dr. Hu has delivered dozens of keynote addresses and invited papers at sci-entific conferences and has received several best paper awards. In 1997, he waselected a member of the National Academy of Engineering and received theBerkeley Distinguished Teaching Award. He is an Honorary Professor of Bei-jing University, Beijing, China, and of the Chinese Academy of Science. He re-ceived the 1991 Grand Prize of Excellence in Design Award from Design Newsand the first Semiconductor Research Corporation Technical Excellence Awardin 1991 for leading the development of IC reliability simulator, BERT. He re-ceived the SRC Outstanding Inventor Award in 1993 and 1994. He co-developedthe MOSFET model BSIM3v3, chosen as the first industry standard model forIC simulation in 1995, and given an R&D 100 Award as one of the 100 mosttechnologically significant new products of the year in 1996. The Board of Di-rectors of the IEEE awarded him the 1997 Jack A. Morton Award for his pio-neering contributions to MOSFET reliability physics and modeling. In 1998, hereceived the Monie A. Ferst Award of Sigma Xi for encouragement of researchthrough education. He received the Pan Wen Yuan Foundation Award for out-standing research in electronics in 1999.

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SOI thermal impedance extraction methodology and its significance for circuit simulation