Software Lab-IV BTEC 606 Lab Manual

8/15/2019 Software Lab-IV BTEC 606 Lab Manual

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Oriental University, Indore Department of E & C

Software Lab-IV Lab Manual VHDL

CONTENTS

S.NO. NAME OF THE EXPERIMENT DATE OFSUBMISSION

REMARKS

1.

2.

3.

4.

5.

6.

7.

8.

9.

10.


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FPGA DESIGN FLOW

Programmable Logic Design Flow

Gate level Model

Libraries (Simprims

and

Unisims

Design Specifications

Design Entry

RTL Model

Functional

Simulation

(Zero Delay)

TE

S

T

B

E N

C

H

SynthesisGate level

description usingtarget library cells

Gate level

Simulation

Mapping +

Translation

Gate level model todevice architecture

Place and Route

Placing the design indevice while optimizing

it for speed and area

Programming file

generation

Bit Stream

Download onto

FPGA/ CPLD

Timing

Simulation

(Gate +Interconnect

Delays)

Target Device

Libraries (Vender

Specific)

Design Constraints

Area / Speed

Target Device

Libraries (VenderSpecific)

Design Constraints

Area / Speed


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FPGA Design Flow for XilinxThe Design flow followed by Xilinx devices is as shown as under:

Xilinx FPGAs are reprogrammable and when combined with an HDL design

flow can greatly reduce the design and verification cycle.


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Broadly the stages can be categorized as:

1. Design Entry may have two alternatives:

a) Performing HDL coding for synthesis as the target.( Xilinx HDL Editor). b) Using Cores(Xilinx Core Generator).

2. Functional Simulation of synthesizable HDL code (MTI ModelSim).

3. Design Synthesis ( Xilinx project navigator).4. Design Implementation (Xilinx Design Manager).

The stages are linked as follows:

Design EntryThe first stage of Xilinx design flow is a design entry process. A design must be

specified by using either a schematic editor or HDL text-based tool.

Functional Simulation Upon the finish of the design entry stage, the functional simulation of the design

is being performed, which is used to verify functionality of the design assuming no

delays, whatsoever. This assumes no target technology selection at this stage and henceassumes zero delay in simulation.

Complex designs must be intensively simulated, at different simulation points,

during the design flow. Simulation verifies the operation of the design before it is

Timing Simulation

Program onto FPGA

VERILOG HDL/VHDL

Code Design Entry

Functional Simulation

Synthesis

Post Synthesis Simulation

Implementation


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actually implemented as hardware. One of the most prevalent methods for simulation is

testbenching. Testbenches (VERILOG HDL) or text fixtures (Verilog) are used to specify

circuit stimuli and responses.Roughly, simulation can be divided as functional and timing simulation. Primarily, the

functional simulation verifies that the design‟s specifications are correctly understood and

coded. Timing information, produced during the device implementation stage, is notavailable during the functional simulation. Functional simulation can be used aftersynthesis, too.

Comparison between the pre- and post-synthesis simulations‟ results checks the results of

the HDL compiler‟s work and the HDL code‟s correctness. Timing simulation operates with the real delays (results of device implementation) and is

used for verification of implemented design. Timing data are given in an .sdf file

(Standard Delay Format).

Xilinx supports functional and timing simulations at different points of the design flow: Register Transfer Level (RTL) simulation. Post-synthesis functional simulation (Pre-NGDBuild).

Post-implementation back-annotated timing simulation.

Design SynthesisAfter this process, the synthesis is performed. Here for the first time in the design

flow the target technology (choice of a particular FPGA device family) is being

performed. This target technology selection will remain the same, henceforth in the

design flow, upto the final implementation stage, where finally generated Bit stream filegets downloaded onto that FPGA.

The output of the synthesis process is creation of gate level netlist. This refers to

the EDIF implementation netlist of the FPGA design. Besides the EDIF implementation

netlist, the XNF (Xilinx netlist format) netlist can be used as well.

Although the XNF is now becoming rather obsolete. The EDIF netlist is used asan input file to the Xilinx Implementation tool and specifies how the core will be

implemented.The Electronic Design Interchange Format (EDIF) is a format used to exchange design

data between different CAD systems. In the world of FPGA design, it is used for

interchange of data between different EDA (Electronic Design Automation) software

tools. EDIF files are used for FPGA implementation only. They are the result of designsynthesis and can be generated from different design entry EDA tools: schematic or HDL

design tools. EDIF files are inputs to the Xilinx implementation tools during the

translation step (NGDBuild).

Design ImplementationDesign Implementation includes the following steps:i) Translate

ii) Map

iii) Place and Route

In the Translate step, which is the first step in the implementation process, EDIF

netlist must be further converted into Native Generic Database file (NGD), by means of a


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program called NGDBuild. The NGD file resulting from an NGDBuild run contains the

logical description of the design that can be mapped into a targeted Xilinx FPGA device

family. It is important to stress that NGDBuild merges all available EDIF netlists fromthe working directory. This is actually the step where the black-box netlist becomes

merged with the rest of FPGA design.

In the next stage, the Map stage, the NGD file is an input into a MAP programthat maps logical design to a Xilinx FPGA. The output of the MAP program is an NCD(Native Circuit Description) file. The NCD is a physical representation of the design

mapped to the components of internal FPGA architecture.

The mapped design is ready to be placed and routed. The PAR program does this job. The input to PAR is a mapped (not routed) NCD file, while the output is a fully

routed NCD file.

Review reports are generated by the Implement Design process, such as the MapReport or Place & Route Report, and change any of the following to improve your

design:

Process properties Constraints Source files

Synthesis and again implementation of the design is being made until design

requirements are met.Timing verification of the design can be made at different points in the design

flow as follows:

i) Run static timing analysis at the following points in the design flow: After Map. After Place and Route.

ii) Running Timing Simulations at the following points in the design flow: After Map (for a partial timing analysis of CLB and IOB delays). After Place and Route (for full timing analysis of block and net

delays).

Program onto FPGAProgramming on the Xilinx device can be made as follows:

Creation of a programming file (BIT) to program FPGA. Generate a PROM, ACE, JTAG file for debugging or to download to

the device. Use iMPACT to program the device through programming cable.

Xilinx FPGA, as an SRAM-based programmable PLD, must be configured with

the configuration bitstream. The configuration bitstream is generated from the fullyrouted NCD file, by means of a BitGen program. The output of BitGen is a binary file

with the .BIT extension that can be formatted for different PROM devices.


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EXPERIEMENT NO. 1

Simulation using all the modeling styles and Synthesis of all the

logic gates using VHDL

AIM:Perform Zero Delay Simulation of all the logic gates

written in behavioral, dataflow and structural modeling style in VHDL using a

Test bench. Then, Synthesize each one of them on two different EDA tools.

Electronics Design Automation Tools used:i) FPGA Advantage 3.1 (includes Model Sim simulation tool and Leonardo

Spectrum Synthesis Tool)

ii) Xilinx Project Navigator 8.1 (Includes all the steps in the design flow from

Simulation to Implementation to download onto FPGA).

Block Diagram:

Truth table:

And Gate: Or Gate:

A B Y

0 0 0

0 1 1

1 0 1

1 1 1

Nand Gate: Nor Gate:

A B Y

0 0 1

0 1 0

1 0 0

1 1 0

And, Nand,

Or, Nor,

Xor, Xnor

A

B

C

A B Y

0 0 0

0 1 0

1 0 0

1 1 1

A B Y

0 0 1

0 1 1

1 0 1

1 1 0


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Xor Gate: Xnor Gate:

A B Y

0 0 1

0 1 0

1 0 01 1 1

Boolean Equation:

And Gate: Y = (A.B) Or Gate: Y = (A + B) Nand Gate: Y = (A.B)‟ Nor Gate: Y = (A+B)‟

Xor Gate: Y = A.B‟ + A‟.B Xnor Gate: Y = A.B + A‟.B‟

VHDL Code (In different modeling styles):

And Gate (In Dataflow, behavioral Modeling):

library ieee;use ieee.std_logic_1164.all;

entity andg is port (a,b : in std_logic;

c : out std_logic);

end andg;

architecture andg_df of andg is -- simple dataflow modeling

beginc


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end org;

architecture org_df of org is -- dataflow modeling using when …. else begin

c


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process(a,b)variable v : std_logic_vector(1 downto 0);

beginv := a & b;case v is

when "00" => c c c c c


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Xor gate(Dataflow, behavioral modeling):


entity xorg is

port (a,b : in std_logic;c : out std_logic

);end xorg;

architecture xorg_df of xorg is -- simple dataflow modeling begin

c


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architecture Xnorg_df of Xnorg is -- dataflow modeling using with …… select signal sel : std_logic_vector(1 downto 0);

beginsel b_i,c => c_i

);


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process begin

a_i


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EXPERIEMENT NO. 2

Simulation using all the modeling styles and Synthesis of 1-bit half

adder and 1-bit Full adder using VHDL

AIM:Perform Zero Delay Simulation of 1-bit half adder and 1-bit Full adder written in behavioral, dataflow and structural modeling style in VHDL using a Test bench. Then,

Synthesize each one of them on two different EDA tools.





Block Diagram:

1-bit Half Adder:

1-bit Full Adder:

Truth table:Half Adder:A B Sum Carry

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Half Adder

(1-bit)

A

B

Sum

Carry

Full Adder

(1-bit)

Sum

Cout

A

B

Cin


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Full Adder:

A B Cin Sum Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 00 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Boolean Equation:

Half Adder: Sum = A B

Carry = A.B

Full Adder:Sum = A B Cin

Cout = A.B + A.Cin + B.Cin

VHDL Code:

Half Adder (Using dataflow, Behavioral Modeling):

library ieee;

use ieee.std_logic_1164.all;

entity ha_1b is port ( a, b : in std_logic;

sum, carry : out std_logic);

end ha_1b;

architecture ha_1b_df of ha_1b is -- dataflow modeling using with selectsignal s : std_logic_vector(1 downto 0);

begin

s


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'0' when "10",'1' when "11",

'0' when others;end ha_1b_df;

architecture ha_1b_df1 of ha_1b is -- simple dataflow modeling using Boolean equation

beginsum


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variable v : std_logic_vector(2 downto 0); begin

v := a & b & cin;case v is

when "000" =>sum


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b => b ,sum => s1 ,

carry => s2);

ha_1b_i2 : ha_1b port map ( a => s1 ,

b => cin ,sum => sum ,carry => s3

);

Org_i : org port map ( a => s3,

b => s2,c => cout

);end fa_1b_str;

architecture fa_1b_mixed of fa_1b is

component ha_1b port (a,b : in std_logic;

sum, carry: out std_logic

);end component;

signal s1,s2,s3 : std_logic;

begin

ha_1b_i : ha_1b port map ( a => a , --structural modeling b => b ,

sum => s1 ,

carry => s2);

process (s1,cin) -- behavioral modeling

beginsum


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end ha_1b_tst;

architecture ha_1b_tst_a of ha_1b_tst iscomponent ha_1b

port (a, b : in std_logic;sum, carry : out std_logic

);end component;

signal a_i ,b_i, sum_i,carry_i : std_logic; beginnandg_i : ha_1b port map ( a => a_i,

b => b_i,sum => sum_i,

carry => carry_i);

process begin

a_i


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begin

fa_1b_i : fa_1b port map ( a => a_i, b => b_i,

cin => cin_i,sum => sum_i,

cout => carry_i);

process begin

a_i


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Full Adder:

Synthesis:

Half Adder:

EDA Tool Name: Fpga Advantage 3.1 – Leonardo spectrum

EDA Tool Name: Xilinx Project Navigator – 8.1

Full Adder:



Synthesis Report (Xilinx Project Navigator):

Full Adder:


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EXPERIEMENT NO. 3

Simulation using all the modeling styles and Synthesis of 2:1

Multiplexer and 4:1 Multiplexer using VHDL

Aim:Perform Zero Delay Simulation of 2:1 Multiplexer and 4:1 Multiplexer written in behavioral, dataflow and structural modeling style in VHDL using a Test bench. Then,

Synthesize each one of them on two different EDA tools.





Block Diagram:

2:1 Multiplexer:

4:1 Multiplexer:

2:1

Multiplexer

A

BY

S

Y4:1

Multiplexer

A

B

C

D

S1 S0


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Truth table:

2:1 Multiplexer:

S A B Y

0 0 0 00 0 1 0

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 0

1 1 1 1

4:1 Multiplexer:

A B Y0 0 A

0 1 B

1 0 C

1 1 D

Boolean Equation:2:1 Multiplexer:

Y = A.S‟ + B.S 4:1 Multiplexer:Y = A.S1‟.S0‟ + B.S1‟.S0 + C.S1.S0‟ + D.S1.S0

VHDL Code:

2:1 Multiplexer ( in dataflow and behavioral modeling style) :

library ieee;


entity mux21 is

port ( a,b,s : in std_logic;

y : out std_logic);

end mux21;

architecture mux21_df of mux21 is -- simple dataflow modeling using Booleanequation


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begin

y y

y y


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y


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architecture mux41_str of mux41 is

component mux21

port ( a,b,s : in std_logic;y : out std_logic

);

end component;signal con1, con2 : std_logic; begin

mux21_i1 : mux21 port map ( a => a , b => b ,

s => s1 ,

y => con1

);

mux21_i2 : mux21 port map ( a => c ,

b => d ,s => s1 ,

y => con2

);

mux21_i3 : mux21 port map ( a => con1 ,

b => con2 ,

s => s0 ,y => y

);

end mux41_str;

VHDL Test Bench:

2:1 Multiplexer:

library ieee;


entity mux21_tst is

end mux21_tst;

architecture mux21_tst_a of mux21_tst iscomponent mux21

port (a,b,s : in std_logic;

y : out std_logic);

End component;

signal a,b,s,y : std_logic; begin

mux21_i : mux21 port map ( a => a,


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b => b,

s => s,

y => y);

process

begina


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EXPERIEMENT NO. 4

Simulation and Synthesis of 1:4 Demultiplexer using VHDL

Aim:Perform Zero Delay Simulation 1:4 Demultiplexer in VHDL using a Test bench. Then,

Synthesize on two different EDA tools.





Block Diagram:

Truth Table:

Input Select Output

A 00 Y(0)

B 01 Y(1)

C 10 Y(2)

D 11 Y(3)

Boolean Equation:

Y(3) = A.S.(1)‟.S(0)‟ Y(2) = B.S.(1)‟.S(0)

Y(1) = C.S.(1).S(0)‟ Y(0) = D.S.(1).S(0)

A 1:4

DemultiplexerY

S


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);

end component;

signal a : std_logic;signal s : std_logic_vector(1 downto 0);

signal y : std_logic_vector(3 downto 0);

begindemux14_tst_i : demux14 port map (a,s,y); -- positional association process

begin

a


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EXPERIEMENT NO. 5

Simulation and Synthesis of 2:4 Decoder using VHDL

Aim:Perform Zero Delay Simulation 2:4 Decoder in VHDL using a Test bench. Then,






Block Diagram:

Truth Table:

A Y

00 0001

01 0010

10 0100

11 1000

Boolean Equation:

Y(0) = A(1)‟. A(0)‟

Y(1) = A(1)‟.A(0) Y(2) = A(1).A(0)‟

Y(3) = A(1). A(0)

A2:4

Decoder Y


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VHDL Code:


entity decod24 is port ( a : in std_logic_vector(1 downto 0);

y : out std_logic_vector(3 downto 0)

);end decod24;

architecture decod24_beh of decod24 is -- behavioral modeling using case … end case

begin process(a)

begin

case a is

when "00" => y y y y y


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begin

a1


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EXPERIEMENT NO. 6

Simulation and Synthesis of 4:2 Encoder using VHDL

Aim:Perform Zero Delay Simulation 4:2 Encoder in VHDL using a Test bench. Then,






Block Diagram:

Truth Table:

A Y

1000 00

0100 01

0010 10

0001 11

Boolean Equation:Y(1) = A(1) + A(0)Y(0) = A(2) + A(0)

VHDL Code:library ieee;


entity encod42 is

port (a : in std_logic_vector(3 downto 0);

y : out std_logic_vector(1 downto 0)

A 4:2Encoder

Y


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);

end encod42;

architecture encod42_df of encod42 is

begin

with a selecty


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Simulation Waveform:

Synthesis:



Synthesis Report (Xilinx project Navigator):


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EXPERIEMENT NO. 7

Simulation and Synthesis of 4:2 Priority Encoder using VHDL

Aim:Perform Zero Delay Simulation 4:2 Priority Encoder in VHDL using a Test bench.

Then, Synthesize on two different EDA tools.





Block Diagram:

Truth Table:

A(3) A(2) A(1) A(0) Y(1) Y(0)

0 0 0 1 0 0

0 0 1 X 0 1

0 1 X X 1 0

1 X X X 1 1

A(3) A(2) A(1) A(0) Y(1) Y(0)

0 0 0 1 0 0

0 0 1 0 0 1

0 0 1 1 0 10 1 0 0 1 0

0 1 0 1 1 0

0 1 1 0 1 0

0 1 1 1 1 0

1 0 0 0 1 0

1 0 0 1 1 1

1 0 1 0 1 1

A4:2

Priority

Encoder

Y


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1 0 1 1 1 1

1 1 0 0 1 1

1 1 0 1 1 1

1 1 1 0 1 1

1 1 1 1 1 1

Boolean Equation:Y(1) = A(3) + A(2)

Y (0) = A(2)‟.A(1) + A(3).A(2) + A(3).A(0)



entity pri_encod42 is

port (a : in std_logic_vector(3 downto 0);

y : out std_logic_vector(1 downto 0);valid : out std_logic

);

end pri_encod42;

architecture pri_encod42_beh of pri_encod42 is

begin process(a)

begin

if (a(3) = '1') then

y


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wait for 100 ns;

a


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EXPERIEMENT NO. 8

Simulation and Synthesis of magnitude comparator 1-bit using

VHDL

Aim:Perform Zero Delay Simulation of magnitude comparator 1-bit in VHDL using a Test bench. Then, Synthesize on two different EDA tools.


Spectrum Synthesis Tool)ii) Xilinx Project Navigator 8.1 (Includes all the steps in the design flow from


Block Diagram:

Truth Table:

A B AgtB AltB AeqB

0 0 0 0 1

0 1 0 1 0

1 0 1 0 0

1 1 0 0 1

Boolean Equation:

AgtB = A.B‟ AltB = A‟.B AeqB = A‟.B‟ + A.B



use ieee.std_logic_arith.all;

A Magnitude

Comparator

1-bitB

AltB

AgtB

AeqB


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use ieee.std_logic_unsigned.all;

entity magcomp1 is port (a,b : in std_logic;

agtb, aeqb, altb : out boolean

);end magcomp1;

architecture magcomp1_df of magcomp1 is

beginagtb b;

altb


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end process;

end magcomp1_tst_a;

Simulation Waveform:

Synthesis:



Synthesis Report (Xilinx project Navigator):


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EXPERIEMENT NO. 9

Simulation and Synthesis of D latch and D flip flop using VHDL

Aim:Perform Zero Delay Simulation of d latch and d flip flop in VHDL using a Test bench.

Then, Synthesize on two different EDA tools.





VHDL Code:D-latch:

library ieee;


entity dlatch is

port (d,en,reset : in std_logic;

q : out std_logic);

end dlatch;

architecture dlatch_beh of dlatch is

signal s : std_logic;

begin

process(d,en,reset) begin

if (reset = „1‟) then

s


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end process;

end dff_asyncrst_a;

architecture dff_syncrst_a of dff is

begin

process(clk) beginif( clk'event and clk = '1') then

if (reset = '1') then

q


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d


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d


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EXPERIEMENT NO. 10

Simulation and Synthesis of JK, T Flip Flop using VHDL

Aim:Perform Zero Delay Simulation of JK, T, Flip flop in VHDL using a Test bench. Then,






VHDL Code:

JK-flip flop:


entity JKff is

port (j,k,clk,reset : in std_logic;q : out std_logic

);

end JKff;

architecture JKff_beh of JKff is

signal s : std_logic;

begin process(clk,reset)

begin

if (reset = '1') thens


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end if;

end process;

end JKff_beh;

T-flip flop:


entity tff is port (t,clk,reset : in std_logic;

q : out std_logic

);

end tff;

architecture tff_beh of tff is

signal s : std_logic; begin

process(clk,reset)

begin

if (reset = '1') thens


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tff_i : tff port map ( t,clk,reset,q);

clk

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Software Lab-IV BTEC 606 Lab Manual