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Test
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TM
SoC Test ChallengesDr. Yacoub El-Ziq
(408)868-0496
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TM OutlineOutline
• What is an SoC?• Why design with SoCs?• SoC Technology Trends• SoC Design & Test Methodology Flow .• SoC Test Challenges• Leading Test Synthesis Techniques• Future Test Trends• Relevant Websites.
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TM What is an SoCWhat is an SoC
• What is an SoC?A complex electronic system manufactured on a
single piece of silicon.• Examples: video camera, PDA/Cell phone,
wireless network, etc.• Future SoCs will contain some mechanical
parts as well.• Contains digital and/or analog circuitry.
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TM System on Chip (SoC)System on Chip (SoC)
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TM Why SoC?Why SoC?
Benefits of SoCs:Make it faster Make it cheaper Save power Make it possibleMajor market differentiator
Benefits of SoCs:Benefits of SoCs:Make it faster Make it faster Make it cheaper Make it cheaper Save power Save power Make it possibleMake it possibleMajor market differentiatorMajor market differentiator
SoC Challenges: More cost Increases TTM Presents major test challenges.
SoC Challenges: SoC Challenges: More cost More cost Increases TTM Increases TTM Presents major test challenges.Presents major test challenges.
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TM Technology TrendsTechnology Trends
Silicon Trends:Moore’s Law still in tact New materials: Al Cu SOI300 MM wafers.>1K signal pinsHi Speed serial I/O: > 2.5 Gb/secPower: 150 – 300W
Silicon Trends:Silicon Trends:Moore’s Law still in tact Moore’s Law still in tact New materials: Al New materials: Al Cu Cu SOISOI300 MM wafers.300 MM wafers.>1K signal pins>1K signal pinsHi Speed serial I/O: > 2.5 Hi Speed serial I/O: > 2.5 Gb/secGb/secPower: 150 Power: 150 –– 300W Test Trends:
More structural testing Low cost testersVery high speed testers
Test Trends:Test Trends:More structural testing More structural testing Low cost testersLow cost testersVery high speed testers Very high speed testers
300W
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TM SoC Design MethodologySoC Design Methodology
L og ica l
P h ys ica l
T e s t
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TM SoC Design FlowSoC Design Flow
R T L D e s ig n
L o g i c D e s ig n
P h y s ic a l D e s i g n
S o C M a n u f a c tu r in g
L e v e l 3
L e v e l 2
( S p e c )
( R T L )
L e v e l 1(N e t l is t )
L e v e l 0( G D S II )
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TM SoC Design ExamplesSoC Design Examples
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TM SoC TTM ImpactSoC TTM Impact
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TM SoC Test ChallengesSoC Test Challenges
Conventional Test Challenges:Testability AnalysisAd-hoc testability improvementsFault Simulation ATPGATE
Conventional Test Challenges:Conventional Test Challenges:Testability AnalysisTestability AnalysisAdAd--hoc testability improvementshoc testability improvementsFault Simulation Fault Simulation ATPGATPGATEATE
Test Synthesis Challenges: JTAGInternal ScanMemory BISTLogic BISTSoC Test Bus Standards
Test Synthesis Challenges: Test Synthesis Challenges: JTAGJTAGInternal ScanInternal ScanMemory BISTMemory BISTLogic BISTLogic BISTSoC Test Bus StandardsSoC Test Bus Standards
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TM Software vs. Hardware Software vs. Hardware
TestingTestingSoftware Testing focus:
functionalitySoftware Testing focus:Software Testing focus:
functionalityfunctionality
Hardware Testing focus: Functionality (Design Verification)Manufacturing DefectsAging (Field Failures)
Hardware Testing focus: Hardware Testing focus: Functionality (Design Verification)Functionality (Design Verification)Manufacturing DefectsManufacturing DefectsAging (Field Failures)Aging (Field Failures)
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TM Defective ChipsDefective Chips
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TM Fault TypesFault Types
Stuck-AtShortOpenIntermittentTimingAt-Speed
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TM Shipping Defective ProductsShipping Defective Products
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TM Yield vs. Test Coverage Yield vs. Test Coverage
RequirementsRequirements
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TM The Role of Test SynthesisThe Role of Test Synthesis
What is Test Synthesis?DFT, plus a lot more!
ATPG
System-level integration
ATE interface
How it is accomplished?Mandated at the system specification
level
DFT Integrated into logic synthesis
EDA tools used to generate ATPG vectors and fault coverage.
EDA tools verify ATE interfaces.Why needed?
Maximize test reuse
Lower test cost
Less-stringent ATE requirements
Faster TTM
Where in the product life cycle?Design Engineering
Manufacturing
Field
Reduces cost & Accelerates TTM
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TM Boundary Scan (JTAG)Boundary Scan (JTAG)
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TM Boundary Scan TAP ControllerBoundary Scan TAP Controller
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TM Internal Scan FlipInternal Scan Flip--FlopFlop
D D
Q /Q I s c a n _ in Q /Q I
C lk s c a n _ e n a b le a n d s c a n _ o u t
F /F
0m u x 1
F /F
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TM Multiple Scan ChainsMultiple Scan Chains
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TM RAM BIST Fault Model RAM BIST Fault Model
Stuck-At-1 & Stuck-At-0Stuck OpenTransition FaultState CouplingRAM Cell to RAM Cell multiple access fault.
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TM RAM BIST ControllerRAM BIST Controller
RAMBISTController
Pass/Fail
Data Out
Data In
Address
BIST Clock
BIST Select
Address
Data In
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TM Logic BIST Basic StructureLogic BIST Basic Structure
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TM SoC Future Test TrendsSoC Future Test Trends
Tighter Integration of Internal Scan, Boundary Scan, and BIST.System-level Structural Testing.Designing Structural testing into system diagnostics.More usage of SoC Internal System Bus and Test Bus standards.Lower cost ATE.
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TM Relevant WebsitesRelevant Websites
www.ieee.org
www.eetimes.com
www.cores.org
www.synopsys.com
www.mentor.com
