SoC Technology in the Era

of 3-D Tri-Gate Transistors for

Low Power, High Performance, and

High Density Applications

Peng Bai

Vice President, Technology Manufacturing Group

Intel Corporation

August 2013

p. 2 Peng Bai

Industry Leading Intel 22 nm SoC Technology

Moore’s Law in the Era of 3-D Tri-gate Transistor

Summary

Outlines

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Silicon

Substrate

Oxide

Gate

The 3-D Tri-gate Transistor Era Has Arrived with 22nm Technology

Intel 22 nm “Ivy Bridge” Microprocessor

World’s first product based on 22nm 3-D Tri-Gate transistor introduced in 2012

p. 4 Peng Bai

1 x

10 x

100 x

Leakage Floor

Voltage Ceiling

1 V

3 V

5 V

Density Device

NFmin

Analog RF Digital

Dense

Raise Transistor Voltage Ceiling

Lower Transistor Leakage Floor

CPU

Mixed Signals

RF Capability

High Density

Interconnect

3-D Tri-gate Transistor Foundation for SoC Platform Technology

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Transistor Performance vs. Leakage

Lo

we

r T

ran

sist

or

Le

ak

ag

e

Higher Transistor Performance (Switching Speed)

32nm 45nm 1x

0.1x

0.01x

0.001x

65nm 22nm

Laptop Ultrabook™

Tablet

Pocket Device

Server

Desktop

3-D Tri-gate transistor technology drive key SoC vectors in performance, low power,

and integration to optimize for a wider range of SoC products

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SoC 3-D Tri-gate Transistors

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(a)High Speed (HP/SP) Logic

(c) High Voltage (TG)

Main types of transistors – High performance, Low leakage and high voltage

Tri-gate SoC Transistor Family

(b) Low Power (LP/ULP) Logic

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Logic -High Speed (HP/SP) -Low Power (LP/ULP)

High Voltage

Dual gate flow : two distinct gate electrodes/gate dielectrics

Tri-Gate SoC – Dual Gate Process

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Transistor Type High Speed Logic Low Power Logic High Voltage

Options

High

Performance

(HP)

Standard

Perf./ Power

(SP)

Low

Power

(LP)

Ultra Low

Power

(ULP)

1.8 V 3.3 V

Vdd

(Volt) 0.75 / 1 0.75 / 1 0.75 / 1 0.75/1.2 1.5/1.8/3.3 3.3 / >5

Gate Pitch (nm) 90 90 90 108 min. 180 min. 450

Lgate (nm) 30 34 34 40 min. 80 min. 280

N/PMOS Idsat/Ioff

(mA/um)

1.08/ 0.91

@ 0.75 V,

100 nA/um

0.71 / 0.59

@ 0.75 V,

1 nA/um

0.41 / 0.37

@ 0.75 V

30 pA/um

0.35 / 0.33

@ 0.75 V

15 pA/um

0.92 / 0.8

@ 1.8 V

10 pA/um

1.0 / 0.85

@ 3.3 V

10 pA/um

22 nm Tri-gate SoC Transistor Characteristics

Mix-and-match flexibility of transistor types

Leading edge performance and low power for 22nm SoC products

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50

60

70

80

90

100

110

120

0 100 200 300

Su

b-t

hre

sho

ld S

lop

e (

mV

/de

cad

e)

Poly CD (nm)

1.8 V HVTransistor

LogicTransistor

32 nm

Planar

32 nm

Planar

22 nm

3-D Tri-gate

22 nm

3-D Tri-gateS.S. = 60 mV/dec

Near Ideal Sub-threshold Slope

Both logic and high voltage transistors show near ideal

sub-threshold slope with great short channel control

Ideal S. S.

= ln (kT/q) ~ 60

mV

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-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

25 35 45

Vtn

(V)

Leff (nm)

NMOS

PMOS

Logic (SP)Lower Logic

(LP/ULP)

Vtp

(V)

32 nm - Logic [2]

32 nm - Low Power [2]

Logic (SP) Lower Logic

(LP/ULP)

32 nm - Logic [2] 32 nm - Low Power [2]

Excellent short channel control of 22 nm tri-gate SoC reflects in

100 ~200 mV Vt reduction in all transistor types

Excellent Short Channel Control Leads to Vmin Reduction

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0.001

0.01

0.1

1

10

100

0 0.5 1

Ioff (n

A/u

m)

IDNsat (mA/um)

30 pA

Logic

(HP)

Logic

(SP)

30 pA

Low Power

(LP)

@ 0.75V

30 pA

NMOS

1 nA

100 nA

Low Power

(ULP)

30 pA

32 nm [3]

15 pA

32 nm [3]

0.001

0.01

0.1

1

10

100

0 0.5 1

Ioff (n

A/u

m)

IDPsat (mA/um)

PMOS

30 pA

100 nALogic

(HP)

Logic

(SP)

30 pALow Power

(LP)

1 nA

@ 0.75V

30 pA30 pA30 pA

Low Power

(ULP)

30 pA30 pA30 pA 30 pA

32 nm [3]

32 nm [3]

15 pA

Superior 22nm Tri-gate SoC High Performance Transistors

Higher Performance Higher Performance

Low

er

Leakage

High performance transistor Idsat and leakage improvement with pitch scaling

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0.001

0.01

0.1

1

0.001 0.01 0.1 1

Ioff

(n

A/u

m)

Ijunction (nA/um)

22 nm Tri-gate NMOS

22 nm Tri-gate PMOS

32 nm planar [3]

32 nm planar [3]

22 nm tri-gate

Superior 22 nm Tri-gate SoC Low Leakage Transistor

Lower Leakage

22 nm LP Ioff vs. GIDL/Ijunction superior than 32 nm planar LP

Gate

Source Drain

Gate

Source Drain

Gate

Source Drain

Gate Leakage( Igate )

Sub-threshold Leakage( Ioff , Isubthreshold )

Junction Leakage( Ijunction )

R I I V f CV Power 2 leakage

2 + + = a

) I I I I ( 2

1 I junction off off , gate on , gate leakage + + +

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Superior 22 nm SoC High Voltage I/O Transistors

Low

er

Leakage

Higher Performance Higher Performance

> 50% performance improvement in HV I/O transistors with pitch scaling

1.E-12

1.E-11

1.E-10

1.E-09

0 0.5 1

Ioff

(A/u

m)

IDsat (mA/um)

NMOS

@ 1.8 V

65 nm

Ox/Poly45 nm

Hi-k/MG

100 pA/um

10 pA/um

32 nm

Hi-k/MG

22 nm

Tri-gateHi-k/MG

+ 51%

1E-12

1E-11

1E-10

1E-09

0.0 0.5 1.0Io

ff (A

/um

)

IDsat (mA/um)

PMOS

@ 1.8 V

65 nm

Ox/Poly45 nm

Hi-k/MG

100 pA/um

10 pA/um

32 nm

Hi-k/MG

22 nm

Tri-gateHi-k/MG

+ 56%

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22 nm Tri-gate SoC Gate Dielectrics Reliability

22 nm Tri-gate SoC logic and HV I/O have robust gate dielectrics TDDB reliability

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

1.E+05

1.E+06

1.E+07

1.E+08

1.E+09

5 10 15

Tim

e t

o F

ail

[se

c]

VG/EOT [MV/cm]

32nm Planar

22nm Tri-gate

32nm Planar TG

22nm Tri-gate TG

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Interconnects

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22nm SoC Interconnect Systems – Performance and Density

CPU – 9 LM

High Performance

SoC – 9 LM

Standard

SoC – 11 LM

High Density

SoC – 11 LM

High Density

SoC – 11 LM

High Density

1 x pitch

1.4 x pitch2 x pitch

3 x pitch

4 x pitch

1 x pitch

( 2-6 layers)

1.4 x pitch

4 x pitch

2 x pitch

3 x pitch

SoC CPU

Focused on RC Performance

Focused on Flexibility and Density

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Top Metal

Key 22nm SoC Interconnect Features

ULK CDO dielectrics (lower layers), thick top metal, copper bump and lead-free solders

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Layer Pitch (nm)

Process Dielectric Materials

CPU SoC

Fin 60 - - Fin Fin

Contact 90 SAC - Contact Contact

M1 90 SAV ULK CDO M1 M1

MT - 1X 80 SAV ULK CDO M2/M3 2-6 layers

MT – 1.4x 112 SAV ULK CDO M4 Semi-global

MT – 2x 160 SAV ULK CDO M5 Semi-global

MT – 3x 240 SAV ULK CDO M6 Global Routing

MT – 4x 320 360

Via First LK CDO M7/8 Global Routing

MT - TOP 14 um Plate Up Polymer M9 Top Metal

22nm SoC Interconnect Design Rules Summary

Multiple interconnect offering to optimize for differing product requirements

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Analog/Passives/SRAM

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22 nm Tri-gate SoC Analog Characteristics

Improved Analog Performance

Significant gains in Gm*Rout characteristics of 22 nm Tri-gate transistors

0

5

10

15

65nm

Planar

45nm

Planar

32nm

Planar

22nm

Tri-gate

GM

* R

ou

t

GM*Rout@Vgs=peak GM, Vds=1.1 V, NMOS

p. 22 Peng Bai

High Q Inductors MIM Capacitor

Metal

Insulator

Metal

22 nm Tri-gate SoC Advanced Passive Devices

Precision Resistor

R C L

Normalized Resistance

+ 15% - 15%

100 90 110

Rich advanced passives precision resistors, MIM capacitors and high Q inductors

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6T SRAM

HDC

6T SRAM

LVC

6T SRAM

HPC

( 0.092 um2 )

( 0.108 um2 )

( 0.130 um2 )

22 nm Tri-gate SoC SRAM Offerings

Selected SRAM cell options including high density, low voltage and high performance

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Superior 22 nm Tri-gate SoC SRAM Bit Cell Leakage

Significant SRAM bit cell leakage reduction due to much improved short channel control

1

10

100

1000

32 nm LP

@ 1 V

22 nm LP

@ 1 V

22 nm LP

@ 0.75 V

22 nm LP

@ 0.6 V

Bit

Ce

ll L

ea

ka

ge

(p

A/c

ell) [3]

@ Standby/retention

p. 25 Peng Bai

1.0 2.0 3.0 4.0 5.0

0.6

0.7

0.8

0.9

1.0

Operating Frequency (GHz)

Su

pp

ly V

olt

ag

e (

V)

0.0

Fail

Pass

22 nm HP

Tri-gate [6]

22 nm SP

Tri-gate

22 nm LP

Tri-gate

32 nm LP

Planar [4]

65nm LP

Planar

4.6 GHz3.5 GHz2.6 GHz800 MHz 1.8 GHz

150 mV

Superior 22 nm Tri-gate SoC SRAM Performance and Vmin

40% frequency improvement or 150mV Vmin reduction over 32nm planar LP SRAM

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Moore’s Law

in the Era of 3-D Tri-gate Transistor

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Classical Scaling Ended with 90nm

A Look Back at History: Classical Era of Scaling

1/k = 0.7

p. 28 Peng Bai 28

Modern Era of Scaling Driven by Continual Innovations

3D Tri-gate Transistor the latest in a series of innovations

Strained Siliconh

High-k Metal Gate

Tri-Gate

90 nm 65 nm 45 nm 32 nm 22 nm

2003 2005 2007 2009 2011

p. 29 Peng Bai

Scaling Now Require New Materials and Structures

Strained Si: meff

High k: k

Metal Gate: Tinv

3-D Tri-gate: Vt

20 )VV(L

W)

T

k(

2

1I tg

effinveffdsat -=

em

High -k Metal GateStrained Si Tri -Gate

(Eq. 1)

0

0.5

1

1.5

2

1001000

Idsa

t (m

A/u

m)

Gate Pitch ( nm )

PMOS

NMOS

Idsat @ 1V,

100nA/um Ioff

Hi-k/Metal Gate

Strained Silicon

Oxide/Poly Gate

Strained Silicon

Oxide/Poly Gate

Non-Strained Si

0.13 um

90 nm

65 nm

45 nm

32nm

K. Mistry et al, IEDM Tech Dig., pp. 247-250 (2007)

C.-H. Jan et al, IEDM Tech. Dig., pp. 637-640 (2008)

S. Natarajan et al, IEDM Tech. Dig., pp. 941-943 (2008)

C.-H. Jan et al, IEDM Tech. Digest, paper 28.1 (2009)

C.-H. Jan, CSTIC ‘12

p. 30 Peng Bai

The Quest for Better Electrostatics and Short Channels

Increasing

Electrostatics

Planar

With High K Fins &

Multigate

UTB SOI

(or QW)

Hisamoto – IEDM 1989

Wires/Dots

Dupre

IEDM 2008 Tomioka – IEDM 2011

GATE

ALL AROUND

And many others

p. 31 Peng Bai

The Quest to Increase Mobility for Lower Voltage

Strain

Increasing

Mobility

Graphene CNT

Gate

SourceDrainn-Ge

Gate

SourceDrainn-Ge

Ge

InAlAs Barriers

QW

SEM Micrograph

InP

Energy Band DiagramEnergy Band DiagramEnergy Band Diagram

Si

d

III-V

0.0E+00

5.0E+06

1.0E+07

1.5E+07

2.0E+07

2.5E+07

3.0E+07

0 50 100 150 200 250

DIBL [mV/V]

Eff

ecti

ve V

elo

cit

y [

cm

/s]

InGaAs

Strained Si

InSb

>5X Veff

increase

VDS = 0.5V

VG-VT =

0.3V

p. 32 Peng Bai

Interconnect Increasing Importance for Scaling

Line width (nm)

Cu Resistivity from Grain and Sidewall scattering dominant at small dimension

p. 33 Peng Bai

Rethinking Interconnect Transport Mechanisms

Unlike diffusion & drift, delay for ballistic transport proportional to length

Interconnect Length (gate pitch)

Dela

y (

ps)

Source: S. Rakheja et al. IITC 2010

p. 34 Peng Bai

Heterogeneous System Integration

Logic

Memory

Power Reg.

Radio

Sensors

Photonics

2-D Integration (SoC)

3-D Integration (SiP)

Enable smart integration of a variety of functions and devices

Source: IEDM 2011: The Evolution of Scaling from the Homogeneous Era to the Heterogeneous Era, M. Bohr

p. 35 Peng Bai

Lithography Scaling Challenges

Scaling feature size without wavelength scaling are technical and cost challenges

10

100

1000

0.01

0.1

1

1980 1990 2000 2010 2020

Wa

ve

len

gth

(nm

)

Min

. Fe

atu

re S

ize

(u

m)

Year of Production

193 nm248 nm

EUV

32 nm

22 nm15 nm

S. Sivakumar,“Lithography for the 15 nm

node”,2010 IEDM Short Course (2010

p. 36 Peng Bai

Co-Optimization Key to Extracting Value from Moore’s Law

Packaging Masks

Process

Design Tools

Product

Manufacturing

Design for Manufacturing

Co-Optimized Process+Product

Rapid Yield Learning

Early Product Ramp

p. 37 Peng Bai

0

2,000

4,000

6,000

8,000

2005 2007 2009 2011 2013 2015

Exabytes

(1018)

Forecast

Source: IDC, YouTube, Apple, Facebook, Twitter, Intel

Other brands and names may be claimed as the property of others.

What Happens in

ONE MINUTE?

230K Tweets Posted

60 Hours of Video Uploaded

170K Photos Shared

204M Emails Sent

6,000 Songs Downloaded

7 EXABYTES OF DATA EVERY DAY

= 17,000 HD MOVIES

EVERY SECOND

DATA GROWTH

Digital Information Created

And approximately 4 trillion transistors shipped per minute in 2012

p. 38 Peng Bai

Intel has developed an industry leading 22nm SoC technology based on 3-D Tri-Gate transistor and introduced products since 2012.

3-D Tri-gate transistor serves as an excellent foundation for SoC platform technology in offering SoC features and their flexible integration for a wide range of products.

3-D Tri-Gate transistor technology is a key innovation in advancing Moore’s law, the foundation of the semiconductor industry.

Summary