SmartFusion2 SoC FPGA Fabric User Guide - Caxapacaxapa.ru/thumbs/591155/SmartFusion2_Fabric_UG.pdf · 2020. 2. 17. · SmartFusion2 SoC FPGA Fabric User Guide Revision 4 9 Fabric

SmartFusion2 SoC FPGA FabricUser Guide

SmartFusion2 SoC FPGA Fabric User Guide

Table of Contents

About this Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1 Fabric Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Fabric Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Logic Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Interface Logic Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10I/O Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11FPGA Routing Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Fabric Array Coordinate System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2 LSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

LSRAM Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Port List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Memory Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Dual-Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Two-Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Block Select Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

How to Use LSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37LSRAM Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3 Micro SRAM (uSRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

uSRAM Resource Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Revision 4 2


Port List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Port Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

How to Use uSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

4 Mathblocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Mathblock Resource Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

How to Use Mathblocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74Mathblock Use Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82Coding Style Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

5 I/Os. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93Transmit Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95Receive Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95Low Power Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96On-Die Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

I/O Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Supported I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98Single-Ended Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99Voltage-Referenced Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99Differential Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

I/O Programmable Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100Programmable Input Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101Programmable Slew Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102Programmable Weak Pull-Up/Pull-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102Programmable Schmitt Trigger Input and Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102Programmable Output Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103Configurable ODT and Driver Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104Low Power Signature Mode and Activity Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107Bus Keeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1075 V Input Tolerance and Output Driving Compatibility (only MSIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107Other I/O Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

I/Os in Conjunction with Fabric, MDDR/FDDR, and MSS Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110DDRIOs with MDDR/FDDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110DDRIOs with Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110MSIOs/MSIODs with MSS Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110MSIOs/MSIODs with Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

JTAG I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Dedicated I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112Device Reset I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

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Crystal Oscillator I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112SERDES I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

A List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

B Product Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119Customer Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Contacting the Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119Email . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119My Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120Outside the U.S. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

ITAR Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

4 Revision 4

About this Guide

PurposeSmartFusion®2 system-on-chip (SoC) field programmable gate array (FPGA)s integrate fourthgeneration flash-based FPGA fabric. The FPGA fabric composed of 4-input look-up table (LUT) logicelements, includes embedded memories and Mathblocks for DSP processing capabilities. Thisdocument describes the SmartFusion2 FPGA fabric architecture, embedded memories, Mathblocks,fabric routing, and I/Os.

ContentsThis user's guide contains the following chapters:

• Chapter 1 - Fabric Architecture

• Chapter 2 - LSRAM

• Chapter 3 - Micro SRAM (uSRAM)

• Chapter 4 - Mathblocks

• Chapter 5 - I/Os

Additional DocumentationTable 3 lists additional documentation available on SmartFusion2 SoC FPGAs. Refer to the web page for a complete and up-to-date listing: www.microsemi.com/soc/products/smartfusion2/docs.aspx.

Table 3 • Additional Documents

Document Description

SmartFusion2 SoC FPGA Product Brief This product brief provides an overview of SmartFusion2family, features, and development tools.

SmartFusion2 SoC FPGA Datasheet This datasheet contains SmartFusion2 DC and switchingcharacteristics.

SmartFusion2 Pin Descriptions This document contains SmartFusion2 pin descriptions,package outline drawings, and links to pin tables in Excelformat.

SmartFusion2 Microcontroller Subsystem User Guide SmartFusion2 devices integrate a hard microcontrollersubsystem (MSS). The MSS consists of a ARM® Cortex™-M3 processor with embedded trace macrocell (ETM),instruction cache, embedded memories, DMA engines,communication peripherals, timers, real-time counter (RTC),general purpose I/Os, and FPGA fabric interfaces. Thisdocument describes the SmartFusion2 MSS and its internalperipherals.

SmartFusion2 SoC FPGA High Speed DDR InterfacesUser Guide

SmartFusion2 devices integrate hard high-speed DDRmemory controllers for accessing external bulk memories.This document describes the SmartFusion2 high-speedexternal memory interfaces.

Revision 4 5

http://www.microsemi.com/soc/documents/SmartFusion2_PB.pdf

http://www.microsemi.com/soc/documents/SmartFusion2_DS.pdf

http://www.microsemi.com/soc/documents/SmartFusion2_PinInfo_DS.pdf

http://www.microsemi.com/soc/products/smartfusion2/docs.aspx

http://www.microsemi.com/soc/documents/SmartFusion2_CortexM3_UG.pdf

http://www.microsemi.com/soc/documents/SmartFusion2_HS_DDR_Interfaces_UG.pdf

http://www.microsemi.com/soc/documents/SmartFusion2_HS_DDR_Interfaces_UG.pdf

About this Guide

SmartFusion2 SoC FPGA High Speed SerialInterfaces User Guide

SmartFusion2 devices integrate hard high-speed serialinterfaces (PCIe, XAUI/XGXS, SERDES) for accessingexternal bulk memories. This document describes theSmartFusion2 high-speed serial interfaces.

SmartFusion2 Clocking Resources User Guide SmartFusion2 clocking resources include oscillators, FPGAfabric global network, and clock conditioning circuitry(CCCs) with dedicated phase-locked loops (PLLs). Theseclocking resources provide flexible clocking schemes to theon-chip hard IP blocks—MSS, fabric DDR (FDDR)subsystem, and high-speed serial interfaces (PCIe,XAUI/XGXS, SERDES)—and logic implemented in theFPGA fabric.

SmartFusion2 Low Power Design User Guide In addition to low static power consumption during normaloperation, SmartFusion2 devices support an ultra-low-powerStatic mode (Flash*Freeze mode) with power consumptionless than 1 mW. Flash*Freeze mode retains all the SRAMand register data which enables fast recovery to Activemode. This document describes the SmartFusion2Flash*Freeze mode entry and exit mechanisms.

SmartFusion2 Security and Reliability User Guide The SmartFusion2 device family incorporates essentially allthe security features that made third generation MicrosemiSoC devices the gold standard for security in the PLDindustry. Also included are unique design and data securityfeatures and use models new to the PLD industry.SmartFusion2 flash-based FPGA fabric has zero FITconfiguration rate due to its single event upset (SEU)immunity, which is critical in reliability applications. Thisdocument describes the SmartFusion2 security features anderror detection and correction (EDAC) capabilities.

SmartFusion2 System Controller User Guide The system controller manages programming of theSmartFusion2 device and handles system service requests.The subsystems, interfaces, and system services in thesystem controller are discussed in this user guide.

SmartFusion2 Programming User Guide Describes different programming modes supported inSmartFusion2 devices. High level schematics of theseprogramming methods are also provided as a reference.Important board-level considerations are discussed.

Libero SoC User Guide Libero® System-on-Chip (SoC) is the most comprehensiveand powerful FPGA design and development softwareavailable, providing start-to-finish design flow guidance andsupport for novice and experienced users alike. Libero SoCcombines Microsemi SoC Products Group tools with suchEDA powerhouses as Synplify®, ModelSim®, andViewDraw®. This user guide discusses the usage of thesoftware and design flow.

Table 3 • Additional Documents (continued)

Document Description

6 Revision 4

http://www.microsemi.com/soc/documents/SmartFusion2_Sys_Ctrl_UG.pdf

http://www.microsemi.com/soc/documents/SmartFusion2_HS_Serial_ Interfaces_UG.pdf

http://www.microsemi.com/soc/documents/SmartFusion2_PLL_CCC_UG.pdf

http://www.microsemi.com/soc/documents/SmartFusion2_LPower_UG.pdf

http://www.microsemi.com/soc/documents/SmartFusion2_Security_UG.pdf

http://www.microsemi.com/soc/documents/SmartFusion2_Programming_UG.pdf

http://www.microsemi.com/soc/documents/libero_ug.pdf

1 – Fabric Architecture

IntroductionThe SmartFusion2 SoC FPGA fabric comprises an array of logic elements and embedded hard blockssuch as large static random access memory (LSRAM), micro SRAM (uSRAM), and mathblocks for digitalsignal processing (DSP) capability. These elements are arranged as several rows inside the fabric,interconnected by the clustered routing architecture of the SmartFusion2 device. Each element in thefabric has a distinct logical coordinate value assigned to it. Figure 1-1 on page 8 shows the simple layoutof the SmartFusion2 SoC FPGA fabric architecture.

Three types of resources constitute the major part of the fabric:

• Logic elements

• Interface logic elements

• I/O modules

The logic element is the basic element used for implementing the combinatorial circuits, arithmeticfunctions, and sequential circuits inside the fabric. Each logic module consists of a 4-input LUT, a D-flip-flop, and a dedicated carry chain.

The interface logic is the logic element that interfaces the embedded hard blocks to the fabric routing.The interface logic enables the accessibility of the embedded hard block through the fabric routing. Theinterface logic is structurally similar to the logic element except that it does not contain the dedicatedcarry chain. The interface logic can also be used to implement the combinatorial and sequential circuits,if the associated embedded hard block is not being used by the design.

The I/O module forms the digital part of the fabric user I/Os, also called as multi-standard inputs/outputs(MSIOs). The I/O module enables the user I/Os to be connected to the fabric routing, thus, enabling therouting of the external world signals to and from the logic elements inside the fabric.

The SmartFusion2 fabric uses a clustered routing architecture to interconnect the various elementsinside the fabric. In clustered architecture, various logic elements are grouped together to form theclusters. There are three types of clusters in the SmartFusion2 SoC FPGA fabric:

• Logic clusters

• Interface clusters

• I/O clusters

The logic cluster is composed of 12 logic elements; the interface cluster is composed of 12 interface logicelements. I/O clusters are composed of 3 to 4 I/O modules, which are distributed on four sides of thedevice, as shown in Figure 1-1 on page 8 (north, south, east, and west I/O clusters).

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Fabric Architecture

Figure 1-1 • SmartFusion2 Fabric Architecture for M2S050

North I/O Clusters

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Fabric ResourcesTable 1-1 lists the fabric resources available on SmartFusion2 devices.

Architecture OverviewThe following sections of this chapter describe the SmartFusion2 SoC FPGA fabric architecture in detail.

• Logic Element

• Interface Logic Element

• I/O Module

• FPGA Routing Architecture

Logic ElementThe logic element is the basic logic block in the SmartFusion2 FPGA fabric. These logic elements can beused as a combinational logic element (CLE), or sequential logic element (SLE) in the design. Each logicelement consists of:

• A fully permutable 4-input LUT

• A dedicated carry chain based on the carry look-ahead technique

• A separate flip-flop which can be used independently from the LUT

Figure 1-2 on page 10 shows the functional block diagram of the logic element with carry chain.

Table 1-1 • Fabric Resources for SmartFusion2 Devices

Fabric Resource M2S005 M2S010 M2S025 M2S050 M2S090 M2S100 M2S150

Logic elements

(4-input LUT + Flip-Flop)6,060 12,084 27,696 56,340 86,316 99,512 146,124

LSRAM 18K blocks 10 21 31 69 109 160 236

uSRAM 1K blocks 11 22 34 72 112 160 240

Mathblocks 11 22 34 72 84 160 240

PLLs and CCCs 2 2 6 6 6 8 8

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Fabric Architecture

The 4-input LUT can be configured to implement any 4-input combinatorial function or to implement an arithmetic function, where the LUT output is XORed with carry input (Cin) to generate the sum (S) output. The sum output, S, is typically used as an output for arithmetic functions but can also be used as an output for logical functions along with the other output, Y, when the LUT is used to implement combinatorial functions.

Each logic element has a dedicated 3-bit look-ahead carry implementation, which is used to implement adedicated carry chain between the logic elements when the LUT is used to implement arithmeticoperations.

The carry chain has hardwired routing nets running between the logic elements, which reduces the carrypropagation delay through the carry chain, thus giving better performance. The logic element alsocontains a dedicated flip-flop, which can be used in conjunction with or independently from the LUT. Theflip-flop can be configured as a register or latch. It has asynchronous and synchronous load and clockenable inputs. The data input of the flip-flop can be fed from the direct input (D1) or from the outputs ofthe 4-input LUT inside the logic element.

Interface Logic ElementEmbedded hard blocks (LSRAM blocks, uSRAM blocks, and mathblocks) contain a dedicated interfacelogic. The embedded hard blocks are connected to the fabric routing structure through LUTs and flip-flops on their inputs and outputs, and these together form the interface logic element.

Each embedded hard block is associated with 36 interface logic elements. This interface logic element isstructurally equivalent to a logic element but does not have a dedicated carry chain. When a givenembedded hard block is used by the target design, the interface logic is used to connect the embeddedhard block’s I/Os to the fabric routing. If an embedded hard block is not used by the design, the interfacelogic element is available for use as a normal logic elements for implementing combinatorial andsequential circuits. These are in addition to logic elements available in the fabric.

Figure 1-2 • Functional Block Diagram of Logic Element

Y

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I/O ModuleThe I/O module includes the I/O digital (IOD) circuitry and the associated routing interface. Each user I/Opad is connected to its own dedicated I/O module. The I/O module interfaces the user I/Os with the fabricrouting and enables the routing of external signals coming in though the I/Os to reach all the logicelements. The I/O modules also enable the internal signals to reach the I/Os.

Figure 1-3 shows the functional diagram of the complete MSIO with the IOD and I/O analog (IOA)sections. The IOD consists of the input registers, output registers, output enable registers, and routingmultiplexers (MUXes). The output register provides the registered version of the output signals to theI/Os. In the same way, the input registers are used to register the inputs received from the I/Os. Theoutput enable acts as a control signal for the output, if the I/O is configured as a tristated or bidirectionalI/O. These registers in the I/O modules are similar to the D-flip-flops available in the logic element. Theusage of the output registers in the I/O modules for registering the output signals at I/Os enables betterdesign performance. Also, in the case of a signal bus, these registers ensure that all the bits of the signalbus are synchronized to the clock signal when being sent out through the I/Os. At the input side, the inputregisters allow capturing the input signals and synchronizing them to the design clock.

Figure 1-3 • Functional Block Diagram of MSIO

outreg

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Fabric Architecture

FPGA Routing ArchitectureThe SmartFusion2 SoC FPGA fabric has a clustered routing architecture. Clustering is a hierarchicalgrouping of fabric resources that allows a more area-efficient implementation of designs whilemaintaining optimal performance. It also helps in reducing the run-time of the place-and-route software.

The SmartFusion2 fabric routing architecture is composed of three types of clusters:

• Logic Cluster

• Interface Cluster

• I/O Cluster

Logic ClusterThe logic cluster is a combination of 12 logic elements with a dedicated hardwired carry chainimplemented for all 12 logic elements. The logic clusters contain routing MUXes. Each routed signal isdriven by a unique logic element output or routing MUX. All the logic elements are interconnected withfeedback from outputs to inputs. The intra-routing inside the logic clusters has very low propagation delayas compared to the routing outside the logic clusters.

Each LUT, D-flip-flop, and the carry-circuit in the logic cluster have an individual X-Y logical coordinateassigned, and this makes them independently addressable. Figure 1-4 shows the top-level logic clusterlayout diagram.

Interface ClusterThe interface cluster is similar to the logic cluster except that it is a combination of 12 interface logicelements. These clusters are used to interface the inputs and outputs of the embedded hard blocks(LSRAM, uSRAM, mathblocks, and CCCs) to fabric routing. Each embedded hard block is spanned by 3interface clusters, as shown in Figure 1-5 on page 13. The interface logic can be used as a logicelements (without carry chain) when the associated embedded hard block is not used by the design.

Figure 1-4 • Logic Cluster Top-Level Layout

Logic Elements

Cluster Carry INCluster Carry Out

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Buffers

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12 Revision 4


I/O ClusterI/O clusters are combinations of I/O modules and the associated routing interfaces. The north and southI/O clusters each contain four I/O modules. The east and west I/O clusters, each contain three I/Omodules. Each I/O pad is associated with its own dedicated I/O module.

Routing StructureThe routing of any design is completed automatically by the Libero placement-and-routing software, thus,it is completely transparent. The selection among various routing resources by the placement-and-routing software depends upon the design constraints provided.

Knowledge of the routing architecture and functional modules can be useful in providing correct designconstraints to the placement and routing software, so that it can be guided to do an optimal designimplementation on the SmartFusion2 fabric.

In the SmartFusion2 device, the fabric routing is segregated into two parts:

• Inter-cluster routing

• Intra-cluster routing

Figure 1-5 • Interface Cluster

Interface Cluster

Routing

Interface Cluster

Embedded Hard Blocks-LSRAMs, µSRAMs, Mathblocks, CCCs

3 Clusters Wide

Interface LogicLUT+FF

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Figure 1-6 shows the fabric routing structure for the SmartFusion2 device.

Inter-cluster routing spans the clusters and connects them together. The inter-cluster routing resource is common to all the clusters inside the fabric and is universal across the clusters.

Intra-cluster routing spans the modules that constitute a cluster. Intra-cluster routing is not unique andvaries from cluster to cluster, depending upon the functionality of the cluster. For example, the intra-cluster routing for an interface cluster is different from that of a logic cluster. There are differences in therouting of the various interface clusters, depending upon the embedded hard block to which theyinterface.

Inter-cluster routing and intra-cluster routing are completely separate. Inter-cluster routing never drivesthe inputs of the functional modules (logic elements, interface logic elements, or I/O modules) directlyand the outputs of the functional modules do not drive the inter-cluster routing directly. Inter-clusterrouting has to pass through the intra-cluster routing to reach the functional modules. That makesSmartFusion2 routing a fully clustered routing architecture.

The global network can also directly drive intra-cluster routing through special routing MUXes. Theseglobal routing MUXes bring in flip-flop control signals such as clock, enable, and sets/resets.

There are a few short routing lines between the adjacent clusters and between the inter-cluster and intra-cluster routing MUXes. These short paths are provided to provide better performance to the signalsrouted through these lines.

Fabric Array Coordinate SystemEvery element in the SmartFusion2 SoC FPGA fabric has individual logical X-Y coordinates associatedwith the fabric array coordinate system. These logical coordinates are used by the Libero SoC place-and-route software while implementing the design using the fabric elements. The place-and-routesoftware can be constrained to occupy the design components in specific locations inside the fabricusing this coordinate system. Regions can be created inside the fabric and a particular part of the designcan be assigned to that region using the Libero SoC floor-planner software.

Figure 1-6 • Fabric Routing Structure

Inter-Cluster Routing

ClusterIntra-Cluster Routing (3 Levels of Routing Muxes)

Logic Elements

Output MUXes

Inter-Cluster Routing

From Other Clusters

To Other Clusters

To Other Clusters

From Adjacent Clusters

To Adjacent Clusters

From Other Clusters

14 Revision 4


The boundaries of these regions can be specified using the array coordinates. Similarly, the embeddedhard block is also addressable through the fabric coordinate system.

The array coordinates are measured from the bottom left corner to the top right corner of the FPGAfabric. Table 1-2 on page 17 provides the array coordinates of logical modules and embedded hardblocks of SmartFusion2 devices. Figure 1-7, Figure 1-8 on page 16, and Figure 1-9 show the arraycoordinates of an M2S050, M2S025, and M2S010 devices. For more information on how to use arraycoordinates for region/placement constraints, refer to the Libero SoC User Guide or online help(available in the software) for SmartFusion2 Libero SoC tools.

Figure 1-7 • M2S050 Fabric Logical Coordinates

(0,206)

Mathblocks (0,158)

uSRAM (0,146)

LSRAM (0,134)

LSRAM (36,11)

Mathblocks (0,95)

uSRAM (0,83)

Mathblocks (0,59)

uSRAM (0,47)

LSRAM (36,194)

(887,206)

(887,158)

(887,146)

(887,134)

(887,11)

(887,0)

(887,95)

(887,83)

(887,59)

(887,47)

(851,194)

(0,0)

Revision 4 15


Fabric Architecture



(0,146)

Mathblocks (0,110)

uSRAM (0,98)

LSRAM (36,11)

Mathblocks (0,35)

uSRAM (0,23)

LSRAM (36,194)

(635,146)

(635,110)

(635,98)

(635,11)

(635,0)

(635,35)

(635,23)

(599,194)

(0,0)

(0,104)

Mathblocks (0,80)

uSRAM (0,68)

uSRAM (0,11)

LSRAM (0,47)

Mathblocks (0,23)

LSRAM (0,92)

(407,104)

(407,80)

(407,68)

(407,11)

(407,0)

(407,47)

(407,23)

(371,92)

(0,0)

16 Revision 4


Glossary

Acronyms

uSRAMMicro static random access memory

CCC Clock conditioning circuits

LSRAMLarge static random access memory

Terminology

ClustersClusters are formed by grouping a certain number of logic elements and interconnecting them. This isrelated to the clustered routing architecture of SmartFusion2 SoC FPGA fabric.

Interface ClusterAn interface cluster is formed by grouping 12 interface logic elements.

I/O ClusterI/O cluster is formed by grouping either 3 or 4 I/O modules.

Interface LogicThe logic element consists of a 4-input LUT and a D flip-flop. This logic element interfaces the hardmacros (LSRAMs, uSRAMs, and mathblocks) to fabric routing.

I/O ModuleThe logic element consists of flip-flops and routing MUXes. This logic element interfaces the user I/Os tofabric routing.

Inter-cluster RoutingInter-cluster routing refers to routing resources between various types of clusters.

Intra-cluster RoutingIntra-cluster routing refers to routing resources existing inside a specific cluster.

Table 1-2 • Fabric Array Coordinate Systems

Device

Logic Elements uSRAM LSRAM Mathblocks

Min Max Bottom Middle Top Bottom Middle Top Bottom Middle Top

X Y X Y (X,Y) (X,Y) (X,Y) (X,Y) (X,Y) (X,Y) (X,Y) (X,Y) (X,Y)

M2S005 - - - - - - - - - - - - -

M2S010 0 0 407 104 (0,11) NA (0,68) (0,47) NA (0,92) (0,23) NA (0,80)

M2S025 0 0 635 146 (0,23) NA (0,98) (36,11) NA (36,134) (0,35) NA (0,110)

M2S050 0 0 887 206 (0,47) (0,83) (0,146) (36,11) (0,134) (36,194) (0,59) (0,95) (0,158)

M2S090 - - - - - - - - - - - - -

M2S100 - - - - - - - - - - - - -

M2S0150 - - - - - - - - - - - - -

Revision 4 17

Fabric Architecture

Logic ClusterA logic cluster is formed by grouping 12 logic elements.

Logic ElementThe basic logic element in SmartFusion2 SoC FPGA fabric, consisting of a 4-input LUT, a D-flip-flop, and a dedicated carry chain.

List of ChangesThe following table lists critical changes that were made in each revision.

Date Changes Page

Revision 4(September 2013)

Updated Figure 1-3 • Functional Block Diagram of MSIO (SAR 48166). 11

Updated Table 2-1 • Number of LSRAM 18K Blocks Available per Device, Table 3-1 • SmartFusion2 uSRAM (1Kb Blocks) Resource, and Table 4-1 • SmartFusion2 Mathblocks Resource (SAR 48420).

20, 48, and 69

Revision 3(May 2013)

Table 1-1 • Fabric Resources for SmartFusion2 Devices and Table 1-2 • Fabric Array Coordinate Systems are modified (SAR 47579).

9 and 17

Updated the "Interface Logic Element" section (SAR 47435). 10

Revision 2(April 2013)

Restructured the document (SAR 41767). NA

18 Revision 4

2 – LSRAM

IntroductionThe SmartFusion2 SoC FPGA fabric has embedded 18 Kbit SRAM blocks used for storing data. Theselarge SRAM blocks (LSRAMs) are arranged in multiple rows within the FPGA fabric and can beaccessed through the fabric routing architecture. The number of LSRAM blocks available depends uponthe specific SmartFusion2 device, as shown in Table 2-1 on page 20. For example, in the M2S050 devicethere are 69 LSRAM blocks available, which are spread across three rows inside the fabric.

FeaturesSmartFusion2 LSRAM blocks have the following features:

• Each LSRAM block can store up to 18,432 bits of data and can be configured in any of thefollowing depth x width combinations: 512 x 36, 512 x 32, 1k x 18, 1k x 16, 2k x 9, 2k x 8, 4k x 4,8k x 2, or 16k x 1.

• Each LSRAM block contains two independent data ports—Port A and Port B.

• The LSRAM is synchronous for both read and write operations. These operations are triggered onthe rising edge of the clock.

• Supports maximum frequency up to 400 MHz.

• An optional pipeline register is available at the read data port to improve the clock-to-out delay.

• LSRAM supports two types of read operations:

– Flow-through read (or non-pipelined)

– Pipelined read

• LSRAM supports two types of write operations:

– Simple write

– Feed-through write (write-bypass write)

• LSRAM can be operated in two memory modes:

– Dual-port mode

– Two-port mode

• A write operation requires one clock cycle.

• A read operation requires one clock cycle in Non-pipelined mode. In Pipelined mode, the outputdata appears in the next cycle.

• Read from both ports at the same location is allowed.

• Read and write on the same location at the same time is not allowed. There is no built in collisionprevention or detection circuit in LSRAM.

Revision 4 19

LSRAM

LSRAM ResourcesTable 2-1 lists LSRAM rows and 18k blocks available in SmartFusion2 devices.

Functional DescriptionThis section provides the detailed description of the following:

• Architecture Overview

• Port List

• Port Descriptions

Architecture Overview SmartFusion2 LSRAM embedded memory includes the RAM1Kx18 macro. Figure 2-1 shows a simplifiedblock diagram of the LSRAM memory block and Table 2-2 on page 21 provides the port descriptions.Figure 2-1 displays two independent data ports, the pipeline registers for read data delay, and the feed-through multiplexers to enable immediate access to the write data.

Table 2-1 • Number of LSRAM 18K Blocks Available per Device

Device M2S005 M2S010 M2S025 M2S050 M2S090 M2S100 M2S150

Rows 1 2 2 3 4 4 6

LSRAM 18 K Blocks 10 21 31 69 109 160 236

Note: All numbers given above are per device.

Figure 2-1 • Simplified Functional Block Diagram for LSRAM

A_DOUT[ 17 : 0 ]

A_DIN[ 17 : 0 ]

B_ DIN [ 17: 0]

A_ARST_N

A_ ADDR[ 13: 0 ]

A_WEN[ 1: 0]

A_BLK[ 2 : 0]

A _CLK

B_ADDR[ 13: 0 ]

B_WEN[ 1: 0]

B_BLK[ 2: 0 ]

B_CLK

` B_ARST_N

Port A Row DecodeWrite Control

Port B Row DecodeWrite Control

Column Decode

Column Decode

B_ DOUT_CLK

A

A_WMODE

_ DOUT_CLK

B_DOUT[ 17 : 0 ]

Memory

Array

1 K x 18

Feed-through MUX

Pipeline Register

B_WMODE

A_DOUT_LAT

B_DOUT_LAT

20 Revision 4


Port List

Table 2-2 • Port List for LSRAM Macro (RAM1KX18)

Port Name Direction Type1 Description Polarity

PORT A

A_WIDTH[2:0] Input Static Port A Width/depth mode select –

A_WEN[1:0]2 Input Dynamic Port A Write enable High

A_ADDR[13:0] Input Dynamic Port A Address input –

A_DIN[17:0] Input Dynamic Port A Data input –

A_DOUT[17:0] Output Dynamic Port A Data output –

A_BLK[2:0] Input Dynamic Port A Block select High

A_WMODE Input Static Port A Feed-through write select High

A_CLK Input Dynamic Port A Clock Rising

A_ARST_N Input Dynamic Port A Asynchronous reset Low

A_DOUT_CLK Input Dynamic Port A Pipeline register clock Rising

A_DOUT_LAT Input Static Port A Pipeline register Select Low

A_DOUT_ARST_N Input Dynamic Port A Pipeline register asynchronous reset

Low

A_DOUT_EN Input Dynamic Port A Pipeline register enable High

A_DOUT_SRST_N Input Dynamic Port A Pipeline register synchronous reset

Low

PORT B

B_WIDTH[2:0] Input Static Port B Width/depth mode select –

B_WEN[1:0]2 Input Dynamic Port B Write enable High

B_ADDR[13:0] Input Dynamic Port B Address input –

B_DIN[17:0] Input Dynamic Port B Data input –

B_DOUT[17:0] Output Dynamic Port B Data output –

B_BLK[2:0] Input Dynamic Port B Block select High

B_WMODE Input Static Port B Feed-through write select High

B_CLK Input Dynamic Port B Clock Rising

B_ARST_N Input Dynamic Port B Asynchronous reset Low

B_DOUT_CLK Input Dynamic Port B Pipeline register clock Rising

B_DOUT_LAT Input Static Port B Pipeline register select Low

B_DOUT_ARST_N Input Dynamic Port B Pipeline register asynchronous reset

Low

B_DOUT_EN Input Dynamic Port B Pipeline register enable High

Notes:

1. Static inputs are defined at design time and can be or are controlled by flash configuration bits.

2. If LSRAM is configured in Two-port mode with a write data width of x36/x32 and read data width of x36/x32, both the bits of A_WEN and B_WEN must be tied to logic 1 and should not be dynamically changed.

Revision 4 21

LSRAM

Port Descriptions

A_WIDTH[2:0] and B_WIDTH[2:0]These signals represent the depth x width mode selections for each port. Table 2-3 shows the depth xwidth based on ports width selection.

A_WEN[1:0] and B_WEN[1:0]These signals represent the write enables for each port to select read/write operations. Table 2-4 shows the depth x width operations based on port write enable selection.

B_DOUT_SRST_N Input Dynamic Port B Pipeline register synchronous reset

Low

Common Signals

A_EN Input Static Port A power-down Low

B_EN Input Static Port B power-down Low

SII_LOCK Input Static Lock access to SII High

BUSY Output Dynamic Busy signal from SII High

Table 2-2 • Port List for LSRAM Macro (RAM1KX18) (continued)

Port Name Direction Type1 Description Polarity

Notes:

1. Static inputs are defined at design time and can be or are controlled by flash configuration bits.

2. If LSRAM is configured in Two-port mode with a write data width of x36/x32 and read data width of x36/x32, both the bits of A_WEN and B_WEN must be tied to logic 1 and should not be dynamically changed.

Table 2-3 • Depth/Width Mode Selection

A_WIDTH/B_WIDTH Depth/Width

000 16K x 1

001 8K x 2

010 4k x 4

011 2K x 92K x 8

100 1K x 181K x 16

101110111(Two-port)

512 x 36512 x 32

22 Revision 4


Table 2-4 • Read/Write Operation Selection1,2

Depth x Width A_WEN/B_WEN Operation

16K x 1

8K x 2

4K x 4

2K x 8

2K x 9

1K x 16

1K x 18

00 Read operation

16K x 1

8K x 2

4K x 4

2K x 8

2K x 9

01 Write operation

1K x 16 01 Write [7:0]

10 Write [15:8]

11 Write [15:0]

1K x 18 01 Write [8:0]

10 Write [17:9]

11 Write [17:0]

512 x 32

(Two-port write-Port B)

A_WEN[1:0] = “11”

B_WEN[1:0] = “11”

Write [31:0]

512 x 36

(Two-port write-Port B)

A_WEN[1:0] = “11”

B_WEN[1:0] = “11”

Write [35:0]

Notes:

1. In Dual-port mode, every port reads when the corresponding write enable (A_WEN/B_WEN) is "00" and corresponding port select (A_BLK/B_BLK) is active.

2. In Two-port mode, the read port (Port A) reads in every clock cycle if A_BLK is active.

Revision 4 23

LSRAM

A_ADDR[13:0] and B_ADDR[13:0]These signals represent the address buses for the two ports. In x1 mode 14 bits are used to address the16,384 independent locations. In wider modes (x2, x4, etc.) fewer address bits are used. The usedaddress bits are the most significant bits (MSB). The unused bits are the least significant bits (LSBs) andthey must be grounded. Table 2-5 shows the address bus used and unused bits for depth x widthselections.

A_DIN[17:0] and B_DIN[17:0]These signals represent the data input buses for the two ports. In Dual-port mode, the data width canrange from 1 bit to 18 bits. In Two-port mode, Port B becomes the write-only port. Giving a write datawidth of 36 bits, A_DIN[17:0] becomes write data[35:18] and B_DIN[17:0] becomes write data[17:0]. Theused bits for any mode are LSB justified in the data bus and the unused MSB bits must be grounded.Table 2-6 shows the data input buses used and unused bits for depth x width selections.

Table 2-5 • Address Bus Used and Unused Bits

Depth x Width

A_ADDR/B_ADDR

Used Bits Unused bits (to be grounded)

16K x 1 [13:0] None

8K x 2 [13:1] [0]

4K x 4 [13:2] [1:0]

2K x 9

2K x 8

[13:3] [2:0]

1K x 18

1K x 16

[13:4] [3:0]

512 x 36 [13:5] [4:0]

Table 2-6 • Data Input Buses Used and Unused Bits

Depth x Width

A_DIN/B_DIN


16K x 1 [0] [17:1]

8K x 2 [1:0] [17:2]

4K x 4 [3:0] [17:4]

2K x 8 [7:0] [17:8]

2K x 9 [8:0] [17:9]

1K x 16 [16:9] is [15:8]

[7:0] is [7:0]

[17]

[8]

1K x 18 [17:0] None

512 x 32 A_DIN[16:9] is [31:24]

A_DIN[7:0] is [23:16]

B_DIN[16:9] is [15:8]

B_DIN[7:0] is [7:0]

A_DIN[17]

A_DIN[8]

B_DIN[17]

B_DIN[8]

512 x 36 A_DIN[17:0] is [35:18]

B_DIN[17:0] is [17:0]

None

24 Revision 4


A_DOUT[17:0] and B_DOUT[17:0]These signals represent the data output buses for the two ports. In Dual-port mode, the data width canrange from 1 bit to 18 bits. In Two-port mode, Port A becomes the read-only port. Giving a read datawidth of 36 bits, A_DOUT[17:0] becomes read data[35:18] and B_DOUT[17:0] becomes read data[17:0].The used bits for any mode are LSB justified in the data bus and the unused MSB bits must be grounded.Table 2-7 shows the data output buses used and unused bits for depth x width selections.

Table 2-7 • Data Output Buses Used and Unused Bits

Depth x WidthA_DOUT/B_DOUT


16K x 1 [0] [17:1]

8K x 2 [1:0] [17:2]

4K x 4 [3:0] [17:4]

2K x 8 [7:0] [17:8]

2K x 9 [8:0] [17:9]

1K x 16 [16:9] is [15:8]

[7:0] is [7:0]

[17]

[8]

1K x 18 [17:0] None

512 x 32 A_DOUT[16:9] is [31:24]

A_DOUT[7:0] is [23:16]

B_DOUT[16:9] is [15:8]

B_DOUT[7:0] is [7:0]

A_DOUT[17]

A_DOUT[8]

B_DOUT[17]

B_DOUT[8]

512 x 36 A_DOUT[17:0] is [35:18]

B_DOUT[17:0] is [17:0]

None

Revision 4 25

LSRAM

A_BLK[2:0] and B_BLK[2:0]These signals represent the port select control signals for each port. Table 2-8 shows operations (Read, Write, and No operation) based on selection of port select control signals.

A_WMODE and B_WMODEThese signals represent the Write mode control signals for Port A and Port B.

• Logic 0: Output data port holds the previous value.

• Logic 1: Feed-through; write data appears on the corresponding output data port. In Two-portmode, feed-through write is not supported.

A_CLK and B_CLKThese signals represent the clock inputs for Port A and Port B. All inputs must be set up before the risingedge of the clock. The read or write operation begins with the rising edge.

A_ARST_N and B_ARST_NThese signals represent Active Low, asynchronous reset inputs for Port A and Port B. Assertion of theseresets during read operation forces the data output lines to logic 0. Assertion of these resets during writeoperation results in garbage values written into the memory.

A_DOUT_ARST_N and B_DOUT_ARST_NThese signals represent Active Low, asynchronous reset inputs for the output pipeline registers for Port Aand Port B. Assertion of these reset signals forces the data output to logic 0. In Non-pipelined mode,these inputs should be tied to logic 1.

A_DOUT_LAT and B_DOUT_LATThese signals represent Latch mode inputs for the output pipeline registers for Port A and Port B.

• Logic 0: Register operation

• Logic 1: Latch operation

Table 2-8 • Port Select Control Signals

Port Select Signal Value Result

A_BLK[2:0] 111 Perform read or write operation on Port A.

A_BLK[2:0] 000

001

010

011

100

101

110

No operation in memory from Port A. Port A output is forced to logic 0.

B_BLK[2:0] 111 Perform read or write operation on Port B.

B_BLK[2:0] 000

001

010

011

100

101

110

No operation in memory from Port B. Port B output is forced to logic 0.

26 Revision 4


A_DOUT_EN and B_DOUT_ENThese signals represent Active High; enable inputs for the output pipeline registers for Port A and Port B.

• Logic 1: Normal register operation

• Logic 0: Register holds previous data

A_DOUT_SRST_N and B_DOUT_SRST_NThese signals represent Active Low, synchronous reset inputs for the output pipeline registers for Port Aand Port B. Assertion of these reset signals forces the data output to logic 0. In Non-pipelined mode,these inputs should be tied to logic 1.

A_EN and B_ENThese are Active Low, power-down configuration bits for each port.

SII_LOCKThis control signal, when asserted to logic 1, locks the entire LSRAM memory for being accessed by thesystem controller interface bus (SII). The system controller can access the LSRAM for the followingpurposes:

• Testing the memory

• Moving data between LSRAM and embedded nonvolatile memory (eNVM) or external memories

• Moving data between various LSRAMs or between uSRAMs and LSRAMs

• LSRAMs cannot be accessed when the system controller is accessing them

BUSYThis signal acts as a Status signal when the system controller is accessing the particular LSRAM. Logic 1on this signal indicates system controller access. This signal can be used to monitor the completion ofLSRAM access.

Memory ModesLSRAM can be configured as a dual-port SRAM or two-port SRAM.

Dual-Port ModeLSRAM configured as dual-port SRAM provides a data storage capability of 18 Kbits with twoindependent access ports: Port A and Port B (Figure 2-2 on page 28). Read and write operations can bedone from both the ports independently at any location as long as there is no collision.

In Dual-port mode, the maximum data width can be x18 for either port. In Dual-port mode, each port ofthe LSRAM can be configured in the following depth x width configurations:

• 1k x 18, 1k x 16

• 2k x 9, 2k x 8

• 4k x 4

• 8k x 2

• 16k x 1

Revision 4 27

LSRAM

Figure 2-2 shows the data path for the dual-port SRAM (DPSRAM).

Data can be written to either or both ports and also can be read from either or both ports. Each port hasits own address, data in, data out, clock, block select, and write enable. The read and write operationsare synchronous and require a clock edge.

There is no collision detection or prevention circuit built into LSRAM. Simultaneous write operations fromboth the ports to the same address location result in data uncertainty. Simultaneous read and writeoperations from both the ports to the same address location results in correct data written into thememory but garbage values being read out.

The read operation requires one clock cycle in Non-pipelined mode. In Pipelined mode, the output dataappears in the next cycle. The write operation requires one clock cycle.

When the read operation is configured with output pipeline registers, the input clock sourcing the pipelineregisters has to be synchronized to the LSRAM's clock input; that is, A_DOUT_CLK should besynchronized to A_CLK and B_DOUT_CLK should be synchronized to B_CLK.

Table 2-9 shows the data width configurations that are supported by LSRAM configured in Dual-portmode.

Figure 2-2 • Data Path for Dual-Port Mode

DATA In A DATA In B

DATA Out A DATA Out B

PORT A PORT B

Pipeline Register A

Pipeline Register B

18 18

18 18

A_DIN B_DIN

B_DOUTA_DOUT

Port A Signals

Port B Signals

Table 2-9 • Data Width Configurations for LSRAM in Dual-Port Mode

Port A Data Width (represented as “x number of bits”) Port B Data Width (represented as “x number of bits”)

x1 x1, x2, x4, x8, x16

x2 x1, x2, x4, x8, x16

x4 x1, x2, x4, x8, x16

x8 x1, x2, x4, x8, x16

x16 x1, x2, x4, x8, x16

28 Revision 4


Two-Port ModeLSRAM configured as two-port SRAM provides a data storage capability of 18 Kbits, with Port Adedicated to read operations and Port B dedicated to write operations (Figure 2-3). In Two-port mode,the maximum data width for the read port (Port A) and the write port (Port B) is x36.

x9 x9, x18

x18 x9, x18

Table 2-9 • Data Width Configurations for LSRAM in Dual-Port Mode (continued)

Port A Data Width (represented as “x number of bits”) Port B Data Width (represented as “x number of bits”)

Figure 2-3 • Data Path for Two-Port Mode

DATA In A DATA In B

DATA Out A DATA Out B

PORT A

PORT B

Pipeline Register A

Pipeline Register B

18 18

18 18

A_DIN B_DIN

B_DOUTA_DOUT

Port A Signals

Port B Signals

Revision 4 29

LSRAM

In Two-port mode, LSRAM can be configured in the following depth x width configurations:

• 512 x 36

• 512 x 32

• 1k x 18, 1k x 16

• 2k x 9, 2k x 8

• 4k x 4

• 8k x 2

• 16k x 1

There is no collision detection or prevention circuit built into LSRAM. Simultaneous read operations fromPort A and write operations from Port B for the same address location should be avoided. This situationresults in correct values being written into the memory, but garbage values will be read out from thememory.

When the read port data width is configured as x36/x32:

• Output data pins are borrowed from Port B, with Port A forming the MSB and Port B forming theLSB.

• Input data pins are borrowed from Port A, with Port A forming the MSB and Port B forming theLSB.

The read operation requires one clock cycle in Non-pipelined mode. In Pipelined mode, the output dataappears in the next cycle. The write operation requires one clock cycle.

When the read operation is configured with output pipeline registers, the input clock sourcing the pipelineregisters has to be synchronized to the LSRAM's clock input. When the read data width is x18 or less,A_DOUT_CLK has to be synchronized to A_CLK. When the read data width is x36/x32, bothA_DOUT_CLK and B_DOUT_CLK have to be synchronized to A_CLK.

Table 2-10 shows the data width configurations supported by LSRAM configured in Two-port mode.

Table 2-10 • Data Width Configurations for LSRAM in Two-Port Mode

Read Port – Port A (represented as “x number of bits”) Write Port – Port B (represented as “x number of bits”)

x1 x1, x2, x4, x8, x16

x2 x1, x2, x4, x8, x16

x4 x1, x2, x4, x8, x16

x8 x1, x2, x4, x8, x16

x9 x9, x18

x16 x1, x2, x4, x8, x16

x18 x9, x18

x32 x1, x2, x4, x8, x16, x32

x36 x9, x18, x36

Note: In Two-port mode, if the write data width is x36/x32 and read data width is x36/x32, both the bits of A_WEN andB_WEN have to be tied to logic 1 and should not be dynamically changed.

30 Revision 4


Operating Modes

Read Operation

Flow-Through ReadFlow-through mode indicates a non-pipelined read operation where the pipeline registers are bypassed and the data is displayed on the corresponding output in the same clock cycle. During flow-through read operation, the LSRAM can generate glitches on the data output buses. Therefore, Microsemi recommends using LSRAM with pipeline registers to avoid these read glitches.

Pipelined ReadIn a pipelined read operation, the output data is registered at the pipeline registers, so the data is displayed on the corresponding output in the next clock cycle. In Pipeline mode, pipeline clock input and LSRAM's clock input should be synchronized and fed with a single clock source.

Timing Diagram: Flow-Through Read and Pipeline Read• The addresses (A_ADDR, B_ADDR), BLK enables (A_BLK, B_BLK), and read enables (A_WEN,

B_WEN = 0) should be set up before the rising edge of the clock (A_CLK, B_CLK).

• For non-pipeline read operations, data comes on the output bus (A_DOUT, B_DOUT) after adelay of tCLK2Q (read access time without pipeline register) in the same cycle.

• For pipeline read operations, the data is displayed on the output in the next clock cycle.

Revision 4 31

LSRAM

Figure 2-4 shows the timing diagram for a read operation performed on LSRAM.

Figure 2-4 • Read Operation Timing Waveforms

t t

t t

t t

t

t t

t

A_CLKB_CLK

A_ADDR [13:0]B_ADDR [13:0]

A_BLK [2:0]B_BLK [2:0]

A_WENB_WEN

A_DOUT [17:0] (Non-Pipeline Read)B_DOUT [17:0] (Non-Pipeline Read)

A_DOUT_CLKB_DOUT_CLK

A_DOUT_ENB_DOUT_EN

t

t t

t t t t

t

A_DOUT [17:0] (Pipeline Read)B_DOUT [17:0] (Pipeline Read)

CY

CLCH

ADDRSU ADDRHD

BLKHDBLKSU

RDEHDRDESU

CLK2Q

PLCY

PLCLKMPWH PLCLKMPWL

RDPLESU RDPLEHDRDPLEHDRDPLESU

CLK2Q

Table 2-11 • Read Operation Timing Parameters

Parameters Description

tCY Clock period

tCH Clock minimum pulse width High

tCL Clock minimum pulse width Low

tADDRSU Address setup time

tADDRHD Address hold time

tBLKSU Block select setup time (With pipeline register enabled)

tBLKHD Block select hold time (With pipeline register enabled)

tRDESU Read enable setup time (A_WEN, B_WEN =0)

tRDEHD Read enable hold time (A_WEN, B_WEN =0)

tCLK2Q Read access time with pipeline register

Read access time without pipeline register

32 Revision 4


Write Operation

Feed-Through Write (write-bypass write)During this write operation, the data written into the memory array is displayed immediately on the corresponding data output for non-pipeline operation. For pipeline operation data output displays in next clock. The feed-through write option is not supported when the LSRAM is configured in Two-port mode.

Simple WriteIn simple write, the data written into the memory array is not displayed on the corresponding data output until it is read out. The data output retains the last read data value.

Timing Diagram: Feed-Through Write and Simple Write• The addresses (A_ADDR, B_ADDR), BLK enables (A_BLK, B_BLK), and write enables (A_WEN,

B_WEN = 1) should be set up before the rising edge of the clock (A_CLK, B_CLK).

• For a feed-through write, the written data is displayed on the output (A_DOUT, B_DOUT) after adelay of tCLK2Q in the same clock cycle.

• For a simple write, the written data is displayed on the output only when a read operation isperformed on the same address.

Figure 2-5 on page 34 shows the timing diagram for a write operation performed on LSRAM.

tPLCY Pipelined clock period

tPLCLKMPWH Pipelined clock minimum pulse width High

tPLCLKMPWHL Pipelined clock minimum pulse width Low

tRDPLESU Pipelined read enable setup time (A_DOUT_EN, B_DOUT_EN)

tRDPLEHD Pipelined read enable hold time (A_DOUT_EN, B_DOUT_EN)

Table 2-11 • Read Operation Timing Parameters (continued)


Revision 4 33

LSRAM

Figure 2-5 • Write Operation Timing Waveforms

t t

t t

t t

t

t t

t

A_CLKB_CLK

A_AADR [13:0]B_AADR [13:0]

A_BLK [2:0]B_BLK [2:0]

A_WENB_WEN

A_DOUT [17:0] (Feed Through)B_DOUT [17:0] (Feed Through)

t t

A_DIN [17:0]

B_DIN [17:0]

CY

CH CL

ADDRSU ADDRHD

BLKHDBLKSU

WEHDWESU

DHDDSU

CLK2Q

Table 2-12 • Write Operation Timing Parameters


tCY Clock period



tADDRSU Address setup time

tADDRHD Address hold time

tBLKSU Block select setup time (with pipeline register enabled)

tBLKHD Block select hold time (with pipeline register enabled)

tWESU Write enable setup time (A_WEN, B_WEN = 1)

tWEHD Write enable hold time (A_WEN, B_WEN = 1)

tDSU Data setup time

tDHD Data setup time

tCLK2Q Read access time with Feed-through write timing

34 Revision 4


Reset OperationThe reset signals (A_ARST_N and B_ARST_N) are asynchronous Active Low signals. For any normaloperation of LSRAM, these reset signals should be kept High. To reset the LSRAM, the reset signalsmust be Low.

When reset is asserted (A_ARST_N or B_ARST_N forced Low), the LSRAM behaves as follows duringread and write operations:

1. Read operation: If reset is asserted when the read operation is in process, the data output port isforced Low after a certain amount of delay. If the clock is High and the reset signal is asserted andthen deasserted in the same High clock phase or Low clock phase, the data output stays Lowuntil the next cycle. The data output changes its state only if a read operation or write operation inBypass mode is performed on the LSRAM. In a simple write operation, the data output stays Low.

2. Write operation: The corrupted data is written into the memory. Therefore, Microsemirecommends to avoid asserting reset during write operation.

Timing Diagram: Asynchronous Reset Operation

Block Select OperationThe block select in LSRAM works like a chip select. When the block select (A_BLK and B_BLK) is High,the LSRAM is active and read and write operations can be performed.

If the block select is Low, the LSRAM does not perform any read or write operations. It drives logic 0 onthe data output pins until the next read cycle or write operation in Bypass mode. When the pipelineregisters are used, the block select effect at the output is delayed by one pipeline clock cycle (thepipeline registers are independent of block select).

Figure 2-7 on page 36 shows the timing diagram for block select inputs for LSRAM.

Figure 2-6 • Timing Diagram for Asynchronous Reset Operation

tt t

A_CLKB_CLK

A_ARST_NB_ARST_N

A_DOUTB_DOUT

t

CY

CLCH

R2Q

Table 2-13 • Asynchronous Reset Timing Parameters


tCY Clock period



tR2Q Asynchronous reset to output propagation delay

Revision 4 35

LSRAM

Figure 2-6 on page 35 shows the timing diagram for asynchronous reset operation performed on LSRAM.

Figure 2-7 • Block Select Timings

t

A_CLKB_CLK

A_BLK [2:0]B_BLK [2:0]

t t

A_DOUT [17:0] (Non-Pipeline Mode)B_DOUT [17:0] (Non-Pipeline Mode)

t

A_DOUT [17:0] (Pipeline Access)B_DOUT [17:0] (Pipeline Access)

t

t

CY

BLKMPW

BLKHDBLKSU

BLK2Q

CLK2Q

Table 2-14 • Block Selection Timing Parameters


tCY Clock period



tBLKSU Block select setup time (with pipeline register enabled)

tBLKHD Block select hold time (with pipeline register enabled)

tBLKMPW Block select minimum pulse width

tBLK2Q Block select to out disable time (when pipeline registers are disabled)

tCLK2Q Read access time without pipeline register

36 Revision 4


CollisionCollision scenarios arise between both ports of the LSRAM when a read operation is requested from oneport and a write operation from the other port simultaneously on the same address location, or when awrite operation occurs at the same location at the same time from both the ports. Table 2-15 describesthe behavior of the LSRAM during the various cases of collisions.

There are no collision prevention or detection techniques available in LSRAM. The last 3 scenarios mentioned in Table 2-15 are not allowed on LSRAM and should be avoided.

How to Use LSRAMThe following sections describe how to use LSRAM in an application:

• Design Flow

• LSRAM Use Model

Design FlowLibero SoC software provides separate configuration tools for Dual-port mode and Two-port mode. Usingthese configuration tools, LSRAM blocks can be configured in the required operating modes. Theseconfiguration tools generate the required HDL wrapper files for LSRAM with appropriate values assignedto the static signals. The generated LSRAM wrapper HDL files can be used in the design hierarchy byconnecting the ports to the rest of the design.

LSRAM Dual-Port ModeFigure 2-8 on page 38 shows the ports of the DPSRAM IP macro available in Libero SoC. Refer to theSmartFusion2 Dual-Port Large SRAM Configuration for detailed software configuration information ondual-port LSRAM.

Table 2-15 • Collision Operation Description

Operation Description

Simultaneous read from Port A and Port B atthe same location

Operation is allowed without any restrictions and data is available onthe output ports after the specified time, as described in the readtiming diagrams in Figure 2-4 on page 32.

Simultaneous read from Port A and write fromPort B at the same location

Not allowed. The new data may be written into the address locationbut the read data out will be a garbage value.

Simultaneous read from Port B and write fromPort A at the same location

Not allowed. The new data may be written into the address locationbut the read data out will be a garbage value.

Simultaneous write from Port A and Port B atthe same location

Not allowed. If the data to be written is same on both the ports, thendata is successfully written. If the data is different, then the LSRAMcell has an undetermined state.

Revision 4 37

LSRAM

LSRAM Two-Port ModeFigure 2-9 shows the ports of the TPSRAM IP macro available in Libero SoC. Refer to the SmartFusion2Two-Port Large SRAM Configuration document for detailed software configuration information for two-port LSRAM.

Figure 2-8 • Ports of the LSRAM Configured as Dual-Port SRAM - DPSRAM Macro in Libero SoC

Table 2-16 • Port Description for the DPSRAM Macro

Port Name Direction Description

A_CLK, B_CLK Input These signals represent the clock inputs for Port A and Port B. The same clockinputs also act as clock inputs for the output pipeline registers if configured asregisters. You must set up all inputs before the rising edge of the clock. The reador write operation begins with the rising edge.

A_ADDR, B_ADDR Input These signals represent the address inputs for Port A and Port B.

A_BLK, B_BLK Input These signals represent the block-select inputs for Port A and Port B.

A_DIN, B_DIN Input These signals represent the data inputs for Port A and Port B.

A_WEN, B_WEN Input These signals represent the write enables for Port A and Port B.

A_DOUT, B_DOUT Output These signals represent the data outputs for Port A and Port B.

A_DOUT_EN, B_DOUT_EN

Input These signals represent the Read data register Enable for Port A and Port B.

A_DOUT_SRST_N, B_DOUT_SRST_N

Input These signals represent the Read data register Synchronous reset for Port Aand Port B.

A_DOUT_ARST_N, B_DOUT_ARST_N

Input These signals represent the Read data register Asynchronous reset for Port Aand Port B.

38 Revision 4


Figure 2-9 • Ports of the LSRAM Configured as Two-Port SRAM - TPSRAM Macro in Libero SoC

Table 2-17 • Port Description for the TPSRAM Macro


WCLK Input This signal represents the clock input for the write port (Port B). You must set up all writeinputs before the rising edge of the clock. The write operation begins with the rising edge.

RCLK Input This signal represents the clock input for the read port (Port A). The same clock inputsalso act as clock inputs for the output pipeline registers if configured as registers. Youmust set up all read inputs before the rising edge of the clock. The read operation beginswith the rising edge.

ARST_N Input This signal represents Active Low, asynchronous reset inputs for Port A and Port B.Assertion of this reset during a read operation forces the data output lines to logic '0'.Assertion of these resets during a write operation results in garbage values written intothe memory.

WADDR Input This signal represents the address input for write Port B.

RADDR Input This signal represents the address input for read Port A.

WEN Input This signal represents the write enable for write Port B.

WD Input This signal represents the data input for write Port B.

REN Input This signal represents the read enable for read Port A.

RD Output This signal represents the data output for read Port A.

RD_EN Input This signal represents the Read data register enable.

RD_SRST_N Input This signal represents the Read data register Synchronous reset.

Revision 4 39

LSRAM

LSRAM Macro (RAM 1Kx18)Libero SoC can be used to instantiate the LSRAM macro (RAM1Kx18) in the design. When using theRAM1Kx18 macro, care should be taken to provide appropriate values to the static signals to configurethe LSRAM correctly before instantiating it in the design.

Figure 2-10 shows the LSRAM macro RAM1Kx18 available in Libero SoC.

Associated LSRAM IP CoresIn addition to LSRAM macros, Libero SoC also has IP cores available to access the LSRAM throughAHB and APB slave interfaces through which configuration parameters such as bus (AHB/APB) datawidth, RAM selection (LSRAM, uSRAM), and depth of the memory can be set. Figure 2-11 on page 41and Figure 2-12 on page 41 show CoreAHBLSRAM and CoreAPBLSRAM, available in the Libero SoCcatalog.

Figure 2-10 • RAM1Kx18 Macro

40 Revision 4


CoreAHBLSRAMFigure 2-11 shows CoreAHBLSRAM IP (LSRAM with AHB slave Interface), available in Libero SoC.Refer to the CoreAHBLSRAM Handbook for detailed software configuration information for Dual portLSRAM.

CoreAPBLSRAMFigure 2-12 shows CoreAPBLSRAM IP (LSRAM with APB slave interface), available in Libero SoC.Refer to the CoreAPBLSRAM Handbook for detailed software configuration information.

Figure 2-11 • CoreAHBLSRAM IP in Libero SoC

Table 2-18 • Port Description for the CoreAHBLSRAM IP


HCLK Input AHB clock. All AHB signals inside the block are clocked on the rising edge.

HRESETn Input AHB Reset. The signal is Active Low. Asynchronous assertion and synchronousdeassertion. Used to reset AHB registers in the block.

S Input/Output AHB slave interface signals include:

HSEL: AHBL slave select

HADDR: AHBL address

HWRITE: AHBL write

HREADYIN: AHBL ready input

Figure 2-12 • CoreAPBLSRAM IP in Libero SoC

Revision 4 41

LSRAM

CoreFIFO IPLibero SoC IP catalog has a CoreFIFO IP, which can be configured as a soft FIFO for generation of FIFO control logic. Memory configuration can be selected as LSRAM, uSRAM, or external memory as per the design requirements. Refer to the CoreFIFO Handbook for detailed software configuration information.

LSRAM Use Model

Use Model 1: Two-port SRAM with a Write Data Width of x36 and Read Data Width of x18LSRAM does not support any two-port configurations with a write port (Port B) data width of x36/x32 anda read port (Port B) data width of x18/x9/x8/x4/x2/x1. If such a configuration is required for the design,two LSRAM blocks must be used to implement these configurations.

Following use model explains how to implement a two-port SRAM (using RAM1kx18 macros) with a writedata width of x36 and a read data width of x18.

The implementation has the following configurations:

• Write port: 512 x 36

• Read port: 1024 x 18

• Read and write input clock: Two different clock sources

• Pipelined read mode: Disabled

Table 2-19 • Port Description for the CoreAPBLSRAM IP


PCLK Input APB clock. All APB signals inside the block are clocked on the rising edge.

PRESETn Input APB Active Low asynchronous reset.

S Input/Output APB Slave interface signals include:

PSEL: APB slave select

PADDR: APB Address

PWDATA: APB write data

PRDATA: APB read data

PENABLE: APB strobe. Indicates the second cycle of an APB transfer.

PWRITE: APB write

PREADY: APB3 ready signal for future APB3 compliance. Used to extend APB transfer.

PSLVERR: APB slave error. Indicates transfer failure. It is tied to Low.

42 Revision 4


Figure 2-13 shows the two-port SRAM with a write data width of x36 and read data width of x18.

The above implementation can be configured automatically using two-port LSRAM (TPSRAM) macroavailable in Libero SoC. Table 2-19 on page 42 shows the TPSRAM data width configurations thatrequire two LSRAM blocks.

Figure 2-13 • Two-Port SRAM With W36 and R18

A_CLKA_ARST_NA_BLK[2:0]A_ADDR[13:0]A_DIN[17:0]A_WEN[1:0]A_DOUT_ENA_DOUT_ARST_NA_DOUT_SRST_N

B_CLKB_ARST_NB_BLK[2:0]B_ADDR[13:0]B_DIN[17:0]B_WEN[1:0]B_DOUT_ENB_DOUT_ARST_NB_DOUT_SRST_N

A_DOUT_LATA_WIDTH[2:0]A_WMODEA_EN

B_DOUT_LATB_WIDTH[2:0]B_WMODEB_ENS_LOCK

A_DOUT[17:0]

B_DOUT[17:0]

BUSY

A_CLKA_ARST_NA_BLK[2:0]A_ADDR[13:0]A_DIN[17:0]A_WEN[1:0]A_DOUT_ENA_DOUT_ARST_NA_DOUT_SRST_N

B_CLKB_ARST_NB_BLK[2:0]B_ADDR[13:0]B_DIN[17:0]B_WEN[1:0]B_DOUT_ENB_DOUT_ARST_NB_DOUT_SRST_N

A_DOUT_LATA_WIDTH[2:0]A_WMODEA_EN

B_DOUT_LATB_WIDTH[2:0]B_WMODEB_EN

S_LOCK

A_DOUT[17:0]

B_DOUT[17:0]

BUSY

LSRAM #1

LSRAM #2

RCLK‘1’

REN,’1',’1'‘0’,RADDR[9:0],‘0’,’0',’0'

18'b0“00”

‘1’ARST_N

‘1’

WCLK

A_DOUT_CLK‘1’

B_DOUT_CLK

A_DOUT_CLK‘1’

B_DOUT_CLK

‘1’WEN,’1',’1'

‘0’,WADDR[8:0],’0',‘0’,’0',’0'WD[26:19], WD[8:0]

3

14

3

14

“11”18‘1’‘0’‘1’‘1’

‘1’“011”

‘0’‘1’

‘1’“100”

‘0’‘1’‘0’

‘1’

18'b0“00”

‘1’

‘1’

‘1’

WD[35:27], WD[17:9]“11”

‘1’‘0’‘1’‘1’

‘1’“011”

‘0’‘1’

‘1’“100”

‘0’‘1’

‘0’

RD[17:9]

Not Connected

Not Connected

RD[8:0]

Not Connected

Not Connected

Revision 4 43

LSRAM

Glossary

Acronyms

LSBLeast significant bit


MSBMost significant bit


Terminology

Flow-through ReadA read operation performed with the output not being registered by the output pipeline registers.

Pipelined ReadA read operation performed with the output being registered by the output pipeline registers.

Simple WriteA write operation in which the data written does not appear on the SRAM output ports.

Feed-through Write (Write-Bypass Write)A write operation in which the data written appears on the SRAM output ports immediately for non-pipeline mode and next clock cycle for pipeline mode.

Dual-Port ModeSRAM with two independent ports through which both read and write operation can be done.

Two-Port ModeSRAM with two ports, one dedicated to read operations and the other dedicated to write operations.

Table 2-20 • Two-Port Configurations Requiring Two LSRAM Blocks

Write Data Width Read Data width

x36 x18

x32 x16

x36 x9

x32 x8

x32 x4

x32 x2

x32 x1

44 Revision 4


List of ChangesThe following table lists critical changes that were made in each revision.

Date Changes Page


Table 2-1 • Number of LSRAM 18K Blocks Available per Device is modified (SAR 47579).

20

Figure 2-12 • CoreAPBLSRAM IP in Libero SoC is updated (SAR 47619). 41


Restructured the chapter (SAR 45272). NA

Revision 1(October 2012)

Added new Figure 2-4, Figure 2-5, and Figure 2-7 32, 34, and 36

Updated Table 2-12, Table 2-13, and Table 2-14 34, 35, and 36

Revision 4 45

3 – Micro SRAM (uSRAM)

IntroductionThe SmartFusion2 SoC FPGA fabric has embedded 1 Kbit micro SRAM (uSRAM) blocks used for storingdata. These uSRAMs are arranged in multiple rows within the FPGA fabric can be accessed through thefabric routing architecture. The number of uSRAM blocks available varies among SmartFusion2 devices,as shown in Table 3-2 on page 49. For example, in the M2S050 device there are 72 uSRAM blocksavailable, spread across three rows inside the fabric.

FeaturesSmartFusion2 uSRAM blocks have the following features:

• Each uSRAM block stores up to 1 Kbits (1,152 bits) of data and can be configured in any of thefollowing depth × width combinations: 64 × 18, 64 × 16, 128 × 9, 128 × 8, 256 × 4, 512 × 2 and1,024 × 1.

• Each uSRAM has 2 read data ports (Port A and Port B) and 1 write data port (Port C).

• Read operations can be performed in both Synchronous and Asynchronous modes. The writeoperation is always synchronous.

• The 2 read ports have address/block select registers for enabling Synchronous mode operation.These registers can also be configured as transparent latches for Asynchronous modeoperations.

• In Pipelined mode, the 2 read ports have output registers with independent clocks. These Outputpipeline registers can also be configured as transparent latches for Asynchronous modeoperation.

• Due to the availability of separate input address and output pipeline registers, read operationsthrough Port A and Port B in uSRAM can be performed in 6 different modes:

– Synchronous read mode without pipeline registers (Synchronous-Asynchronous mode)

– Synchronous read mode with pipeline registers (Synchronous-Synchronous mode)

– Asynchronous read mode without pipeline registers (Asynchronous-Asynchronous mode)

– Asynchronous read mode with pipeline registers (Asynchronous-Synchronous mode)

– Synchronous read mode with pipeline registers configured as latches

– Asynchronous read mode with pipeline registers configured as latches

• Separate synchronous and asynchronous resets are provided for the input address/block selectregisters. These resets can be used to initialize the read ports.

• The output pipeline registers have separate synchronous and asynchronous resets which provideindependent control to these registers.

• uSRAM can operate up to 400 MHz in Synchronous-Synchronous read mode through Port A andPort B, including a write operation at 400 MHz through Port C.

• The two read ports are independent of each other and simultaneous read operations can beperformed from both ports at the same address location.

• Simultaneous read and write operations at the same location are not allowed.

Revision 4 47

Micro SRAM (uSRAM)

uSRAM Resource TableTable 3-1 lists uSRAM blocks available for SmartFusion2 devices.

Functional DescriptionThe following sections provide the detailed description of the following:

• Architecture Overview

• Port List

• Port Description

Architecture OverviewSmartFusion2 uSRAM embedded memory includes the RAM64X18 macro, available in Libero SoCsoftware. Figure 3-1 shows a simplified block diagram of the uSRAM memory block with two read dataports, one write data port and pipeline registers at read port. Table 3-2 on page 49 provides the portdescriptions.

Table 3-1 • SmartFusion2 uSRAM (1Kb Blocks) Resource

Device Number of uSRAM

SmartFusion2 Rows Number per Row Total

M2S005 1 11 11

M2S010 2 11 22

M2S025 2 17 34

M2S050 3 24 72

M2S090 4 28 112

M2S100 4 40 160

M2S150 6 40 240

48 Revision 4


Port List

Figure 3-1 • Simplified Functional Block Diagram of uSRAM

A_DOUT[17:0]Port ARead

Decode

Port BRead

Decode

B_DOUT_CLK

A_DOUT_CLK

B_DOUT[17:0]

Memory Array

64 x 18

C_ADDR[9:0]

C_DIN[17:0]

C_WEN

C_CLK

Port

CW

rite

Cont

rol

A_ADDR[9:0]A_BLK [1:0]

A_ADDR_CLK

B_ADDR[9:0]B_BLK [1:0]

B_ADDR_CLK

Pipeline Registers

A_ADDR_LAT

B_ADDR_LAT

A_DOUT_LAT

B_DOUT_LAT

Table 3-2 • Port List for uSRAM

Port Name Direction Type* Descriptions Polarity

Port A

A_ADDR[9:0] Input Dynamic Address input –

A_BLK[1:0] Input Dynamic Block select Active High

A_WIDTH[2:0] Input Static Depth x width mode selection –

A_DOUT[17:0] Output Dynamic Data output –

A_DOUT_ARST_N Input Dynamic Pipeline register asynchronous reset Active Low

A_DOUT_CLK Input Dynamic Pipeline register clock input Rising

A_DOUT_EN Input Dynamic Pipeline register enable Active High

A_DOUT_LAT Input Static Pipeline Latch mode input Active High

A_DOUT_SRST_N Input Dynamic Pipeline register synchronous reset Active Low

A_ADDR_CLK Input Dynamic Address register clock Rising

Note: *Static inputs are defined at design time and are controlled by flash configuration bits.

Revision 4 49

Micro SRAM (uSRAM)

A_ADDR_EN Input Dynamic Address register enable Active High

A_ADDR_LAT Input Static Address register Latch mode input Active High

A_ADDR_SRST_N Input Dynamic Address register synchronous reset Active Low

A_ADDR_ARST_N Input Dynamic Address register asynchronous reset Active Low

Port B

B_ADDR[9:0] Input Dynamic Address input

B_BLK[1:0] Input Dynamic Block select Active High

B_WIDTH[2:0] Input Static Depth x width mode selection –

B_DOUT[17:0] Output Dynamic Data output –

B_DOUT_ARST_N Input Dynamic Pipeline register Asynchronous reset Active Low

B_DOUT_CLK Input Dynamic Pipeline register clock input Rising

B_DOUT_EN Input Dynamic Pipeline register enable Active High

B_DOUT_LAT Input Static Pipeline Latch mode input Active High

B_DOUT_SRST_N Input Dynamic Pipeline register synchronous reset Active Low

B_ADDR_CLK Input Dynamic Address register clock Rising

B_ADDR_EN Input Dynamic Address register enable Active High

B_ADDR_LAT Input Static Address register Latch mode input Active High

B_ADDR_SRST_N Input Dynamic Address register synchronous reset Active Low

B_ADDR_ARST_N Input Dynamic Address register asynchronous reset Active Low

Port C

C_ADDR[9:0] Input Dynamic Address input –

C_BLK[1:0] Input Dynamic Block select Active High

C_WIDTH[2:0] Input Static Depth x width mode selection –

C_DIN[17:0] Output Dynamic Data output

C_CLK Input Dynamic Clock input Rising

C_WEN Input Dynamic Write enable Active High

Common Signals

A_EN Input Static Port A power-down Low

B_EN Input Static Port B power-down Low

C_EN Input Static Port C power-down Low

SII_LOCK Input Static Lock access to SII High

Busy Output Dynamic Busy signal while SII access High

Table 3-2 • Port List for uSRAM (continued)

Port Name Direction Type* Descriptions Polarity

Note: *Static inputs are defined at design time and are controlled by flash configuration bits.

50 Revision 4


Port Description

A_WIDTH[2:0], B_WIDTH [2:0], and C_WIDTH [2:0]These signals represent the depth x width mode selections for each port. Table 3-3 shows the depth xwidth based on ports width selection.

A_ADDR[9:0], B_ADDR [9:0], and C_ADDR [9:0]These signals represent the address buses for the three ports (two read and one write). In ×1 mode, 10bits are used to address the 1,152 independent locations. In wider modes such as ×2 and ×4, feweraddress bits are used. The used address bits are the most significant bits (MSB). The unused bits are theleast significant bits (LSBs) and they must be grounded. Table 3-4 shows the address bus used andunused bits for depth × width selections.

Table 3-3 • Width/Depth Mode Selection

A_WIDTH / B_WIDTH / C_WIDTH Depth x Width

000 1K x 1

001 512 x 2

010 256 x 4

011128 x 9

128 x 8

100

101

110

111

64 x 18

64 x 16

Table 3-4 • Address Bus Used and Unused Bits

Depth x WidthA_ADDR / B_ADDR / C_ADDR

Used Bits Unused Bits (to be grounded)

1K x 1 [9:0] None

512 x 2 [9:1] [0]

256 x 4 [9:2] [1:0]

128 x 9

128 x 8[9:3] [2:0]

64 x 18

64 x 16[9:4] [3:0]

Revision 4 51

Micro SRAM (uSRAM)

C_DIN[17:0]This signal represents the data input bus for the write Port C. The used bits for any mode are LSBjustified in the data bus and the unused MSB bits must be grounded. Table 3-5 shows the data input busused and unused bits for depth × width selections.

A_DOUT[17:0] and B_DOUT[17:0]These signals represent the data output buses for the two ports (Port A and Port B). The used bits for anymode are LSB justified in the data bus and the unused MSB bits must be grounded. Table 3-6 shows thedata output bus used and unused bits for different depth x width selections.

Table 3-5 • Data Input Buses Used and Unused Bits

Depth x WidthC_DIN

Used Bits Unused Bits (to be grounded)

1K x 1 [0] [17:1]

512 x 2 [1:0] [17:2]

256 x 4 [3:0] [17:4]

128 x 8 [7:0] [17:8]

128 x 9 [8:0] [17:9]

64 x 16[16:9]

[7:0]

[17]

[8]

64 x 18 [17:0] None

Table 3-6 • Data Output Buses Used and Unused Bits

Depth x WidthA_DOUT/B_DOUT

Used Bits Unused Bits

1K x 1 [0] [17:1]

512 x 2 [1:0] [17:2]

256 x 4 [3:0] [17:4]

128 x 8 [7:0] [17:8]

128 x 9 [8:0] [17:9]

64 x 16[16:9]

[7:0]

[17]

[8]

64 x 18 [17:0] None

52 Revision 4


A_BLK[1:0], B_BLK [1:0], and C_BLK [1:0]These signals represent the port select control signal for each port. Table 3-7 shows the operations(Read, write and no operation) based on selection of port select control signals.

C_CLKThis signal represents the clock signal for Port C. Ensure all inputs are set up before the first rising clockedge. The write operation starts at the rising edge of this clock signal.

C_WENThis signal represents the write enable for Port C.

A_ADDR_CLK and B_ADDR_CLKThese signals represent the clock inputs for the input address/block select registers for Port A and PortB. In Synchronous read mode, set up the address and block select inputs before the rising edge of theseclocks. In Asynchronous mode, tie these clocks to logic 1.

A_DOUT_CLK and B_DOUT_CLKThese signals represent the clock inputs for the output pipeline registers for Port A and Port B. InPipelined mode, the output data appears in the next clock cycle. In Latch mode operation, the outputdata appears in the same clock cycle. When the registers are configured as transparent, tie these inputsto logic 1.

A_ADDR_LAT and B_ADDR_LATThese signals represent Latch mode inputs for the input address/block select registers for Port A andPort B.


• Logic 1: Transparent operation

A_DOUT_LAT and B_DOUT_LATThese signals represent Latch mode inputs for the output pipeline registers for Port A and Port B.


• Logic 1: Latch/Transparent operation

A_ADDR_ARST_N and B_ADDR_ARST_NThese signals represent Active Low, asynchronous reset inputs for the input address/block selectregisters for Port A and Port B.

Table 3-7 • Port Select Control Signals

Port Select Signal Value Operation

A_BLK[1:0]

11 Perform read operation on Port A.

00

01

10

Port A is not selected and its read data will be logic 0.

B_BLK[1:0]

11 Perform read operation on Port B.

00

01

10

Port B is not selected and its read data will be logic 0.

C_BLK[1:0]

11 Perform write operation on Port C.

00

01

10

Port C is not selected.

Revision 4 53

Micro SRAM (uSRAM)

The assertion of these reset signals forces the address and block select input registers to logic 0, whichin turn forces the data output to logic 0. When these registers are configured as transparent, tie theseinputs to logic 1.

A_DOUT_ARST_N and B_DOUT_ARST_NThese signals represent Active Low, asynchronous reset inputs for the output pipeline registers for Port Aand Port B. Assertion of these reset signals forces the data output to logic 0. When these registers areconfigured as transparent, tie these inputs to logic 1.

A_ADDR_SRST_N and B_ADDR_SRST_NThese signals represent Active Low, synchronous reset inputs for the input address/block select registersfor Port A and Port B. The assertions of these reset signals forces the address input registers and blockselect registers to logic 0, which in turn forces the data output to logic 0. When the registers areconfigured as transparent, these inputs should be tied to logic 1.

A_DOUT_SRST_N and B_DOUT_SRST_NThese signals represent Active Low, synchronous reset inputs for the output pipeline registers for Port Aand Port B. Assertion of these reset signals forces the data output to logic 0. In non-pipelined mode ofoperation, tie these inputs to logic 1.

A_ADDR_EN and B_ADDR_ENThese signals represent Active High enable inputs for the input address/block select registers for Port Aand Port B. When logic 0 is applied on these inputs, the input registers hold the previous input address.When logic 1 is applied on these inputs, the input registers behave as normal D flip-flops. When theregisters are configured as transparent, these inputs should be tied to logic 1.

A_DOUT_EN and B_DOUT_ENThese signals represent Active High enable inputs for the output pipeline registers for Port A and Port B.When logic 0 is applied on these inputs, the pipeline registers hold the previously read data out. In non-pipelined mode, tie these inputs to logic 1.

A_EN, B_EN, and C_ENThese are Active Low, power-down configuration bits for each port.

SII_LOCKThis control signal, when asserted to logic 1, locks the entire uSRAM memory from being accessed bythe system controller interface bus (SII). The system controller can access the uSRAM for the followingreasons:

• Testing the memory

• Moving data between uSRAM and eNVM or external memories

• Moving data between various uSRAMs

• Moving data between uSRAMs and LSRAMs

uSRAMs cannot be accessed while the system controller is accessing them.

BUSYThis signal acts as a status signal when the system controller is accessing a particular uSRAM. Logic 1on this signal indicates system controller access. This signal can be used to monitor the completion ofuSRAM access.

54 Revision 4


Operating Modes

Read OperationuSRAM blocks are read through two ports: Port A and Port B. There are six modes for read operations:

• Synchronous read mode without pipeline registers (Synchronous-Asynchronous mode)

• Synchronous read mode with pipeline registers (Synchronous-Synchronous mode)

• Synchronous read mode with pipeline registers configured as latches

• Asynchronous read mode without pipeline registers (Asynchronous-Asynchronous mode)

• Asynchronous read mode with pipeline registers (Asynchronous-Synchronous mode)

• Asynchronous read mode with pipeline registers configured as latches

Synchronous Read Mode Synchronous read mode requires that the input registers for the address and block select inputs areconfigured in Flip-flop mode (A_ADDR_LAT or B_ADDR_LAT = 0). Similarly, on the output side, thepipeline registers can be configured as registers, latches, or transparent, providing read data asregistered, latched, or asynchronous.

When the pipeline registers are configured as normal registers, the clock inputs of both the input andoutput registers should be synchronous to each other and should be fed with a single clock source. Ifthese registers are configured as a transparent latch, the clock inputs should be tied to High. In Latchmode, both the input and output clocks should be in opposite phase. Microsemi recommends configuringthe pipeline registers, in either the register or Latch mode during read operation to avoid glitches on theread output data lines.

In Synchronous read mode, the address (A_ADDR or B_ADDR) and block-select (A_BLK or B_BLK)inputs must satisfy the setup and hold timings with respect to the input clocks (A_ADDR_CLK orB_ADDR_CLK).

Synchronous Read mode without Pipeline Registers (Synchronous-Asynchronous Read Mode)

• The input registers are configured in Synchronous read mode.

• The output pipeline registers are configured as transparent.

• This mode is achieved by setting A_DOUT_LAT or B_DOUT_LAT = 1, A_DOUT_CLK orB_DOUT_CLK = 1, A_DOUT_ARST_N or B_DOUT_ARST_N = 1, A_DOUT_SRST_N = 1 orB_DOUT_SRST_N = 1, A_DOUT_EN or B_DOUT_EN = 1, A_BLK = 1, B_BLK = 1.

• Figure 3-2 on page 56 shows the synchronous asynchronous operation with data output behavior when block select inputs are deasserted (any bit forced to logic 0).

• The output data is displayed immediately-in the same clock cycle in which the address and blockselect inputs were registered.

• The uSRAM can generate glitches on the output buses when used without the pipeline registers.

Table 3-8 on page 56 describes the timing parameter values for Synchronous read mode without pipelineregisters, with reference to timing waveforms, as shown in Figure 3-2 on page 56.

Revision 4 55

Micro SRAM (uSRAM)

Synchronous Read Mode with Pipeline Registers (Synchronous-Synchronous Read Mode)

• The input registers are configured in Synchronous read mode.

• The output pipeline registers are configured as edge-triggered registers (Pipelined mode).

• Pipelined mode is achieved by setting A_DOUT_LAT or B_DOUT_LAT = 0, A_DOUT_CLK orB_DOUT_CLK = rising edge clock, A_DOUT_ARST_N or B_DOUT_ARST_N = 1,A_DOUT_SRST_N = 1 or B_DOUT_SRST_N = 1, A_DOUT_EN or B_DOUT_EN = 1, A_BLK = 1, B_BLK = 1.

• The input register clock and pipeline register clock must be synchronous to each other; hencethey should be sourced from the same clock input.

• The output data appears on the output bus in the next clock cycle.

Figure 3-2 • Timing Waveforms for Synchronous-Asynchronous Read Operation

tCLKMPWH tCLKMPWL

tCY

tADDRSU tADDRHD

tBLKSU tBLKHD tBLKSU tBLKHD

tBLK2QtCLK2Q

A0

D-1 D0

A1

A_ADDR_CLKB_ADDR_CLK

A_ADDR[9:0]B_ADDR[9:0]

A_BLKB_BLK

A_DOUT[17:0]B_DOUT[17:0]

Table 3-8 • Timing Parameters for Synchronous-Asynchronous Read Operation

Parameter Description

tCY Read clock period

tCLKMPWH Read clock minimum pulse width High time

tCLKMPWL Read clock minimum pulse width Low time

tADDRSU Read address setup time in Synchronous mode

tADDRHD Read address hold time in Synchronous mode

tBLKSU Read block select setup time (when pipeline registers enabled)

tBLKHD Read block select hold time (when pipeline registers enabled)

tCLK2Q Read access time without pipeline registers

tBLK2Q Read block select to out disable/enable time

56 Revision 4


Table 3-9 describes the timing parameter values for Synchronous read mode with pipeline registers.Refer to Figure 3-3 for timing waveforms.

Synchronous Read Mode with Pipeline Registers Configured as Latches• The input registers are configured in Synchronous read mode.

• The output pipeline registers are configured as level-sensitive latches with A_DOUT_CLK orB_DOUT_CLK acting as latch enables.

• The pipeline registers are configured as latches by setting A_DOUT_LAT or B_DOUT_LAT = 1.

• The pipeline latches are enabled by the pipeline register clock (A_DOUT_CLK or B_DOUT_CLK)with opposite phase with respect to the input register clock (A_ADDR_CLK or B_ADDR_CLK).During the low phase of the pipeline clocks, the pipeline latches hold the previous data until thelatch inputs become stable.

Figure 3-3 • Timing Waveforms for Synchronous-Synchronous Read Operation

tCLKMPWH tCLKMPWL

tCY

tADDRSU tADDRHD


tPLCLKMPWH tPLCLKMPWL tPLCY

tCLK2Q tCLK2Q tCLK2Q

A0 A1 A2



A_BLKB_BLK


A_DOUT[17:0]B_DOUT[17:0] D-1 D0D-2

Table 3-9 • Timing Parameters for Synchronous-Synchronous Read Operation









tCLK2Q Read access time with pipeline registers

tPLCY Read pipeline clock period

tPLCLKMPWH Read pipeline clock minimum pulse width High

tPLCLKMPWL Read pipeline clock minimum pulse width Low

Revision 4 57

Micro SRAM (uSRAM)

• In this case, the read access time is related to the negative edge of the address input clock(A_ADDR_CLK or B_ADDR_CLK)-the positive edge of the pipeline clock (A_DOUT_CLK orB_DOUT_CLK).

• This mode is used to moderate the effect of glitches that can appear on the uSRAM's data outputbus when used without the pipeline registers (when uSRAM is configured in Synchronous-Asynchronous read mode).

Table 3-10 describes the timing parameter values for Synchronous read mode with Latched mode. Referto the timing waveforms shown in Figure 3-4.

Asynchronous Read ModeAsynchronous read mode requires that the input registers for the address and block-select inputs areconfigured as transparent (A_ADDR_LAT or B_ADDR_LAT = 1, A_ADDR_CLK or B_ADDR_CLK = 1,A_ADDR_EN or B_ADDR_EN = 1, A_ADDR_ARST_N or B_ADDR_ARST_N = 1, A_ADDR_SRST_N orB_ADDR_SRST_N = 1, A_BLK = 1, B_BLK = 1).

Figure 3-4 • Timing Waveforms for Synchronous Latched Read Operation

tCLKMPWH tCLKMPWL

tCY

tADDRSU tADDRHD


tCLK2Q

tCLPL1

A0

D-1 D0

A1 A2



A_BLKB_BLK



Table 3-10 • Timing Parameters for Synchronous Latched Read Operation









tCLK2Q Read access time with pipeline registers in Latch mode

tCLPL1 Minimum pipeline clock low phase in order to prevent glitches with pipelineregister in Latch mode.

58 Revision 4


Asynchronous Read Mode Without Pipeline Registers (Asynchronous-Asynchronous Mode)

• The input registers are configured in Asynchronous read mode.

• The output pipeline registers are configured as transparent (non-pipelined operation).

• The pipeline registers can be made transparent by setting A_DOUT_LAT or B_DOUT_LAT = 1,A_DOUT_CLK or B_DOUT_CLK = 1, A_DOUT_ARST_N or B_DOUT_ARST_N = 1,A_DOUT_SRST_N = 1 or B_DOUT_SRST_N = 1, A_DOUT_EN or B_DOUT_EN = 1.

• After the input address is provided, the output data is displayed on the output data bus after ata2qr delay (Figure 3-5).

• The uSRAM can generate glitches on the data output bus when used without the pipeline register.

Figure 3-5 shows a timing diagram for Asynchronous-Asynchronous read mode for uSRAM andTable 3-11 gives the description of various timing parameters.

Asynchronous Read Mode with Pipeline Registers (Asynchronous-Synchronous Mode)


• The output pipeline registers are configured as registers (Pipelined mode).

• Pipelined mode is achieved with A_DOUT_LAT or B_DOUT_LAT = 0, A_DOUT_CLK orB_DOUT_CLK = rising edge clock, A_DOUT_ARST_N or B_DOUT_ARST_N = 1,A_DOUT_SRST_N = 1 or B_DOUT_SRST_N = 1, A_DOUT_EN or B_DOUT_EN = 1, A_BLK = 1, B_BLK = 1.

• After the input address is provided, the output data is displayed on the output data bus after thenext rising edge of the pipeline register input clock.

Figure 3-5 • Timing Waveforms for Read Operations with Asynchronous Inputs Without Pipeline Registers

A2

D1D0D-1


A_BLKB_BLK


tBLKMPW

tCLK2Q

tBLK2Q

A1

tBLK2Q

A0

Table 3-11 • Timing Parameters of the Asynchronous Read Mode Without Pipeline Registers



tBLK2Q Read block select to out disable/enable time

tBLKMPW Read block select minimum pulse width

Revision 4 59

Micro SRAM (uSRAM)

Figure 3-6 shows the timing diagrams for Asynchronous-Synchronous read mode for uSRAM andTable 3-12 gives the timing parameters.

Asynchronous Read Mode with Pipeline Registers Configured as Latches


• The output pipeline registers are configured as level-sensitive latches with A_DOUT_CLK orB_DOUT_CLK acting as latch enables.

• The pipeline registers can be configured as latches by setting A_DOUT_LAT or B_DOUT_LAT =1.

• After the input address is provided, the output data is displayed on the output data bus when thenext high level comes on the latch enable inputs-A_DOUT_CLK or B_DOUT CLK.

• This mode is provided to moderate the effect of the glitches which can occur on uSRAM's dataoutput buses when used without the pipeline registers.

Figure 3-6 • Timing Waveforms for Read Operations with Asynchronous Inputs with Pipeline Registers

A2A1

D0

A0A_ADDR[9:0]B_ADDR[9:0]

A_BLKB_BLK



tADDRSU

tADDRHD

tBLKSU

tBLKHD

tCLK2Q

tCLK2Q

tBLKHD

tBLKSU

tPLCLKMPWH

tPLCLKMPWL

Table 3-12 • Timing Parameters of the Asynchronous Read Mode with Pipeline Registers


tPLCY Read pipeline clock period

tPLCLKMPWH Read pipeline clock minimum pulse width High

tPLCLKMPWL Read pipeline clock minimum pulse width Low






60 Revision 4


Figure 3-7 shows the timing diagrams for Asynchronous read mode with latched outputs-pipelineregisters configured as latches. Table 3-13 describes the timing parameters.

Write Operation• Port C is the only port through which a write operation can be performed on uSRAM.

• The write operation is purely synchronous and all operations are synchronized to the rising edgeof the Port C clock input (C_CLK).

• The write inputs-C_ADDR, C_BLK, C_WEN, and C_DIN-have to satisfy the setup and holdtimings with respect to the rising edge of the C_CLK input for a successful write operation.

• If all the inputs meet the required timing parameters, the input data is written into uSRAM in oneclock cycle.

Figure 3-8 on page 62 shows the timing waveforms for a Port C write operation. Table 3-14 on page 62describes the timing parameters.

Figure 3-7 • Timing Waveforms for Read Operations with Asynchronous Inputs with Latched Outputs

A2

D2D0

A1A0A_ADDR[9:0]B_ADDR[9:0]

A_BLKB_BLK


tADDRSUtADDRHD

tBLKSU

tBLKHD

tCLK2QtCLK2Q

tCLPL1

tBLKHD

tBLKSU


Table 3-13 • Timing Parameters of the Asynchronous Read Mode with Latched Outputs


tCLPL1 Minimum pipeline clock low phase in order to prevent glitches with pipeline register in Latch mode






Revision 4 61

Micro SRAM (uSRAM)

Reset OperationThe reset signals (A_ADDR_ARST_N, B_ADDR_ARST_N) are asynchronous Active Low signals for theaddress and block select input registers for Port A and Port B. The assertion of these reset signals forcesthe address and block select input registers to logic 0, which in turn forces the data output to logic 0.When the registers are configured as transparent, tie these inputs to logic 1. Figure 3-9 on page 63shows the timing waveforms for these asynchronous reset signals and Table 3-15 on page 63 shows theTiming parameters for the asynchronous reset.

Figure 3-8 • Timing Waveforms for the Write Operation

tCCY

C_CLK

C_ADDR

C_BLK[1:0]C_WEN

D0 D1Data written in SRAM

C_DIN D 0 D1 D2

tCCLKMPWH

tADDRCSU tADDRCHD

tBLKCSU tBLKCHD

tDINCSU tDINCHD

A 0 A1 A2

tWECSU tWECHD

tCCLKMPWL

tADDRCSU tADDRCHD tADDRCHDtADDRCSU

tBLKCSU tBLKCHD

tWECSU tWECHD

tDINCSU tDINCHD tDINCHDtDINCSU

Table 3-14 • Timing Parameters of the Write Operation


tCCY Write clock period

tCCLKCMPWH Write clock minimum pulse width High

tCCLKCMPWL Write clock minimum pulse width Low

tADDRCSU Write address setup time

tADDRCHD Write address hold time

tBLKCSU Write block setup time

tBLKCHD Write block hold time

tWECSU Write enable setup time

tWECHD Write enable hold time

tDINCSU Write input data setup time

tDINCHD Write input data hold time

62 Revision 4


The reset signals (A_ADDR_SRST_N, B_ADDR_SRST_N) are synchronous Active Low signals for theaddress and block select input registers for Port A and Port B. The assertion of these reset signals forcesthe address and block select input registers to logic 0, which in turn forces the data output to logic 0.

Figure 3-10 on page 64 shows the timing waveform for synchronous reset and Table 3-16 on page 64shows the timing parameters of the synchronous reset.

Figure 3-9 • Timing Waveforms for Asynchronous Reset

tCLKMPWH tCLKMPWL

tCY

tCLK2Q

A_ADDR_CLK

A_ADDR[9:0]

A_BLKB_BLK

A_DOUT[17:0]

A 0 A 1 A2

A_ADDR_ARST_ N

D0D-1

tR2Q

tADDRSU

tADDRHD

B_ADDR_CLK

B_ADDR[9:0]

B_ADDR_ARST_N

B_DOUT[17:0]

Table 3-15 • Timing Parameters of the Asynchronous Reset



tCLKMPWH Read clock minimum pulse width High

tCLKMPWL Read clock minimum pulse width Low

tADDRSU Read address setup time

tADDRHD Read address hold time

tR2Q Read asynchronous reset to output propagation delay


Revision 4 63

Micro SRAM (uSRAM)

CollisionCollision between ports occurs when the read and write operations are requested from two or all threeports at the same time at the same address location. Table 3-17 shows the different scenarios forcollision.

Figure 3-10 • Timing Waveforms for Synchronous Reset


tCLKMPWH tCLKMPWL

tCLK2Q

tCY

tSRSTSU tSRSTHD

A_ADDR_SRST_NB_ADDR_SRST_N

B_DOUTA_DOUT

Table 3-16 • Timing Parameters of the Synchronous Reset



tCLKMPWH Read clock minimum pulse width High

tCLKMPWL Read clock minimum pulse width Low

tSRSTSU Read synchronous reset setup time

tSRSTHD Read synchronous reset hold time

tCLK2Q Read synchronous reset to output propagation delay

Table 3-17 • Collision Scenarios

Operation Comments

Simultaneous read from Port A and read from Port B tothe same address location

Allowed since the read ports are independent of each other.Both read ports deliver correct read data.

Simultaneous read from Port A and write to Port C tothe same address location

Collision occurs. The write operation works correctly but theread operation from Port A generates ambiguous dataoutput unless the clock cycle is long enough to allow thenewly written data to be read.

64 Revision 4


There is no collision prevention or detection implemented in the uSRAM architecture, so the designermust take measures to avoid the last three scenarios in designs.

How to Use uSRAMThe following section describes the Design Flow of uSRAM.

Design FlowLibero SoC software provides a tool for configuring uSRAM blocks in the required operating modes. Therequired HDL wrapper files for uSRAM are generated with appropriate values assigned to the staticsignals. The generated uSRAM wrapper HDL files can be used in the design hierarchy by connecting theports to the rest of the design.

uSRAM - IPFigure 3-11 on page 65 shows the ports of the uSRAM IP macro available in Libero SoC. Refer to theSmartFusion2 Micro SRAM Configuration User Guide for detailed information about softwareconfiguration for SRAM.

Simultaneous read from Port B and write to Port C tothe same address location

Collision occurs. The write operation works correctly but theread operation from Port B generates ambiguous dataoutput unless the clock cycle is long enough to allow thenewly written data to be read.

Simultaneous read form Port A, read from Port B, andwrite to Port C to the same address location

Collision occurs. The write operation works correctly but theread operation from both the ports generates ambiguousdata output unless the clock cycle is long enough to allowthe newly written data to be read.

Table 3-17 • Collision Scenarios (continued)

Operation Comments

Figure 3-11 • uSRAM IP Macro in Libero SoC

Revision 4 65

http://coredocs.s3.amazonaws.com/Actel/SgCore/URAM/sf2_uram_config_ug_1.pdf

http://coredocs.s3.amazonaws.com/Actel/SgCore/URAM/sf2_uram_config_ug_1.pdf

Micro SRAM (uSRAM)

Table 3-18 • Port Description for the uSRAM-IP Macro

Port Name Direction Polarity Description

A_ADDR[] In Port A address input

A_BLK In Active High Port A block select

A_ADDR_CLK In Rising edge Port A clock for A_ADDR

A_DOUT_CLK In Rising edge Port A clock for A_DOUT

A_DOUT[] Out - Port A data output

A_DOUT_ARST In Active Low Port A pipeline register asynchronous reset

A_DOUT_EN In Active High Port A pipeline register enable

A_DOUT_SRST In Active Low Port A pipeline register synchronous reset

A_ADDR_EN In Active High Port A address register enable

A_ADDR_SRST In Active Low Port A address register synchronous reset

A_ADDR_ARST In Active Low Port A address register asynchronous reset

B_ADDR[] In - Port B address input

B_BLK In Active High Port B block select

B_ADDR_CLK In Rising edge Port B clock for B_ADDR

B_DOUT_CLK In Rising edge Port B clock for B_DOUT

B_DOUT[] Out - Port B data output

B_DOUT_ARST In Active Low Port B pipeline register asynchronous reset

B_DOUT_EN In Active High Port B pipeline register enable

B_DOUT_SRST In Active Low Port B pipeline register synchronous reset

B_ADDR_EN In Active High Port B address register enable

B_ADDR_SRST In Active Low Port B address register synchronous reset

B_ADDR_ARST In Active Low Port B address register asynchronous reset

C_ADDR[] In - Port C address input

C_CLK In Rising edge Port C clock for C_ADDR and C_DIN

C_DIN[] In - Port C write data

C_WEN In Active High Port C write enable

C_BLK In Active High Port C block select

66 Revision 4


uSRAM Macro (RAM 64X18)The uSRAM macro (RAM64x18) in Libero SoC can be used directly to instantiate the uSRAM in thedesign. The uSRAM must be configured correctly with appropriate values provided to the static signalsbefore instantiating it in the design. Figure 3-12 shows the uSRAM macro (RAM64x18) available inLibero SoC.

Associated uSRAM IP CoresCoreAHBLSRAM and CoreAPBLSRAM IP coresIn addition to uSRAM macros, Libero SoC also has CoreAHBLSRAM and CoreAPBLSRAM IP coresavailable to access the uSRAM through AHB and APB slave interfaces. You can set configurationparameters such as bus (AHB/APB) data width, RAM selection (LSRAM, uSRAM), and depth of thememory as per design requirement.

Refer to the CoreAHBLSRAM Handbook for uSRAM with AHB slave interface detailed softwareconfiguration information.

Refer to the CoreAPBLSRAM Handbook for uSRAM with APB slave interface detailed softwareconfiguration information.

CoreFIFO IPLibero SoC IP catalog has a CoreFIFO IP, which can be configured as a soft FIFO for generation of FIFOcontrol logic. Memory configuration can be selected as LSRAM, uSRAM or external memory as per thedesign requirements. Refer to the CoreFIFO Handbook for detailed software configuration information.

Figure 3-12 • RAM64x18 Macro

Revision 4 67

Glossary

Acronyms

LSBLeast significant bit


MSBMost significant bit


List of ChangesThe following table lists critical changes that were made in each revision of the chapter.

Date Changes Page


Table 3-2 • Port List for uSRAM is modified (SAR 47579). 49


Restructured the chapter. NA


Added Figure 3-5 to Figure 3-9 and added Table 3-17. 59 to 63

Updated Table 3-11 to Table 3-14. 59 to 62

4 – Mathblocks

IntroductionThe SmartFusion2 SoC FPGA devices have embedded mathblocks, which are optimized for digitalsignal processing (DSP) applications such as finite impulse response (FIR) filters, infinite impulseresponse (IIR) filters, fast Fourier transform (FFT) functions, and encoders that require high datathroughput.

The SmartFusion2 mathblock has a built-in multiplier and adder, which minimizes the external logicrequired to implement multiplication, multiply-add, and multiply-accumulate (MACC) functions.Implementation of these arithmetic functions results in efficient resource usage and improvedperformance for DSP applications. Mathblocks can also be used in conjunction with fabric logic andembedded memories (uSRAM, LSRAM) to implement complex DSP algorithms efficiently. The numberof mathblocks varies depending on the size of the device, as shown in Table 4-2 on page 73.

FeaturesEach mathblock has the following features:

• High-performance and power optimized multiplications operations

• Supports 18 x 18 signed multiplication natively

• Supports 17 x 17 unsigned multiplications

• Supports dot product: the multiplier computes(A[8:0] x B[17:9] + A[17:9] x B[8:0]) x 29

• Built-in addition, subtraction, and accumulation units to combine multiplication results efficiently

• Independent third input C with data width 44 bits completely registered.

• Supports both registered and unregistered inputs and outputs

• Supports signed and unsigned operations

• Internal cascade signals (44-bit CDIN and CDOUT) enable cascading of the mathblocks to support larger accumulator, adder, and subtractor without extra logic

• Supports loopback capability

• Adder support: (A x B) + C or (A x B) + D or (A x B) + C + D

• Clock-gated input and output registers for power optimizations

• Width of adder and accumulator can be extended by implementing extra adders in FPGA fabric.

Mathblock Resource TableTable 4-1 lists the mathblocks available for SmartFusion2 devices.

Table 4-1 • SmartFusion2 Mathblocks Resource

Device Number of Mathblocks

SmartFusion2 Rows Number per Row Total

M2S005 1 11 11

M2S010 2 11 22

M2S025 2 17 34

M2S050 3 24 72

M2S090 3 28 84

M2S100 4 40 160

M2S150 6 40 240

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Mathblocks

Functional DescriptionThis section provides the detailed description of the architecture of Mathblock.

Architecture OverviewSmartFusion2 devices can have one to three rows of mathblocks in the FPGA fabric, as given inTable 4-2 on page 73. Mathblocks can be accessed through the FPGA routing architecture andcascaded in a chain, starting from the left-most block to the right-most block.

Each mathblock consists of the following:

• Multiplier

• Adder or Subtractor

• I/O and Control Registers

Figure 4-1 shows the functional block diagram of the mathblock

Figure 4-1 • Functional Block Diagram of the Mathblock

SUB

DOTP

18

18

44

44

36

44

44

A[17:0]

C[43:0]

B[17:0]

CARRYIN

CARRYIN

ARSHFT17

CDSEL

FDBKSEL

>> 17

CDIN[43:0]

0

C

D

OVFL_CARRYOUT_SEL

OVF

L_CA

RRYO

UT

P[43:0]

CDOUT[43:0]cntlreg

cntlreg

cntlreg

cntlreg

inreg

inreg

inreg

outreg

cntlreg

SUB_AL_NSUB_SL_N

SUB_EN

CLK[1]

CLK[1:0]

CLK[1:0]

CLK[1:0]

CLK[1]

CLK[1]

CLK[1]

A_ARST_N[1:0]

A_SRST_N[1:0]A_EN[1:0]

B_ARST_N[1:0]B_SRST_N[1:0]

B_EN[1:0]

C_ARST_N[1:0]C_SRST_N[1:0]

C_EN[1:0]

ARSHFT17_AL_NARSHFT17_SL_N

ARSHFT17_EN

CDSEL_AL_NCDSEL_SL_N

CDSEL_EN

FDBKSEL_AL_N

FDBKSEL_ENFDBKSEL_SL_N

ARSHFT17_ADARSHFT17_SD_N

ARSHFT17_BYPASS

CDSEL_ADCDSEL_SD_N

CDSEL_BYPASS

FDBKSEL_AD

FDBKSEL_BYPASS

FDBKSEL_SD_N

C_BYPASS[1:0]

B_BYPASS[1:0]

A_BYPASS[1:0]

SUB_BYPASS

SUB_AD

SUB_SD_N

P_ARST_N[1]

P_SRST_N[1]

P_EN[1]

P_BYPASS[1]

CLK[1]

P_ARST_N[1:0]P_SRST_N[1:0]

P_EN[1:0]P_BYPASS[1:0]

CLK[1:0]

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MultiplierA SmartFusion2 mathblock can be used as a multiplier, which accepts two 18-bit inputs (A and B), andgenerates a 36-bit output. The mathblock multiplier can be configured in two different operating modes:

• Normal Mode

• DOTP Mode

Normal ModeIn Normal mode, the mathblock implements a single 18 x18 signed multiplier. The Mathblock accepts theinputs, A [17:0] and B [17:0], and generates A*B with a 36-bit wide result. Figure 4-2 shows the functionalblock diagram of the mathblock in Normal mode.

DOTP Mode Dot Product (DOTP) mode has two independent 9-bit x 9-bit multipliers with adder and the productsum isstored in Upper 36 bits of 44-bit register. In DOTP mode, mathblock implements the following equation:

(A [8:0] x B [17:9] + A[17:9] x B[8:0]) x 29

EQ 1

DOTP mode can be used to implement 9 x 9 complex multiplications.

Figure 4-2 • Functional Block Diagram of the Mathblock in Normal Mode

A[17:0]

B[17:0]

44

44

44D[43:0]

C[43:0]

CARRYIN

SUBNormal Mode

36

18

18

P[43:0]

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Mathblocks

Figure 4-3 shows the functional block diagram of the mathblock in DOTP mode.

Adder or SubtractorThe adder sums the output from the multiplier, C input, CARRYIN, or D input. The final output (P) of theadder is ((A [17:0] x B [17:0]) + C [43:0] + D [43:0] + CARRYIN).

The mathblock can be configured as a 2-input or 3-input adder.

• As a 2-input adder, the mathblock computes A x B + C or A x B + D.

• As a 3-Input adder, the mathblock computes A x B + C + D.

If the adder is configured as a subtractor, the adder output is ((C [43:0] + D [43:0] + CARRYIN) – (A[17:0]x B[17:0])).

I/O and Control RegistersMathblocks have built-in registers on data inputs (A, B, C), data output (P), and control signals. Ifrequired, these registers can be bypassed. All the registers in the mathblock have clock gating capabilityto reduce power consumption.

Mathblocks do not have a pipeline register at the cascade input (CDIN), so pipeline registers can beadded from the fabric when multiple mathblocks are cascaded to implement higher bit-widthmultiplications.

C InputThe C input port allows the formation of many 3-input mathematical functions, such as 3-input addition or2-input multiplication with an addition. The CARRYIN signal is the carry input of the adder oraccumulator. The C input can also be used as a dynamic input achieving the following functionalities:

• Wrapping-around the cascade chain of mathblocks from one row to the next row through the fabric

• Rounding of multiplication outputs

• Trimming of lower order bits of the final sum or partial sum or the product.

Cascaded Input, Output, and SelectionHigher level DSP functions are supported by cascading individual mathblocks in a row. The two datasignals, CDIN [43:0] and CDOUT [43:0], provide the cascading capability with a cascade select input(CDSEL). Table 4-2 on page 73 shows the selection of CDSEL for propagating CDIN to the D input of theadder. To cascade mathblocks, the CDOUT of one block must feed the CDIN of another block. CDOUTto CDIN is a hardwired connection between the blocks within a row.

Figure 4-3 • Functional Block Diagram of the Mathblock in DOTP Mode

A[17:9]B[8:0]

A[8:0]B[17:9]

44

44

36

44D[43:0]

C[43:0]CARRYIN

SUB

P[43:0]

DOT Product Mode

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Two different rows can be cascaded using the fabric routing between the two rows. Extra pipelineregisters may be needed to compensate for the extra delays added due to the fabric routing, which inturn will increase the latency of the chain.

The ability to cascade mathblocks is useful in filter designs. For example, an FIR filter design can usecascading inputs to arrange a series of input data samples and cascading outputs to arrange a series ofpartial output results. The ability to cascade provides a high-performance and low power implementationof DSP filter functions because the general routing in the fabric is not used.

Overflow OutputEach mathblock has an overflow signal, OVFL_CARRYOUT. This signal indicates any overflow from theadditional operation performed by the adder. This signal is also used to extend the adder data widthsfrom the existing 44 bits using fabric. The overflow signal is also used for the implementation ofsaturation capabilities. Saturation refers to catching an overflow condition and replacing the output witheither the maximum (most positive) or minimum (most negative) value that can be represented. InSmartFusion2 mathblocks, this capability is implemented using the adder's output sign bit (MSB [43] bitof the P output) and the overflow signal.

Shift InputFor multi-precision arithmetic, mathblocks provide a right-wire-shift by 17 which is controlled by theARSHFT17 input. Thus, a partial product from one mathblock can be shifted to the right and added to thenext partial product computed in an adjacent mathblock. Using this technique, mathblocks can be usedto build bigger multipliers.

Feedback Select InputFor accumulation operations, mathblock output needs to loopback to the D input of the adder block.Selection of the D input is controlled by the feedback select (FDBKSEL) input. Table 4-2 shows theselection of FDBKSEL for loopback.

Mathblock Interface to Fabric RoutingMathblocks can access the fabric routing through interface logic routing clusters. These clusters arecomposed of 12 flip-flops and 12 4-input (look-up tables) LUTs. When mathblocks are used, these flip-flops and LUTs act as an interface to fabric routing. When mathblocks are not used, these flip-flops andLUTs can be utilized as normal flip-flops and LUTs. The interface logic clusters do not have carry chainsupport.

Table 4-2 • Truth Table for Propagating Operand D of the Adder or Accumulator

CDSEL FDBKSEL ARSHFT17 Operand D

0 0 0 0

0 0 1 0

1 X 0 CDIN[43:0]

1 X 1 17CDIN[43], CDIN[43:18]

0 1 0 P[43:0]

0 1 1 17P[43], P[43:18]

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Mathblocks

How to Use MathblocksThe following sections describe how to use Mathblock in an application:

• Design Flow

• Mathblock Use Models

• Coding Style Examples

Design FlowMathblocks can be used in two ways: through inference or by using the mathblock primitive. Inference isdone during the synthesis stage of an RTL design. Alternately, the mathblock primitive is available in theLibero SoC IP catalog as a component that can be used directly in the HDL file or instantiated inSmartDesign.

Using a Mathblock Through InferenceSynplify Pro can infer mathblocks and can configure them into appropriate modes automatically, if theRTL contains any specific multiply, multiply-accumulate, multiply-add, or multiply-subtract functions. Inthis case, the synthesis tool takes care of all the signal connections of the mathblock to the rest of thedesign and provides the correct values for the static signals to configure the appropriate operationalmode. The tool ties unused dynamic input signals to ground and provides default values to unused staticsignals.

The synthesis tool maps any multiplication function with input widths of 3 or greater to mathblocks.However, the mapping of multiplication functions with input widths less than 3, which are implemented inFPGA logic by default, can be controlled by the synthesis attribute (syn_multstyle). The tool also has thecapability to cascade multiple mathblocks, if the function crosses the limits of a single mathblock. Forexample, if an RTL function has a 35 x 35 multiplication, the synthesis tool implements this using fourmathblocks cascaded in a chain. It also has the capability to place the input and output registers insidethe mathblock boundary, provided they are driven by same clock. If the registers have different clocks,the clock that drives the output register has priority, and all registers driven by that clock are placed intothe mathblock. If the outputs are unregistered and the inputs are registered with different clocks, the inputregisters with the larger input have priority and are placed into the mathblock.

The synthesis tool supports inference of mathblock components across hierarchical boundaries, whichmeans even if the multipliers, input registers, output registers, and subtracter/adders are present indifferent hierarchies, they can be placed into the same mathblock.

For more information on mathblock inference by Synplify Pro, refer to the Synopsys application note oninferring Microsemi SmartFusion2 MACC Blocks.

Using the Mathblock PrimitiveThe mathblock primitive available in the Libero SoC IP Catalog is called MACC. Figure 4-4 on page 75shows the MACC primitive with input/output port and the bit width of each port. The port list anddefinitions are given in Table 4-3 on page 76.

The MACC primitive can be used in designs by SmartDesign for schematic-based design entry or bydirectly instantiating the MACC wrapper in an HDL file as a component. For the MACC primitive, theinputs and outputs must be connected manually to the design signals. Proper values to the static signalsmust be provided to ensure that the mathblock is configured in the correct operational mode. Forexample, to configure the mathblock in DOTP mode, the DOTP signal must be tied to logic 1.

Unused active high dynamic signals should be connected to ground, unused active low dynamic signalsshould be connected to high, and unused static signals should be in default state.

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http://www.microsemi.com/soc/documents/Inferring_Microsemi_SmartFusion2_MACC_Blocks.pdf


Figure 4-4 • Mathblock Macro

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Mathblocks

Table 4-3 • Mathblock Pin Descriptions

Pin Name Direction Type Polarity Description

CLK[1:0] Input Dynamic Rising Edge

Input clocks

• CLK[1] is the clock for A[17:9], B[17:9], P[40:18],OVFL, SHFTSEL, CDSEL, FDBKSEL, and SUBregisters

• CLK[0] is the clock for A[8:0], B[8:0], and P[17:0]

In Normal mode, ensure CLK[1] = CLK[0].

Port A (to Multiplier)

A[17:0] Input Dynamic Input Data

A_ARST_N[1:0] Input Dynamic Low Asynchronous reset

• A_ARST_N[1] is for A[17:9]

• A_ARST_N[0] is for A[8:0]

When not registered, connect A_ARST_N[1:0] to logic 1.

In Normal mode, ensure A_ARST_N[1] = A_ARST_N[0].

A_SRST_N[1:0] Input Dynamic Low Synchronous reset

• A_SRST_N[1] is for A[17:9]

• A_SRST_N[0] is for A[8:0]

When not registered, connect A_SRST_N[1:0] to logic 1.

In Normal mode, ensure A_SRST_N[1] = A_SRST_N[0].

A_EN[1:0] Input Dynamic High Enable for data registers

• A_EN[1] is for A[17:9]

• A_EN[0] is for A[8:0]

When not registered, connect A_EN[1:0] to logic 1.

In Normal mode, ensure A_EN[1] = A_EN[0].

A_BYPASS[1:0] Input Static High Latch input to bypass data registers

• A_BYPASS[1] is for A[17:9]

• A_BYPASS[0] is for A[8:0]

When not registered, connect A_BYPASS [1:0] to logic 1.

In Normal mode, ensure A_BYPASS [1] = A_BYPASS [0].

Port B (to Multiplier)

B[17:0] Input Dynamic Input Data

Notes:

• The asynchronous reset has priority over the synchronous reset and enable signal of the Input/Output registers.

• Asynchronous load input has higher priority than the synchronous load input.

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B_ARST_N[1:0] Input Dynamic Low Asynchronous reset

• B_ARST_N[1] is for B[17:9]

• B_ARST_N[0] is for B[8:0]

When not registered, connect B_ARST_N [1:0] to logic 1.

In Normal mode, ensure B_ARST_N [1] = B_ARST_N [0].

B_SRST_N[1:0] Input Dynamic Low Synchronous reset

• B_SRST_N[1] is for B[17:9]

• B_SRST_N[0] is for B[8:0]

When not registered, connect B_SRST_N [1:0] to logic 1.

In Normal mode, ensure B_SRST_N [1] = B_SRST_N [0].

B_EN[1:0] Input Dynamic High Enable for data registers

• B_EN[1] is for B[17:9]

• B_EN[0] is for B[8:0]

When not registered, connect B_EN [1:0] to logic 1.

In Normal mode, ensure B_EN [1] = B_EN [0].

B_BYPASS[1:0] Input Static High Latch input to bypass data registers

• B_BYPASS[1] is for B[17:9]

• B_BYPASS[0] is for B[8:0]

When not registered, connect B_BYPASS [1:0] to logic 1.

In Normal mode, ensure B_BYPASS [1] = B_BYPASS[0].

Port C (to Adder)

C[43:0] Input Dynamic Input Data

CARRYIN Input Dynamic Adder/accumulator's carry input

C_ARST_N[1:0] Input Dynamic Low Asynchronous reset

• C_ARST_N[1] is for C[43:18]

• C_ARST_N[0] is for C[17:0]

When not registered, connect C_ARST_N[1:0] to logic 1.

In Normal mode, ensure C_ARST_N[1] = C_ARST_N[0].

Table 4-3 • Mathblock Pin Descriptions (continued)


Notes:



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Mathblocks

C_SRST_N[1:0] Input Dynamic Low Synchronous reset

• C_SRST_N[1] is for C[43:18]

• C_SRST_N[0] is for C[17:0]

When not registered, connect C_SRST_N[1:0] to logic 1.

In Normal mode, ensure C_SRST_N[1] = C_SRST_N[0].

C_EN[1:0] Input Dynamic High Enable for data registers

• C_EN[1] is for C[43:18]

• C_EN[0] is for C[17:0]

When not registered, connect C_EN[1:0] to logic 1.

In Normal mode, ensure C_EN[1] = C_EN[0].

C_BYPASS[1:0] Input Static High Latch input to bypass data registers

• C_BYPASS[1] is for C[43:18]

• C_BYPASS[0] is for C[17:0]

When not registered, connect C_BYPASS[1:0] to logic 1.

In Normal mode, ensure C_BYPASS[1] = C_BYPASS[0].

Other Inputs

CDIN[43:0] Input Cascade Cascaded input for operand D of the adder/accumulator. The entire CDIN will be driven by another mathblock's CDOUT.

DOTP Input Static High Dot product mode

When DOTP = 1, mathblock performs

(A[8:0] x B[17:9] + A[17:9] x B[8:0]) x 29

When DOTP = 0, mathblock performs normal 18 x 18 multiplication operations.

SUB Input Dynamic High Subtract operation

When SUB = 1, perform 2's complement subtraction to get

P = C + D + CARRYIN - (A x B).

When SUB = 0, perform 2's complement addition to get

P = C + D + CARRYIN + (A x B).

SUB_AL_N Input Dynamic Low Asynchronous reset input for SUB input's control register.

SUB_SL_N Input Dynamic Low Synchronous reset input for SUB input's control register.

SUB_EN Input Dynamic High Enable input for SUB input's control register.



Notes:



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SUB_BYPASS Input Static High Latch input to bypass SUB input's data register. When logic 1, SUB is not registered.

SUB_AD Input Static High Asynchronous load data for the SUB input's control register.

SUB_SD_N Input Static Low Synchronous load data for the SUB input's control register.

ARSHFT17 Input Dynamic High Arithmetic right-shift for operand D. When asserted, a 17-bit arithmetic right-shift is performed on operand D of the adder/accumulator.

ARSHFT17_AL_N Input Dynamic Low Asynchronous reset input for ARSHFT17 input's control register.

ARSHFT17_SL_N Input Dynamic Low Synchronous reset input for ARSHFT17 input's control register.

ARSHFT17_EN Input Dynamic High Enable input for ARSHFT17 input's control register.

ARSHFT17_BYPASS Input Static High Latch input to bypass ARSHFT17 input's data register. When logic '1', ARSHFT17 is not registered.

ARSHFT17_AD Input Static High Asynchronous load data for the ARSHFT17 input's control register.

ARSHFT17_SD_N Input Static Low Synchronous load data for the ARSHFT17 input's control register.

CDSEL Input Dynamic High Selects CDIN for operand D of the adder/accumulator input.

When CDSEL = 1, CDIN is propagated to the operand D.

When CDSEL = 0, either logic 0 or feedback from output P is routed to the operand D depending upon the FDBKSEL.

CDSEL_AL_N Input Dynamic Low Asynchronous reset input for CDSEL input's control register.

CDSEL_SL_N Input Dynamic Low Synchronous reset input for CDSEL input's control register.

CDSEL_EN Input Dynamic High Enable input for CDSEL input's control register.

CDSEL_BYPASS Input Static High Latch Input to bypass CDSEL input's data register. When logic 1, CDSEL is not registered.

CDSEL_AD Input Static High Asynchronous load data for the CDSEL input's control register.

CDSEL_SD_N Input Static Low Synchronous load data for the CDSEL input's control register.



Notes:



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Mathblocks

FDBKSEL Input Dynamic High Select the feedback from P for operand D of the adder or accumulator.

• When FDBKSEL = 1, propagate the current valueof result P register.

• Ensure P_BYPASS[1] = 0 and CDSEL = 0.

When FDBKSEL = 0, logic 0 is propagated. Ensure CDSEL = 0.

FDBKSEL_AL_N Input Dynamic Low Asynchronous reset input for FDBKSEL input's control register.

FDBKSEL_SL_N Input Dynamic Low Synchronous reset input for FDBKSEL input's control register.

FDBKSEL_EN Input Dynamic High Enable input for FDBKSEL input's control register.

FDBKSEL_BYPASS Input Static High Latch input to bypass FDBKSEL input's data register. When logic 1, FDBKSEL is not registered.

FDBKSEL_AD Input Static High Asynchronous load data for the FDBKSEL input's control register.

FDBKSEL_SD_N Input Static Low Synchronous load data for the FDBKSEL input's control register.

Output Port

P[43:0] Output Result data out

• Normal mode

P = C + D + CARRYIN + (A x B) when SUB = 0

P = C + D + CARRYIN - (A x B) when SUB = 1

• DOTP mode

P = C + D + CARRYIN + ((A[8:0] x B[17:9] + A[17:9] x B[8:0]) x 29) when SUB = 0

P = C + D + CARRYIN - ((A[8:0] x B[17:9] + A[17:9] x B[8:0]) x 29) when SUB = 1



Notes:



80 Revision 4


OVFL_CARRYOUT Output Overflow output

• Normal mode

if C + D + CARRYIN +/- (A x B) > (243 - 1), then OVFL_CARRYOUT = 1

if C + D + CARRYIN +/- (A x B) < - (243), then OVFL_CARRYOUT = 1

else

OVFL_CARRYOUT = 0.

• DOTP mode

if C + D + CARRYIN +/- ((A[8:0] x B[17:9] + A[17:9] x B[8:0]) x 29) > (243- 1), then OVFL_CARRYOUT = 1

if C + D + CARRYIN +/- ((A[8:0] x B[17:9] + A[17:9] x B[8:0]) x 29) < - (243), then

OVFL_CARRYOUT = 1

else

OVFL_CARRYOUT = 0.

OVFL_CARRYOUT_SEL Input Static High Input to the adder for generating the overflow bit or an external bit, which finally comes as an output on the OVFL_CARRYOUT port. The overflow bit indicates the overflow generated in the addition process. The external bit is generated to extend the adder into the fabric. In this case, P[43], C[43], and D[43] are basically not representing the sign bit.

When OVFL_CARRYOUT_SEL = 1,

OVFL_CARRYOUT is the external bit for fabric extension. Otherwise, OVFL_CARRYOUT is the overflow output.

CDOUT[43:0] Output Cascade output of result P. CDOUT is the same as P. It is used to drive the CDIN of another mathblock.

P_ARST_N[1:0] Input Dynamic Low Asynchronous reset input for P and OVFL_CARRYOUT control registers

• P_ARST_N [1] is for OVFL_CARRYOUT andP[43:18]

• P_ARST_N [0] is for P[17:0]

When not registered, connect P_ARST_N [1:0] to logic 1.

In Normal mode, ensure P_ARST_N [1] = P_ARST_N [0].



Notes:



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Mathblocks

Mathblock Use ModelsThis section describes a few use models for SmartFusion2 mathblocks.

Use Model 1: Non-Pipelined Implementation of the 35 x 35 Multiplier35 x 35 multipliers are useful for applications which require more than 18-bit precision. Non-pipelinedimplementation is typically used for low speed applications. A 35 x 35 multiplier can be constructed using4 mathblocks in a single row, connected in a cascade. Figure 4-5 on page 83 shows a typicalimplementation of a non-pipelined 35 x 35 multiplier.

P_SRST_N[1:0] Input Dynamic Low Synchronous reset input for P and OVFL_CARRYOUT control registers

• P_SRST_N [1] is for OVFL_CARRYOUT andP[43:18]

• P_SRST_N [0] is for P[17:0]

When not registered, connect P_SRST_N [1:0] to logic 1.

In Normal mode, ensure P_SRST_N [1] = P_SRST_N [0].

P_EN[1:0] Input Dynamic High Enable input for P and OVFL_CARRYOUT control registers

• P_EN[1] is for OVFL_CARRYOUT and P[43:18]

• P_EN[0] is for P[17:0]

When not registered, connect P_EN[1:0] to logic 1.

In Normal mode, ensure P_EN[1] = P_EN[0].

P_BYPASS[1:0] Input Static High Latch input for P and OVFL_CARRYOUT control registers

• P_BYPASS[1] is for OVFL_CARRYOUT andP[43:18]

• P_BYPASS[0] is for P[17:0]

When not registered, connect P_BYPASS[1:0] to logic 1.

In Normal mode, ensure P_BYPASS[1] = P_BYPASS[0].



Notes:



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The inputs are assumed to be A [34:0] and B [34:0] with a product of P [69:0].

Use Model 2: Pipelined Implementation of the 35 x 35 MultiplierSmartFusion2 mathblocks have built-in registers on all input and output ports. To implement high-speedmultipliers, extra registers are added to the input or output side of the mathblocks to balance the pipelinelatency. These extra registers are implemented in the fabric.

Figure 4-5 • Non-Pipelined 35 x 35 Multiplier

B [17:0] = B[34:17]

A [17:0] = 0, A[16:0]L

B [17:0] = B[34:17]H

A [17:0] = A[34:17]H

B [17:0] = 0, B[16:0]L

A [17:0] = 0, A[16:0]L

B [17:0] = 0, B[16:0]L

A [17:0] = A[34:17]

>>17

>>17

P[69:34]

P[16:0]

P[33:17]

0

H

H

Unconnected

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Mathblocks

Figure 4-6 shows a typical 35 x 35 multiplier implementation with fabric pipeline registers.

Use Model 3: Implementation of 9-Bit Complex MultiplicationComplex multiplication implemented using a mathblock in DOTP mode requires additional 2'scomplement logic in the fabric for negating the Q input. The DOTP implementation in Figure 4-7 onpage 85 shows the optimized way of implementing the 2's complement with minimal logic in the fabric.

For two complex numbers X + jY, P + jQ, the complex multiplication is shown in EQ 2:

Multiplication Result = Real part + Imaginary Part = (PX - QY) + j (PY + QX)

EQ 2

In EQ 2, real part (PX-QY) requires that ‘-Q’ for the multiplication result. This can be compute using theone‘s complement of Q and add the Y using the c input (since -Q = ~Q+1).

Imaginary part = P*Y+Q*X

EQ 3

Real part = P*X + (~Q)*Y + Y

EQ 4

Figure 4-6 • Pipeline 35 x 35 Multiplier

B [17:0] = B[34:17]H

A [17:0] = 0, A[16:0]L

B [17:0] = B[34:17]H

A [17:0] = A[34:17]H

B [17:0] = 0, B[16:0]L

A [17:0] = 0, A[16:0]L

B [17:0] = 0, B[16:0]L

A [17:0] = A[34:17]H

>>17

>>17

P[69:34]

P[16:0]

P[33:17]

Unconnected

0- Fabric Registers

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Figure 4-7 shows the implementation of 9 x 9 complex multiplication using a mathblock configured inDOTP mode.

Use Model 4: Multi-Threading and Multi-ChannelingMathblocks support a multi-threading option where the same mathblock can be used for performing morethan one computation by time multiplexing. Time multiplexing can be done easily for designs with lowsample rates.

The multi-threading capability, if implemented for a chain of mathblocks, is called multi-channeling.

Multi-channeling can be used to implement multi-channel FIR filters where the same mathblock chaincan be used to process multiple input channels by time multiplexing the mathblock chain. Multi-channelfiltering is used in applications such as wireless communications, image processing, and multimediaapplications. The mathblock uses its C input for multi-threading and multi-channeling, but fabric registersare also required for implementation.

Use Model 5 - Rounding and TrimmingRoundingRounding can be computed by adding a fixed term and a variable term to the input value to be rounded,and then truncating. The fixed term can be feed using the C-Input of the mathblock and the valuedepends on the number of decimal points required after rounding. The variable term is always a single bitin the least-significant position whose value may be determined from the input value based on the type ofrounding.

Figure 4-7 • 9-Bit Complex Multiplication Using DOTP Mode

3-Input Adder

X

Y

P

Q

44 PY+ QX9

9

9

9

<< 9

Dot Product ModeA

HB

LB

HA

L

Mathblock1

3-Input Adder

X

Y

P

Q

44PX- QY9

9

9

9

<< 9

Dot Product ModeA

HB

LB

HA

L

Mathblock2

1’s complementLogic

(Imaginary Part)

(Real Part)

C[43:0]= Zeroes 44

C[43:19] = Zeroes C[9:0] = Zeroes

44

C[18:10]= Y

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Mathblocks

Types of rounding are:

• Round to the adjacent even integer: The variable term is determined from the 20 bit of the input value.

• Round towards zero: The variable term is determined from the sign bit of the input value. For example, 1.5 rounds to 1 and -1.5 rounds to -1.

Table 4-4 on page 86 gives examples for 6-bit values including three fraction bits.

Table 4-4 • Rounding Examples

Input ValueFixed Term

C-Input

Round To Even Round Toward Zero

Decimal Binary Variable Term

Sum Truncated Sum

Decimal Variable Term

Sum Truncated Sum

Decimal

2.5 010.100 0.011 000.000 010.111 010 2 000.000 010.111 010 2

1.5 001.100 0.011 000.001 010.000 010 2 000.000 001.111 001 1

-1.5 110.100 0.011 000.000 110.111 110 -2 000.001 111.000 111 -1

-2.5 101.100 0.011 000.001 110.000 110 -2 000.001 110.000 110 -2

Figure 4-8 • Rounding Using C-Input and CARRYIN

A[17:0]

B[17:0]

44

1

18

Variable Term

Fixed Term

18

18

P[43:0]

CARRYIN

C Input

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TrimmingTrimming of the Final Sum: Applications like IIR and FFT often requires the rounding and trimming ofthe final result (for example, last output of a cascade chain or the final value read from an accumulator).The addition of the rounding terms can be done as shown in the Figure 4-9 and final result can betrimmed in fabric.

Trimming of Grouped Sums: When computing very large dot products (for example, a large, fully-enumerated FIR) it is good to avoid overflow by breaking the sum into a few groups, trimming thesum for each group, and only then combining the groups' sums into a final result. The rounding of eachgroup's sum can be done as shown in Figure 4-9 on page 87. The trimming of each group's sum andsummation of the final result can be done in the fabric. Trimming can be done between the output of eachcascade and the final fabric adder.

Trimming of Products: Figure 4-10 shows the implementation of rounding all products towards zero andthen trimming the least significant m bits of the product. As long as there are no additive terms other thanthe products, it is possible to equivalently trim the partial sums instead of the products. Round towardszero can be done using sign bit of the product (A*B) from the sign bits of the incoming factors A and Busing an EXOR.

Figure 4-9 • Rounding and Trimming of the Final Sum

FixedTerm

A B A B

VariableTerm

1

P

Figure 4-10 • Rounding and Trimming of the Final Sum

C

A

B

P[43:m]

A

B

A[17]

B[17]

C[m-1]

C[m-1]

C[43:m] P

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Mathblocks

Coding Style ExamplesThe following code examples illustrate coding styles from which the synthesis tool can infer andimplement SmartFusion2 Mathblocks.

Example 1: 18 x 18 Signed Multiplication – Non-Registered

The following code is for an 18 x 18-bit signed multiplier. The input and output registers are configured inTransparent mode. The synthesis tool maps the code into one mathblock.

module sign18x18_mult ( in1, in2, out1 ); input signed [17:0] in1, in2; output signed [40:0] out1;wire signed [40:0] out1;assign out1 = in1 * in2;

endmodule

Example 2: 18 x 18 Signed Multiplication – Registered

The following code is for an 18 x 18 signed multiplier. The inputs and outputs are registered, with asynchronous active low reset signal. The synthesis tool maps the code into one mathblock.

module sign18x18_mult_reg ( in1, in2, clock, reset, out1 );input signed [17:0] in1, in2;input clock;input reset;output signed [40:0] out1;reg signed [40:0] out1;reg signed [17:0] in1_reg, in2_reg;always @ ( posedge clock )beginif ( ~reset )beginin1_reg <= 18'b0; in2_reg <= 18'b0; out1 <= 41'b0;

end else beginin1_reg <= in1;n2_reg <= in2;out1 <= in1_reg * in2_reg;

end end

endmodule

Example 3: 17 x 17-Bit Unsigned Multiplier with Different Resets

The following code is for a 17 x 17-bit unsigned multiplier, which has input and output registers withdifferent asynchronous resets. The synthesis tool maps the code into one SmartFusion2 mathblock.

module mult_17x17unsign( in1, in2, clock, reset1, reset2, out1 );input [16:0] in1, in2;input clock, reset1, reset2;output [33:0] out1;reg [33:0] out1;reg [16:0] in1_reg, in2_reg;always @(posedge clock or negedge reset1)beginif (~reset1 )beginin1_reg <= 17'b0;in2_reg <= 17'b0;

end else beginin1_reg <= in1;in2_reg <= in2;

endend

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always @(posedge clock or negedge reset2)begin

if (~reset2 )beginout1 <= 34'b0;

end else

beginout1 <= in1_reg * in2_reg;

end end

endmodule

Example 4: 17 x 17-Bit Unsigned Multiplier with Different Clocks

This example shows an unsigned multiplier with inputs and outputs that are registered with differentclocks: clock1 and clock2. In this case, the synthesis tool places only the output registers and themultiplier into the SmartFusion2 mathblock. The input registers are implemented in FPGA logic outsidethe mathblock.

module mult_17x17unsign ( in1, in2, clock1, clock2, outl );input [16:0] in1, in2; input clock1,clock2; output [33:0] outl;reg [33:0] outl;reg [16:0] in1_reg, in2_reg; always @ ( posedge clock1 ) beginin1_reg <= in1;in2_reg <= in2;

endalways @ ( posedge clock2 )beginoutl <= in1_reg * in2_reg;

end endmodule

Example 5: Multiplier-Adder

In the code below. the output of a multiplier is added with another input. Inputs and outputs are registeredand have enables and synchronous resets. The synthesis tool maps the code into one SmartFusion2mathblock.

module mult_add_v1( in1, in2, in3, clock, reset, en, out1);input [16:0] in1, in2;input [33:0] in3;input clock, reset, en;output [34:0] out1;reg [34:0] out1;reg [16:0] in1_reg, in2_reg;reg [33:0] in3_reg; wire [33:0] mult_out; always @(posedge clock) beginif (~reset)beginin1_reg <= 17'b0; in2_reg <= 17'b0; in3_reg <= 34'b0;

endelse beginif (en == 1'b1)beginin1_reg <= in1; in2_reg <= in2; in3_reg <= in3;end

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Mathblocks

end endalways @(posedge clock)beginif (~reset)beginout1 <= 35'b0;

end else beginif (en == 1'b1)beginout1 <= 1'b0, mult_out + 1'b0, in3_reg;

end endendassign mult_out = in1_reg * in2_reg;

endmodule

Example 6: Multiplier-Subtractor

There are two ways to implement multiplier and subtract logic. The synthesis tool places the logicdifferently, depending on how it is implemented.

• Subtract the result of multiplier from an input value (P = Cin – mult_out). The synthesis tool places all logic in the mathblock.

• Subtract a value from the result of the multiplier (P = mult_out – Cin). The synthesis tool places only the multiplier in the mathblock. The subtractor is implemented in FPGA logic outside the mathblock.

– Unsigned MultSub Example (P = Cin – Mult_out) - Implemented in single mathblock.

module mult_sub ( in1, in2, in3, clk, rst, out1 );input [16:0] in1, in2;input [36:0] in3;input clk;input rst;output [39:0] out1;reg [39:0] out1;reg [16:0] in1_reg, in2_reg; always @ ( posedge clk ) beginif (~rst)beginin1_reg <= 17'b0; in2_reg <= 17'b0; out1 <= 40'b0;

endelse beginin1_reg <= in1;in2_reg <= in2;out1 <= in3 - (in1_reg * in2_reg);

end end

endmodule

– Unsigned MultSub Example (P = Mult - Cin) - Multiplier is implemented in mathblock and subtractor in FPGA logic

module mult_sub_v2 ( in1, in2, in3, clk, rst, out1 );input [16:0] in1, in2;input [36:0] in3;input clk;input rst;output [39:0] out1;reg [39:0] out1;reg [16:0] in1_reg, in2_reg;

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always @ ( posedge clk ) beginif ( ~rst )beginin1_reg <= 17'b0; in2_reg <= 17'b0; out1 <= 40'b0;

end else beginin1_reg <= in1;in2_reg <= in2;out1 <= (in1_reg * in2_reg) - in3;

end end

endmodule

Example 7: Signed 35 x 35 Multiplication

The code below implements a signed 35 x 35 multiplication function. The synthesis tool uses 4 cascadedmathblocks to implement this multiplication function.

module sign35x35_mult ( in1, in2, out1);input signed [34:0] in1; input signed [34:0] in2; output signed [69:0] out1; wire signed [69:0] out1; assign out1 = in1 * in2; endmodule

Example 8: Signed 35 x 35 Multiplication with Two Pipelined Register Stages

The code below implements a signed 35 x 35 multiplication function with two pipelined register stages.The synthesis tool uses four cascaded mathblocks to implement this multiplication function. Thesynthesis tool first infers pipeline registers at the input, output of the SmartFusion2 mathblock andcontrols pipeline latency by balancing the number of register stages. To balance the stages, the tool addsadditional registers at the input or output of the mathblock as required, implemented in the fabric logic.

module sign35x35_mult ( in1, in2, clk, rst, out1 );input signed [34:0] in1, in2;input clk;input rst;output signed [69:0] out1;reg signed [69:0] out1;reg signed [34:0] in1_reg, in2_reg; always @ ( posedge clk or negedge rst) beginif ( ~rst )beginin1_reg <= 35'b0; in2_reg <= 35'b0; out1 <= 70'b0;

end else beginini_reg <= in1;in2_reg <= in2;out1 <= ini_reg * in2_reg;

end end

endmodule

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Mathblocks

Glossary

Terminology

Multi-ChannelingMulti-threading done for a chain of mathblocks

Multi-ThreadingUsing a mathblock for performing more than one computation by time multiplexing it.

Pipelined OperationThe mode of operation where the mathblock output is registered at the pipeline registers.

List of ChangesThe following table lists critical changes that were made in this chapter.

Date Changes Page


Table 4-2 • Truth Table for Propagating Operand D of the Adder or Accumulator is modified (SAR 47579).

73

Updated "Features" section (SAR 48006). 69


Restructured the chapter (SAR 45834). NA


Modified Table 4-3 (SAR 41834). 76

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5 – I/Os

IntroductionThe SmartFusion2 SoC FPGA devices have different types of input/outputs (I/Os), such as multi-standard I/Os (MSIO and MSIOD), double data rate I/Os (DDRIO), and dedicated I/Os based onfunctional usage.

The MSIO, MSIOD, and DDRIO provide programmable I/O features such as drive strength, slew rate,input delay, weak pull-up, and weak pull-down for several voltages. The programmable I/O features areexplained in detail in the "I/O Programmable Features" section on page 100.

The DDRIO is an MSIO optimized for LPDDR/DDR2/DDR3 performance. In SmartFusion2 devices,there are two DDR subsystems: the fabric DDR and microcontroller subsystem (MSS) DDR controllers.DDRIOs can be connected to the respective DDR subsystem PHYs or can be used as user I/Os.

The MSIO, MSIOD, and DDRIO can be configured as MSS or fabric I/Os, whereas dedicated I/Os can beused for a single purpose such as serializer/deserializer (SERDES), device reset, and clock functions.Dedicated I/Os cannot be used by any other circuits.

The MSIO, MSIOD, and DDRIO are configured at power-up by means of fabric-related flash bits, whichare used to initialize register blocks. The power-up sequence on the I/O is configured through the systemcontroller and is responsible for controlling the power sequences.

Functional DescriptionFigure 5-1 on page 94 shows the I/O interconnection with fabric, MDDR/FDDR, and MSS peripherals.I/Os are shared with the fabric and MDDR / FDDR / MSS peripherals.

When the MDDR/FDDR controller is used, Libero SoC automatically assigns and configures theMDDR/FDDR controller signals to DDRIOs. In a similar way, when the MSS peripheral is used, LiberoSoC automatically assigns and configures the MSS peripheral signals to MSIOs and MSIODs. For fabriclogic, each I/O port of the design must be individually assigned to I/Os in Libero SoC.

DDRIOs are shared between fabric logic and the MDDR and FDDR, whereas, MSIOs and MSIODs areshared between MSS peripherals and fabric logic. SPIO_SEL signal (as shown in Figure 5-1 onpage 94), determines whether fabric logic or MDDR / FDDR / MSS peripherals will connect to thecorresponding I/O. The selection (SPIO_SEL) of FDDR / MDDR / MSS peripherals, or fabric logic, is setby Libero SoC and configured during programming. When the MDDR/FDDR controller or MSSperipherals are not used, the respective I/Os are available to fabric logic, as shown in Figure 5-1 onpage 94.

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I/Os

The MSIO, MSIOD, and DDRIO can be configured as one differential I/O or two single-ended I/Os.Single-ended I/Os are composed of two separate I/Os named P and N, as shown in Figure 5-1.

The differential I/O is implemented by pairing up P and N. The differential standards are implemented astrue differential outputs and not complementary single-ended outputs.

An I/O consists of a highly featured bidirectional I/O buffer. The I/O is divided into two main sections, asshown in Figure 5-1:

• Digital: IOD (fabric and MDDR / FDDR / MSS peripherals)

• Analog: IOA

The digital (IOD) section generates output enable (OE), data out (DO), and data in (DIN) signals for bothP and N. Refer to the "Fabric Architecture" chapter on page 7 for more details on IOD.

The analog (IOA) section has transmitter and receiver buffers for the P and N pair. The main circuits inthe IOA are transmit and receive buffers (as shown in Figure 5-2 on page 96), that support various I/Ostandards and contain the following modules:

• Transmit Buffer

• Receive Buffer

• Low Power Exit

• On-Die Termination

Figure 5-1 • I/O Interconnection

User Configures in Libero SoC

Libero SoCConfigures Automatically

User configures in Libero SoC

Libero SoC Configures automatically

FabricLogic

FabricLogic

MDDR/FDDRController + PHY

MDDR/FDDRController + PHY

Fabric IOD

MDDR/FDDRIOD

Fabric IOD

MDDR/FDDRIOD

IOAIOD

Transmitter andReceiver

Transmitter andReceiver

PAD

PAD

I/P bufferdisable control

O/P bufferdisable control

Data_out1

Data_in1

DO_P

DI_P

Data_out2

Data_in2

DO_N

DI_N

OE_P

DO_P

DI_P

OE_P

DO_P

DI_P

OE_N

DO_N

DI_N

OE_N

DO_N

DI_N

SPIO_SEL

SPIO_SEL

Differential

Differential

P

N

10

10

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Transmit BufferTransmit and receive buffers transfer signals between the FPGA fabric and the IOA and also transfersignals between MDDR, FDDR, MSS peripherals and the IOA.

OE_P and OE_N control the direction of I/O buffers, as shown in Figure 5-2 on page 96. When an I/O isoperated as a single-ended I/O, OE_P and OE_N individually control the P and N I/O buffers. When anI/O is operated as a differential I/O, OE_P controls both the P and N I/O buffers.

The dynamic OE disables or enables an output buffer for all the standards.

Receive BufferThe enabling and disabling of the input buffer is controlled automatically by Libero SoC.

The I/O receiver can be made to operate in four different modes, as shown in Figure 5-2 on page 96.These modes are selected based on flash configuration bits, which are configured during programming,after power-on. Following are the four modes of the receiver:

• True differential

• Pseudo-differential

• Single-ended

• Schmitt trigger

In True differential mode, P and N pad inputs are fed to the comparator, whereas in Pseudo-differentialmode, each pad input is compared to reference with external reference voltage. Figure 5-2 on page 96shows the detailed IOA structure of an I/O.

The I/O input can be configured as a Schmitt trigger receiver or single-ended receiver. When Schmitttrigger inputs are selected, the input buffers present hysteresis that filters the noise at the receiver andprevents double glitching caused by noisy input edges.

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I/Os

Low Power ExitLow power exit logic indicates to the system controller that designated I/Os have either matched the pre-defined signature bit or have detected activity on the selected I/O after the chip has entered Lowpower mode. For details on Signature and Activity modes, refer to the "Signature Mode" section onpage 107 and "Activity Mode" section on page 107.

On-Die TerminationOn-die termination (ODT) improves the signaling environment by reducing the electrical discontinuitiesintroduced with off-die termination and hence enables reliable operation at higher signaling rates.

For more information on the programmed ODT values for DDRIO, MSIO, and MSIOD, refer to the "I/O Programmable Features" section on page 100.

Figure 5-2 • IOA Architecture

-+

-+

-+

Tx P

Tx N

10

10

OE_P

DO_P

DIN_P_delayed

Fabricor

MDDR/FDDRor

MSS Peripherals

DIN_P

OE_N

DO_N

DIN_N_delayed

DIN_N

DDRIOCalibration Block

Program directly ODT to desired value

Reference Resistor Value

44-DDRIO Pairs Connected to MDDR/FDDR

Single-Ended

Schmit

Psuedo-Differential

True -Differential

Single - ended

Schmit

Psuedo - Differential

VCCIO

VCCIO

X_VREF

X_VREF

ODT /TransmitterImpedance

Input Programming Delay

Input Programming Delay

Differential

Programmable Slew rate for ‘P’ driver

Programmable Slew rate for ‘N’ driver Voltage Standard Select

Programmable Pull-up (or)Pull-down (or)

Disable both for ‘P’

Programmable Pull -up (or )Pull -down (or)

Disable both for ‘N’

PAD_P

PAD_N

IOA

Receiver P

Receiver N

ODT / TransmitterImpedance

DifferentialODT

(MSIOD only)

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I/O BanksI/Os are grouped on the basis of I/O voltage standard. The grouped I/Os of each voltage standard forman I/O bank. Each I/O bank has dedicated I/O supply and ground voltages. Because of these dedicatedsupplies, only I/Os with compatible standards can be assigned to the same I/O voltage bank.

There are 10 I/O banks as shown in SmartFusion2 M2S050 device. Every I/O bank has input and outputbuffers to support a wide range of standards, which require different VCC voltage and reference voltages(VREF) for voltage referenced standards. These voltages are externally supplied and connected todevice pins, which serve banks (groups) of I/Os.

The MSIOs, MSIODs, and DDRIOs are divided into banks, each of which may be configured to support one of the standards listed in Table 5-1 on page 98.

Figure 5-3 • SmartFusion2 (M2S050T-FG896) I/O Bank Location and Naming

Bank 9MSIOD/SERDES_1

(2 pairs)

Bank 0DDRIO (MDDR)

(44 pairs)

Bank 5DDRIO (FDDR)

(44 pairs)

Bank 7MSIOD

(27 pairs)

Bank 6MSIOD/SERDES_0

(2 pairs)

Bank 8MSIO

(23 pairs)

Bank 1MSIO

(10 pairs)

Bank 3MSIO

(23 pairs)

Bank 4JTAG

SmartFusion2 SoC FPGAM2S050T-FG896

Bank 2MSIO

(13 pairs)

Figure 5-4 • SmartFusion2 (M2S010T-FG484) I/O Bank Location and Naming

Bank 7MSIO

(18 pairs)

Bank 0DDRIO (MDDR)

(35 pairs)

Bank 4MSIO

(17 pairs)

Bank 5MSIOD/SERDESIF_0

(2 pairs)

Bank 6MSIOD

(18 pairs)

Bank 1MSIO

(7 pairs)

Bank 3JTAG

SmartFusion2 SoC FPGAM2S010T-FG484

Bank 2MSIO

(19 pairs)

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I/Os

Table 5-1 shows the organization of I/O banks in SmartFusion2 devices.

Supported I/O StandardsThe Table 5-2 shows supported voltage standards supported for various I/O types.

For I/O pin naming and assignments to specific banks, refer to the SmartFusion2 Pin Descriptions.

Table 5-1 • The Organization of I/O Banks in SmartFusion2 Devices

I/O Banks M2S050 M2S010

Bank 0 DDRIO: MDDR or fabric DDRIO: MDDR or fabric

Bank 1 MSIO: MSS or fabric MSIO: MSS or fabric

Bank 2 MSIO: MSS or fabric MSIO: MSS or fabric

Bank 3 MSIO: MSS or fabric MSIO: JTAG/SWD

Bank 4 MSIO: JTAG/SWD MSIO: MSS or fabric

Bank5 DDRIO: FDDR or fabric MSIOD: SERDES_IF_0 or fabric

Bank 6 MSIOD: SERDES_IF_0 or fabric MSIOD: MSS or fabric

Bank 7 MSIOD: fabric MSIO: MSS or fabric

Bank 8 MSIO: fabric

Bank 9 MSIOD: SERDES_IF_0 or fabric

Table 5-2 • Supported Voltage Standards

I/O Standards

I/O Types

MSIO MSIOD DDRIO

Single-Ended I/O

LVTTL 3.3 V Yes – –

LVCMOS 3.3 V Yes – –

PCI Yes – –

LVCMOS 1.2 V Yes Yes Yes




Voltage-Referenced I/O

HSTL1.5V Yes Yes Yes

SSTL1.8 V Yes Yes Yes

SSTL2.5 V Yes Yes Yes

SSTL 2.5 V(DDR1) Yes Yes Yes

SSTL 1.8V (DDR2) Yes Yes Yes

SSTL 1.5V (DDR3) Yes Yes Yes

Differential I/O

LVPECL (input only) Yes – –

LVDS 3.3 V Yes – –

LVDS 2.5 V Yes Yes –

RSDS Yes Yes –

BLVDS Yes – –

MLVDS Yes – –

Mini-LVDS Yes Yes –

98 Revision 4




Single-Ended StandardsSingle-ended I/O standards use a push-pull CMOS output stage with a voltage referenced to systemground. The input buffer configuration, output drive, and I/O supply voltage (VCCI) vary among the I/Ostandards. The advantage of these standards is that a common ground can be used for multiple I/Os.This simplifies board layout and reduces system cost. The reduced slew rate of these I/O standardscauses less electromagnetic interference (EMI) on the board. However, these I/Os are not suitable for high frequency (>200 MHz) switching due to noise and higher power consumption.

Low Voltage TTL (LVTTL)This is a general purpose standard (EIA/JESD8-B) for 3.3 V applications. It uses an LVTTL input bufferand a push-pull output buffer. The LVTTL output buffer can have up to eight different programmable drivestrengths.

Low Voltage CMOS (LVCMOS)SmartFusion2 devices provide five different kinds of LVCMOS: LVCMOS 3.3 V, LVCMOS 2.5 V,LVCMOS 1.8 V, LVCMOS 1.5 V, and LVCOMS1.2 V. LVCMOS 3.3 V (only in MSIO) is an extension of theLVCMOS standard (JESD8-B compliant) used for general purpose 3.3 V applications. LVCMOS 2.5 V isan extension of the LVCMOS standard (JESD8-5-compliant) used for general purpose 2.5 Vapplications.

LVCMOS 1.8 V is an extension of the LVCMOS standard (JESD8-7-compliant) used for general purpose1.8 V applications. The LVCMOS 1.5 V is an extension of the LVCMOS standard (JESD8-11-compliant)used for general purpose 1.5 V applications.

The VCCI values for these standards are 3.3 V, 2.5 V, 1.8 V, 1.5 V, and 1.2 V, respectively. All theseversions use a 3.3 V-tolerant CMOS input buffer and a push-pull output buffer. Similar to LVTTL, theoutput buffer has up to eight different programmable drive strengths.

3.3 V Peripheral Component Interface (PCI)This standard specifies support for both 33 MHz and 66 MHz PCI bus applications. It uses an LVTTLinput buffer and a push-pull output buffer. With the aid of an external resistor, this I/O standard can be5 V-compliant.

Voltage-Referenced StandardsI/Os using these standards are referenced to an external reference voltage (VREF).

High-Speed Transceiver Logic (HSTL) Class I These are general purpose, high-speed 1.5 V bus standards (EIA/JESD8-6) for signaling betweenintegrated circuits. The signaling range is 0 V to 1.5 V, and signals can be either single-ended ordifferential. HSTL requires a differential amplifier input buffer and a push-pull output buffer. Thesestandards are used in the memory bus interface with data switching capability of up to 400 MHz. Theother advantages of these standards are low power and fewer EMI concerns. HSTL has four classes, ofwhich SmartFusion2 devices support Class I. The reference voltage (VREF) is 0.75 V.

Stub Series Terminated Logic 2.5 V (SSTL2) Class I and II These are general purpose 2.5 V memory bus standards (JESD8-9) for driving transmission lines,designed specifically for driving the DDR SDRAM modules used in computer memory. The SSTL2requires a differential amplifier input buffer and a push-pull output buffer. The reference voltage (VREF) is1.25 V.

Stub Series Terminated Logic 1.8 V (SSTL18) Class I and II These are general purpose 1.8 V memory bus standards (JESD8-15) for driving transmission lines,designed specifically for driving the DDR2 SDRAM modules used in computer memory. SSTL18 requiresa differential amplifier input buffer and a push-pull output buffer. The VREF is 0.9 V.

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I/Os

Differential StandardsThese standards require two I/Os per signal (called a signal pair). Logic values are determined by thepotential difference between the lines, not with respect to ground. This is why differential drivers andreceivers have much better noise immunity than single-ended standards. The differential interfacestandards offer higher performance and lower power consumption than their single-ended counterparts.Two I/O pins are used for each data transfer channel. Differential standards require resistor terminationon both I/Os.

Low Voltage Positive Emitter Coupled LogicLow voltage positive emitter coupled logic (LVPECL) requires that one data bit is carried through twosignal lines; therefore, two pins are needed per input or output. It also requires external resistortermination. The voltage swing between the two signal lines is approximately 850 mV. When the powersupply is +3.3 V, it is commonly referred to as LVPECL.

Low Voltage Differential Signal Low voltage differential signal (LVDS) is a differential I/O standard. As with all differential signalingstandards, LVDS requires that one data bit is carried through two signal lines, and it has inherent noiseimmunity over single-ended I/O standards. The voltage swing between two signal lines is approximately350 mV. The external VREF or board termination voltage (VTT) is not required. LVDS requires the use oftwo pins per input or output.

Reduced Swing Differential SignalingReduced swing differential signaling (RSDS) is a signaling standard that defines the outputcharacteristics of a transmitter and inputs of a receiver along with the protocol for a chip-to-chip interfacebetween flat-panel timing controllers and column drivers.

B-LVDS/M-LVDSBus LVDS (B-LVDS) refers to bus interface circuits based on LVDS technology. Multipoint LVDS(M-LVDS) specifications extend the LVDS standard to high-performance multipoint bus applications.Multi-drop and multipoint bus configurations may contain any combination of drivers, receivers, andtransceivers. The LVDS drivers provide the higher drive current required by B-LVDS and M-LVDS toaccommodate the bus loading.

The driver requires series terminations for better signal quality and to control voltage swing. Terminationis also required at both ends of the bus, since the driver can be located anywhere on the bus. TheSmartFusion2 MSIOD has an internal circuit isolation, and the bus isolation should be taken care of inthe design external to the device when using M-LVDS.

Mini-LVDSA serial, intra-flat panel solution that serves as an interface between the timing control function and anLCD source driver.

I/O Programmable FeaturesSmartFusion2 devices support different I/O programmable features for MSIO, MSIOD, and DDRIO. EachI/O pair (P and N) supports the following programmable features:

• Programmable Input Delay

• Programmable Slew Rate Control

• Programmable Weak Pull-Up/Pull-Down

• Programmable Schmitt Trigger Input and Receiver

• Configurable ODT and Driver Impedance

These features can be configured using Libero Soc or in a PDC file. Refer to the Libero SoC User Guidefor more details.

Table 5-3 on page 101 lists all the features supported for single-ended and differential I/Os.

100 Revision 4



Programmable Input DelayEach I/O, when configured as an input, can be programmed with different input delays. The input delay is calculated using:

Delay = D + N x 0.1 ns

EQ 1

where,

N ranges from 0 to 63.

D is the intrinsic delay or circuit delay of an input without additional delay, when N is 0. The total delay range is between D ns to D + 6.3 ns.

Hence, there are 64 input delay values which can be chosen and configured using then MultiView Navigator (MVN) of Libero SoC for MSIO, MSIOD, and DDRIO.

Note: Input delays could be used for hold time improvement for the input register by increasing input pin to input register delay.

Table 5-3 • SmartFusion2 I/O Features

I/O Features

I/Os

MSIO MSIOD DDRIO

Single-Ended Transmitter

Programmable drive strength Yes Yes Yes

Programmable weak pull-up and pull-down Yes Yes Yes

Configurable ODT Yes Yes Yes

Hot insertion capable Yes – –

Bus keeper Yes Yes Yes

I/O state control in Low power mode Yes Yes Yes

LVTTL/LVCMOS 3.3 V outputs compatible with external 5 V TTL inputs Yes – –

Pre-emphasis capability – Yes -

Programmable slew rate – – Yes

Single-Ended Receiver

5 V tolerant with minimal use of external circuitry Yes Yes –

Schmitt receiver Yes Yes Yes

LPE (Signature mode and Activity mode) Yes Yes Yes

Programmable input delay Yes Yes Yes


Differential Transmitter

Programmable weak pull-up and pull-down Yes Yes Yes

Configurable ODT Yes Yes Yes


Differential Receiver

100 Ω differential ODT Yes Yes –

Schmitt receiver Yes Yes Yes

LPE (Signature mode and Activity mode) Yes Yes Yes

Programmable input delay Yes Yes Yes

Programmable Slew rate – – Yes

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I/Os

Programmable Slew Rate ControlEach I/O has a slew rate control that sets the output switching rate for LVCMOS1.5 /1.8 / 2.5 andDDR1/2/3 output standards. There are three slew rate controls provided by the MVN that can beconfigured for a particular I/O standard for DDRIO.

There is no slew rate control for MSIO and MSIOD.

Programmable Weak Pull-Up/Pull-DownThe MSIO has eight programmable drive strengths supported for LVCMOS 1.8, LVCMOS 2.5, LVCMOS 3.3, and LVTTL 3.3 I/O standards, configurable using MVN in Libero SoC.

DDRIOs can be programmed to weak pull-up and weak pull-down, which are mutually exclusive, andweakly hold the output to either VDDI or GND, respectively. Table 5-5 shows the three settings forweak pull-up/pull-down provided by Libero SoC.

Programmable Schmitt Trigger Input and ReceiverThe DDRIO input can be configured as a Schmitt trigger or single-ended receiver with support for different DDRIO standards.

Following are the programmable features of the DDRIO receiver:

• Schmitt receiver, LVCMOS 2.5 V/1.8 V

• Schmitt receiver, LVCMOS 1.5 V/1.2 V

• Schmitt receiver, LVCMOS 1.5 V/1.2 V, delayed

• Schmitt receiver, LVCMOS 2.5 V/1.8 V, delayed

• Receiver, LVCMOS 1.5 V/1.2 V

• Receiver, LVCMOS 2.5 V/1.8 V

• Receiver, LVCMOS 1.5 V/1.2 V, delayed

• Receiver, LVCMOS 2.5 V/1.8 V, delayed

• Receiver, pseudo-differential / voltage reference (DDR1/SSTL25, DDR2/SSTL18, DDR3/SSTL15, LPDDR, HSTL)

• Receiver, true differential (DDR1/SSTL25, DDR2/SSTL18, DDR3/SSTL15, LPDDR)

• Receiver, pseudo-differential / voltage reference, delayed

• Receiver, true differential, delayed

For MSIO/MSIOD, the Schmitt trigger is available for the LVTTL, LVCMOS, and 3.3 V PCI I/O standards.

This feature can be enabled/disabled by using a Physical Design Constraints (PDC) command or byusing MVN in Libero SoC. Schmitt Trigger is disabled by default.

Table 5-4 • Slew Rate Control

Slew Rate Options

0 LVCMOS 2.5, DDR1

1 LVCMOS 1.8, DDR2

2 LVCMOS 1.5, DDR3

Table 5-5 • Weak Pull-Up/Pull-Down

Weak Pull-Up/Pull-Down Options

0 Disable pull-up or pull-down

1 Enable pull-up

2 Enable pull-down

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Programmable Output Drive StrengthThe DDRIO can use fixed impedance calibration for different drive strengths, and these values can be programmed using MVN in Libero SoC for the selected I/O standard. Table 5-6 shows the recommended values. PCODE<5:0> and NCODE<5:0> are registers accessible through the dedicated APB configuration interface.

Table 5-6 • DDRIO Output Drive Strength

I/O Standard NCODE PCODE

DDR1 Full Drive/SSTL2 II 42 44

DDR1 Half Drive/SSTL2 I 42 44

DDR2 Full Drive/SSTL18 II 58 61

DDR2 Half Drive/SSTL18 I 58 61

LPDDR Full Drive 58 61

LPDDR Half Drive 58 61

HSTL II 53 56

HSTL I 53 56

LVCMOS25 24 mA 42 44








LVCMOS25 8 mA 42 44

LVCMOS25 6 mA 42 44

LVCMOS25 4 mA 42 44

LVCMOS25 2 mA 42 44









LVCMOS18 8 mA 58 61

LVCMOS18 6 mA 58 61

LVCMOS18 4 mA 58 61

LVCMOS18 2 mA 58 61

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I/Os

Configurable ODT and Driver ImpedanceDDRIO has an ODT or transmitter impedance feature which is calibrated depending on the I/O standard.If the impedance feature is enabled, impedance can be programmed to the desired value in three ways.Figure 5-2 on page 96 shows the impedance configuration for DDRIO.

• Calibrate the ODT/Driver Impedance with Calibration Block

• Calibrate the ODT/Driver Impedance with Fixed Calibration Codes

• Configure the ODT/Driver Impedance Statically to Desired Value Directly

There are two DDRIO calibration blocks in each SmartFusion2 M2S050 device. The MDDR and FDDRhave a DDRIO calibration block. Each calibration block calibrates ODT/driver impedance for all 44DDRIO pairs (P, N).

Calibrate the ODT/Driver Impedance with Calibration BlockThe I/O calibration block calibrates the I/O drivers to an external resistor. The impedance control is usedto identify the digital values PCODE<5:0> and NCODE<5:0>. These values are fed to thepull-up/pull-down reference network to match the impedance with an external resistor. Once it matchesthe PCODE and NCODE registers, they are latched and sent to the drivers.

The calibrated impedance value can be configured statically by enabling ODT_STATIC, or dynamicallyby enabling ODT_DYN. ODT_STATIC selects the ODT value set in flash configuration bits programmedduring power-on, whereas ODT_DYN selects the ODT value provided at run time. Refer to the MDDR I/OCalibration Control register of the "System Register Block" in the SmartFusion2 MicrocontrollerSubsystem User Guide for enabling the calibration block.

Table 5-7 on page 105 shows the ODT calibrated impedances for the listed I/O standards.





LVCMOS15 8 mA 53 56

LVCMOS15 6 mA 53 56

LVCMOS15 4 mA 53 56

LVCMOS15 2 mA 53 56

LVCMOS12 8 mA 40 42

LVCMOS12 6 mA 40 42

LVCMOS12 4 mA 40 42

LVCMOS12 2 mA 40 42

Table 5-6 • DDRIO Output Drive Strength (continued)

I/O Standard NCODE PCODE

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To calibrate driver or transmitter impedance for an I/O, configure it to the calibrated impedance accordingto the flash configuration bits for the appropriate I/O standard. Recommended reference resistor valuesused for calibration and the calibrated impedance values are shown in Table 5-8.

Table 5-7 • ODT Calibrated Impedance

Driver Mode Reference Resistor (Ω) ODT Calibrated Impedance

ODT, DDR3/SSTL 1.5, 1.5 V

240 120

240 60

240 40

240 30

240 20

ODT, DDR2/SSTL 1.8, 1.8 V

150 150

150 75

150 50

ODT, HSTL 191 47.8

Table 5-8 • Driver/Transmitter Calibrated Impedance

Driver Mode Reference Resistor (Ohm) Transmitter Calibrated Impedance

Transmitter, DDR3 SSTL 1.5 240 34

240 40


150 42


150 42

Transmitter, LPDDR SSTL 1.8 150 20

150 42

Transmitter, HSTL 1.5 191 25.5

191 47.8

LVCMOS 1.2 and 1.5 300 75

300 66.7

300 50

LVCMOS 1.8 150 75

150 50

150 33

150 25

LVCMOS 2.5 150 75

150 50

150 33

150 25

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I/Os

Calibrate the ODT/Driver Impedance with Fixed Calibration CodesFixed calibration codes can be configured through the PCODE<5:0> and NCODE<5:0> registers. Libero SoC recommends using the fixed calibration codes provided in Table 5-6.

Configure the ODT/Driver Impedance Statically to Desired Value DirectlyThe ODT/driver can be calibrated to a desired value by providing PCODE<5:0> and NCODE<5:0> values directly through the dedicated APB configuration interface FIC2. In this configuration, the values are overwritten with existing values. Refer to the MDDR I/O Calibration Control register of the "System Register Block" in the SmartFusion2 Microcontroller Subsystem User Guide for configuring the PCODE and NCODE values. For MSIO and MSIOD, the ODT values shown in Table 5-9 are configured based on I/O standard.

I/O External TerminationIf ODT is not used, I/O standards require termination for better signal integrity. Voltage referencedstandards generally have a serial (driver) and parallel (receiver) termination whereas differentialstandards have only a parallel termination (receiver). Table 5-10 shows external termination schemesfor the I/O standards supported for DDRIO, MSIO, and MSIOD when the ODT/driver impedancecalibration feature is not used.

Table 5-9 • ODT Values

Standards ODT (MSIO) (in Ohms) ODT (MSIOD) (in Ohms)

LVDS 3.3 V 100 NA

LVDS 2.5 V 100 100

BLVDS 100 100

RLVDS 100 100

SSTL 2I and SSTL 2II 50 - 75 - 150 50 - 75 - 150

SSTL 18I and SSTL 18II 50 - 75 - 150 50 - 75 - 150

HSTL I 50 - 75 - 150 50 - 75 - 150

Differential SSTL 2I and SSTL 2II 100 100

Differential SSTL 18I and SSTL 18II 100 100

Table 5-10 • Termination Schemes

I/O Standard External Termination Scheme

SSTL 1.5 single-ended (Class I & II)

Single-ended SSTL I/O standard terminationSSTL 1.8 single-ended (Class I & II)

SSTL 2 single-ended (Class II)

HSTL 1.5 single-ended (Class II) Single-ended HSTL I/O standard termination

SSTL 2.5 differential (Class I & II)

Differential SSTL I/O standard terminationSSTL 1.8 differential (Class I & II)

SSTL 1.5 differential (Class I & II)

HSTL 1.5 differential (Class II) Differential HSTL I/O standard termination

LVCMOS 2.5

No external termination requiredLVCMOS 1.8

LVCMOS 1.5

LVCMOS 1.2

LVDS 100 Ohm, parallel termination

MLVDS 100 Ohm, parallel termination

BLVDS 100 Ohm, parallel termination

RLVDS 100 Ohm, parallel termination

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Low Power Signature Mode and Activity ModeThere are two modes for exiting Low power mode: Signature mode and Activity mode. Flashconfiguration bits are used to configure I/Os to be disabled in Low power mode, Signature mode, andActivity mode. Each DDRIO has four options for configuring and controlling low power exit:

• I/O not designated for low power exit monitoring

• I/O designated for low power activity monitoring

• I/O designated for low power signature, look for 0

• I/O designated for low power signature, look for 1

Signature ModeOnce entering Low power mode, every I/O designated as a signature I/O becomes input only. All otherI/Os are tristated, held by bus hold, or weakly pulled-up/pulled-down. A pattern must be driven to thesignature I/O set during configuration, checking for 0 or 1, depending on the option selected. If all theconfigured signature values match the values at the pins, the device exits Low power mode.

Activity ModeIn Activity mode, the value at the pin of the activity I/O is latched before going to Low power mode. Whenyou configure I/Os for low power activity monitoring, the device exits Low power mode if any activity isdetected.

Bus KeeperThe main function is to weakly hold the signal on an I/O pin at its last driven state, holding it at a validlevel with minimal power dissipation. The bus keeper circuitry also pulls undriven pins away from theinput threshold voltage where noise can cause unintended oscillation. Bus Keeper is only available inFlash*Freeze mode (not during normal operation). This feature is activated by setting LAST_VALUEoption for the selected I/O pad under I/O state in Flash*Freeze mode column in the I/O attribute editor.Figure 5-5 shows the configuration in I/O editor.

For an unused I/O, both input buffer and output buffer are disabled and weak pull-up is enabled. When I/Ois tristated, the weak pull-up will be disabled.

5 V Input Tolerance and Output Driving Compatibility (only MSIO)

5 V Input ToleranceI/Os can support 5 V input tolerance when LVTTL 3.3 V, LVCMOS 3.3 V, and LVCMOS 2.5 Vconfigurations are used. There are three recommended solutions for achieving 5 V receiver tolerance. Allthe solutions meet a common requirement of limiting the voltage at the input to 3.45 V or less. In fact, theI/O absolute maximum voltage rating is 3.45 V, and any voltage above 3.45 V may cause long-term gateoxide failures.

Mini LVDS 100 Ohm, parallel termination

LVPECL 100 Ohm, parallel termination

Note: For more information on electrical characteristics, refer to the SmartFusion2 SoC FPGA DataSheet.

Table 5-10 • Termination Schemes (continued)

Figure 5-5 • Bus Keeper Configuration in I/O Editor

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I/Os

Solution 1 The board-level design must ensure that the reflected waveform at the pad does not exceed the limitsprovided in the recommended operating conditions in the datasheet. This is a requirement to ensurelong-term reliability.

This scheme also works for a 3.3 V PCI configuration, but the internal diode should not be used forclamping, and the voltage must be limited by two external resistors. Relying on diode clamping wouldcreate an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V.

This solution requires two board resistors. Here are some examples of possible resistor values based ona simplified simulation model with no line effects and 10 Ohm transmitter output resistance, where

Rtx_out_high = [VCCI – VOH] / IOH and Rtx_out_low = VOL / IOL).

EQ 2

Example 1 (high speed, high current):

Rtx_out_high = Rtx_out_low = 10 Ω

R1 = 36 Ω (±5%), P(r1)min = 0.069 Ω

R2 = 82 Ω (±5%), P(r2)min = 0.158 Ω

Imax_tx = 5.5 V / (82 × 0.95 + 36 × 0.95 + 10) = 45.04 mA

tRISE = tFALL = 0.85 ns at C_pad_load = 10 pF (includes up to 25% safety margin)

tRISE = tFALL = 4 ns at C_pad_load = 50 pF (includes up to 25% safety margin)

Example 2 (low-medium speed, medium current):

Rtx_out_high = Rtx_out_low = 10 Ω

R1 = 220 Ω (±5%), P(r1)min = 0.018 Ω

R2 = 390 Ω (±5%), P(r2)min = 0.032 Ω

Imax_tx = 5.5 V / (220 × 0.95 + 390 × 0.95 + 10) = 9.17 mA



Other values of resistors are also allowed as long as the resistors are sized appropriately to limit thevoltage at the receiving end to 2.5 V < Vin(rx) < 3.6 V when the transmitter sends a logic 1. This range ofVin_dc(rx) must be assured for any combination of transmitter supply (5 V ± 0.5 V), transmitter outputresistance, and board resistor tolerances.

Figure 5-6 • 5 V Input Tolerance Solution 1

5.5 V

3.3 V

Rext1

Rext2

Requires two board resistorsLVCMOS 3.3 V I/Os

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Solution 2The board-level design must ensure that the reflected waveform at the pad does not exceed the voltageovershoot/undershoot limits provided in the datasheet. This is a requirement to ensure long-termreliability. This scheme also works for a 3.3 V PCI configuration, but the internal diode should not be usedfor clamping, and the voltage must be limited by the external resistors and Zener. Relying on the diodeclamping would create an excessive pad DC voltage of 3 V + 0.7 V = 4 V.

Solution 3The board-level design must ensure that the reflected waveform at the pad does not exceed the voltageovershoot/undershoot limits provided in the datasheet. This is a requirement to ensure long-termreliability.

5 V Output Driving CompatibilitySmartFusion2 I/Os must be set to 3.3 V LVTTL or 3.3 V LVCMOS mode to reliably drive 5 V TTLreceivers. It is also critical that there is NO external I/O pull-up resistor to 5 V, since this resistor wouldpull the I/O pad voltage beyond the 3.6 V absolute maximum value and consequently cause damage tothe I/O. When set to 3.3 V LVTTL or 3.3 V LVCMOS mode, the I/Os can directly drive signals into 5 V TTLreceivers. In fact, VOL = 0.4 V and VOH = 2.4 V in both 3.3 V LVTTL and 3.3 V LVCMOS modes exceedsthe VIL = 0.8 V and VIH = 2 V level requirements of 5 V TTL receivers. Therefore, level 1 and level 0 arerecognized correctly by 5 V TTL receivers.


5.5 V 3.3 V

Rex

Requires one board resistors,one Zener 3.3 V diode, LVCMOS 3.3 V I/Os

Zener3.3 V


5.5 V 2.5 V2.5 V

Rex

On-chipclampdiode

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I/Os

Other I/O Features

Flash*Freeze ModeUser logic in the FPGA fabric may request that the device enter Flash*Freeze mode by means of asystem service request via the USI interface. During Flash*Freeze mode, a number of resources on theSmartFusion2 devices are put into a low power state using the various power management hooksavailable for each resource. At design entry time, you can select which functional blocks go into lowpower state during Flash*Freeze mode.

Intelligent Wake-Up SmartFusion2 devices have two ways to implement wake-up from Flash*Freeze mode:

• Real-time counter (RTC) timeout

• I/O cell wake-up

In the RTC timeout method, the timeout value is set in the RTC before entering Flash*Freeze mode. Inthe I/O cell wake-up method, any activity on a specified input or matching a user defined pattern value(signature) on a number of inputs wakes up the device

I/Os in Conjunction with Fabric, MDDR/FDDR, and MSS Peripherals

DDRIOs with MDDR/FDDRIf you select MDDR/FDDR, Libero SoC automatically connects MDDR/FDDR signals to the DDRIOs. Depending on the memory configuration, only the required DDRIOs are used by Libero SoC. The unused DDRIO are available to you to connect to the FPGA fabric.

DDRIOs with FabricIf you do not select MDDR/FDDR, DDRIOs are available to the FPGA fabric. DDRIOs must be manuallyconfigured in Libero SoC.

MSIOs/MSIODs with MSS PeripheralsIf MSS peripherals are selected, Libero SoC automatically connects MSS peripheral signals to either MSIOs or to the MSIODs. The unused MSIOs or MSIODs are available to connect to the FPGA fabric.

MSIOs/MSIODs with FabricIf MSS peripherals are not selected, MSIOs/MSIODs are available to the FPGA fabric. MSIOs and MSIOD must be manually configured in Libero SoC.

JTAG I/OThe system controller implements the functionality of a JTAG slave, with IEEE 1532 support, which alsoimplies IEEE 1149.1 compliance. JTAG communicates with the system controller using a Commandregister that conveys the JTAG instruction to be executed and a 128-bit data I/O buffer that transfers anyassociated data. The TAP controller uses 8-bit instructions consistent with previous Microsemi families.

The JTAG pins can be run at any voltage from 1.5 V to 3.3 V (nominal). Core voltage must also bepowered for the JTAG state machine to operate, even if the device is in Bypass mode. VJTAG alone isinsufficient. Both VJTAG and core voltage to the SmartFusion2 part must be supplied to allow JTAGsignals to transit the SmartFusion2 device. Isolating the JTAG power supply in a separate I/O bank givesgreater flexibility with supply selection and simplifies power supply and PCB design. If the JTAG interfaceis not used and not planned for use, the VJTAG pin together with the TRSTB pin should be tied to GND.

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Table 5-11 • JTAG Pin Description

Name Type Bus Size Description

JTAGSEL In 1 JTAG controller selection

Depending on the state of the JTAGSEL pin, an external JTAG controller detects the FPGA fabric TAP/auxiliary TAP (High) or the Cortex-M3 processor JTAG debug interface (Low).

The JTAGSEL pin should be connected to an external pull-up resistor such that the default configuration selects the FPGA fabric TAP.

TCK In 1 Test clock

Serial input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal pull-up/-down resistor. If JTAG is not used, Microsemi recommends tying it off TCK to GND or VJTAG through a resistor placed close to the FPGA pin. This prevents.

JTAG operation in case TMS enters an undesired state.

Note that to operate at all VJTAG voltages, 500 Ohm to 1 KOhm satisfy the requirements.

Refer to Table 5-12 for more information.

TDI In 1 Test data

Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an internal weak pull-up resistor on the TDI pin.

TDO Out 1 Test data

Serial output for JTAG boundary scan, ISP, and UJTAG usage.

TMS 1 Test mode select

The TMS pin controls the use of the IEEE1532 boundary scan pins (TCK, TDI, TDO, and TRSTB). There is an internal weak pull-up resistor on the TMS pin.

TRSTB 1 Boundary scan reset pin. The TRSTB pin functions as an active low input to asynchronously initialize (or reset) the boundary scan circuitry. There is an internal weak pull-up resistor on the TRSTB pin. If JTAG is not used, an external pull-down resistor could be included to ensure the TAP is held in Reset mode. The resistor values must be chosen from Table 5-12 and must satisfy the parallel resistance value requirement. The values in Table 5-12 correspond to the resistor recommended when a single device is used. The values correspond to the equivalent parallel resistor when multiple devices are connected via a JTAG chain.

In critical applications, an upset in the JTAG circuit could allow entering an undesired JTAG state. In such cases, Microsemi recommends tying off TRSTB to GND through a resistor placed close to the FPGA pin.

The TRSTB pin also resets the serial wire JTAG debug port (SWJ-DP) circuitry within the Cortex-M3 processor.

Table 5-12 • Recommended Tie-Off Values for the TCK and TRST Pins

VJTAG Tie-Off Resistance1, 2

VJTAG at 3.3 V 200 Ohm to 1 KOhm




Notes:

1. The TCK pin can be pulled up/down.

2. The TRSTB pin can only be pulled down.

3. Equivalent parallel resistance if more than one device is on JTAG chain.

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I/Os

Dedicated I/OSmartFusion2 devices have following dedicated I/Os:

• Device Reset I/O

• Crystal Oscillator I/O

• SERDES I/O

Device Reset I/OSmartFusion2 devices have a dedicated input reset; anytime reset is asserted the whole chip is reset.The device reset feeds the system controller, which generates the system reset for the reset controller toreset the entire device. Figure 5-9 shows the full chip reset flow from device reset.

Asserting device reset causes a SmartFusion2 device to exit Flash*Freeze mode; this is very useful inrecovering from a situation where the device enters Flash*Freeze mode without correct configuration ofthe Flash*Freeze exit mechanism in the I/O cells or in the real-time clock (RTC). This can be considereda cold reset, as it resets all parts of the device. Generation of different reset signals is explained in the“Reset Controller” chapter of the SmartFusion2 Microcontroller Subsystem User's Guide.

Port List and I/O Pins

Crystal Oscillator I/OSmartFusion2 devices have two dedicated I/O pins (EXTLOSC and XTLOSC) connected to each on-chip crystal oscillator. These I/O pins can be connected to a crystal, ceramic resonator, or an RC circuit.

The detailed configuration of these pins and operational modes is explained in the SmartFusion2 Clocking Resources User’s Guide.

Figure 5-9 • Chip Level Resets From Device Reset

System Controller Reset ControllerDEVRST_N

System Resets Chip Level Resets

Table 5-13 • Device Reset I/O Pin

Pin Type I/O Description

DEVRST_N Analog Input Device reset, asserted low, and powered by VPP

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Crystal Oscillator I/O Pins

SERDES I/OThe SERDES I/Os available in SmartFusion2 devices are dedicated to high speed serial communicationprotocols. For more information refer to the SERDES section in the SmartFusion2 SoC FPGA HighSpeed Serial Interfaces User's Guide. The SERDES I/O supports protocols such as PCI Express 2.0,XAUI, serial gigabit media independent interface (SGMII), serial rapid I/O (SRIO), and any user-definedhigh speed serial protocol implementation in fabric. These protocols access the SERDES lanes throughthe physical media attachment (PMA) and physical coding sub layer (PCS) of SERDES interface. Thedetailed configuration of the SERDES interface for various protocols is explained in the “SERDESIFBlock” chapter of the SmartFusion2 SoC FPGA High Speed Serial Interfaces User's Guide. This sectiondescribes the SERDES I/O pins, SERDES I/O banks, SERDES I/O standards, and board-level designconsiderations available.

SERDES I/O BanksThe SERDES I/Os reside in the dedicated I/O banks. The number of SERDES I/Os depends on thedevice size and pin count. For example, the M2S050 device has two SERDES_IFs (SERDES_IF0 andSERDES_IF1), which reside on two I/O banks (bank #6 and bank #9) out of ten I/O banks. The M2S010device has one SERDES_IF (SERDES_IF0), which resides on one I/O bank (bank #5).

Refer to the SmartFusion2 SoC FPGA DataSheet for details on I/O bank locations and I/O electricalspecifications.

SERDES I/O PinsEach SERDES interface in the SmartFusion2 device has four SERDES I/O data lanes or 16 SERDESI/Os available for accessing the SERDES interface (SERDESIF block). Each data lane has two pairs ofdifferential signals: one for transmit data (TxDP, TxDN) and other for receive data (RxDP, RxDN). DataIanes are multiplexed to support different serial protocols and scalable to various link widths—x1, x2, andx4. These settings can be configured in the SERDES_IF macro using Libero SoC design software. EachSERDES_IF has two sets of dedicated power, clock, and reference signals. One set for data lane 0 and1 and another for data lane 2 and 3.

Refer to the SmartFusion2 Pin Descriptions for details on SERDES I/O and power pin names anddescription.

Glossary

Acronyms

DDRIODouble data rate input output

MDDRMicrocontroller subsystem double data rate

FDDRFabric double data rate

IOAInput output analog

Table 5-14 • Crystal Oscillator I/O Pins

Pin Type I/O Description

EXTLOSC Analog Input Dedicated pin for a crystal external RC network connection.

XTLOSC Analog Input Dedicated pin to be used only for crystal connection.

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I/Os

IODInput output digital

LPDDRLow power double data rate memory

ODTOn-die termination

HSTLHigh-speed transceiver logic

SSTLStub series terminated logic

LVDSBus LVDS

ESDElectrostatic discharge protection

HSTLHigh-speed transceiver logic

LPELow power exit

LVDSLow-voltage differential signal

LVPECLLow-voltage positive emitter coupled logic

LVTTLLow voltage transistor transistor logic

MLVDSMultipoint LVDS

MSIOMulti-standard I/O

MVNMultiView Navigator

ODTOn-die termination

RSDSReduced swing differential signaling

SSTLStub series terminated logic

SERDESSerializer/deserializer

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Terminology

Bus KeeperHolds the signal on an I/O pin at its last driven state.

Hot InsertionCapability to connect I/O to external circuitry even after power-up.

Low Power ExitLogic for the chip to come out from low power state.

List of ChangesThe following table lists critical changes that were made in this chapter.

Date Changes Page


Updated Figure 5-1 • I/O Interconnection (SAR 49582). 94

Updated Figure 5-3 • SmartFusion2 (M2S050T-FG896) I/O Bank Location and Naming and Figure 5-4 • SmartFusion2 (M2S010T-FG484) I/O Bank Location and Naming (SAR 47366).

97

Updated the "B-LVDS/M-LVDS" section (SAR 45694). 100

Updated the "SERDES I/O Pins" section to refer to the SmartFusion2 Pin Descriptions and removed the Table 5-15 • SERDES I/O Pins Descriptions (SAR 50634).

113

Updated the "Bus Keeper" section, and Figure 5-5 • Bus Keeper Configuration in I/O Editor is new (SAR 49802).

107


Restructured the document (SAR 45831). NA

Updated Table 5-7 and Table 5-8 (SAR 43407). 105 and 105

Updated the "Device Reset I/O" section (SAR 43545). 112

Updated "Receive Buffer" section (SAR 43914). 95

Updated "I/O Banks" section (SAR 43914). 97

Modified Table 5-2, Table 5-3, and Table 5-11 (SAR 43914). 98

Modified "SERDES I/O" section (SAR 43914). 113

Revision 1(November 2012)

Updated Figure 5-3 and Figure 5-4 (SARs 41791 and 42467). 97

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A – List of Changes

The following table lists critical changes that were made in each revision of the chapter in the user guide.

Date Changed Chapters

List of Changes on page


Updated the "Fabric Architecture" chapter. 18

Updated the "I/Os" chapter. 115


Updated the "Fabric Architecture" chapter (SAR 47579). 18

Table 2-1 • Number of LSRAM 18K Blocks Available per Device is modified (SAR 47579).

45

Table 3-2 • Port List for uSRAM is modified (SAR 47579). 68

Table 4-2 • Truth Table for Propagating Operand D of the Adder or Accumulator is modified (SAR 47579).

92

Updated "Interface Logic Element" section (SAR 47435). 18

Figure 2-12 is updated (SAR 47619). 45

Updated "Features" section (SAR 48006). 92

Updated the state of unused I/O pins (SAR 44937), broken link to the ARM Cortex-M3 processor UG fixed (SAR 43407), reference describing ODT configuration corrected (SAR 48164), and reference to ODT table corrected (SAR 48167).

NA


Restructured the document (SAR 41767). 18

Restructured the chapter (SAR 45272). 45



Restructured the document (SAR 45831). 115

Updated "Receive Buffer" section (SAR 43914). 95

Updated "I/O Banks" section (SAR 43914). 97

Modified Table 5-2, Table 5-3, and Table 5-11 (SAR 43914). NA

Modified "SERDES I/O" section (SAR 43914). 113

Updated Figure 5-3 and Figure 5-4 (SARs 41791 and 42467). 97


Updated "Timing Diagrams" section (SAR 41640). 29

Updated "Read Operation" section (SAR 41640). 55

Modified Table 4-3 (SAR 41834). 76

Updated "Global Routing Network" section (SAR 41770). 73

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B – Product Support

Microsemi SoC Products Group backs its products with various support services, including CustomerService, Customer Technical Support Center, a website, electronic mail, and worldwide sales offices.This appendix contains information about contacting Microsemi SoC Products Group and using thesesupport services.

Customer ServiceContact Customer Service for non-technical product support, such as product pricing, product upgrades,update information, order status, and authorization.

From North America, call 800.262.1060From the rest of the world, call 650.318.4460Fax, from anywhere in the world, 408.643.6913

Customer Technical Support CenterMicrosemi SoC Products Group staffs its Customer Technical Support Center with highly skilledengineers who can help answer your hardware, software, and design questions about Microsemi SoCProducts. The Customer Technical Support Center spends a great deal of time creating applicationnotes, answers to common design cycle questions, documentation of known issues, and various FAQs.So, before you contact us, please visit our online resources. It is very likely we have already answeredyour questions.

Technical SupportVisit the Customer Support website (www.microsemi.com/soc/support/search/default.aspx) for more information and support. Many answers available on the searchable web resource include diagrams, illustrations, and links to other resources on the website.

WebsiteYou can browse a variety of technical and non-technical information on the SoC home page, at www.microsemi.com/soc.

Contacting the Customer Technical Support CenterHighly skilled engineers staff the Technical Support Center. The Technical Support Center can becontacted by email or through the Microsemi SoC Products Group website.

EmailYou can communicate your technical questions to our email address and receive answers back by email,fax, or phone. Also, if you have design problems, you can email your design files to receive assistance.We constantly monitor the email account throughout the day. When sending your request to us, pleasebe sure to include your full name, company name, and your contact information for efficient processing ofyour request.

The technical support email address is [email protected].

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Product Support

My CasesMicrosemi SoC Products Group customers may submit and track technical cases online by going to My Cases.

Outside the U.S.Customers needing assistance outside the US time zones can either contact technical support via email([email protected]) or contact a local sales office. Sales office listings can be found atwww.microsemi.com/soc/company/contact/default.aspx.

ITAR Technical SupportFor technical support on RH and RT FPGAs that are regulated by International Traffic in Arms Regulations (ITAR), contact us via [email protected]. Alternatively, within My Cases, select Yes in the ITAR drop-down list. For a complete list of ITAR-regulated Microsemi FPGAs, visit the ITAR web page.

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© 2013 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks ofMicrosemi Corporation. All other trademarks and service marks are the property of their respective owners.

Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductorsolutions for: aerospace, defense and security; enterprise and communications; and industrialand alternative energy markets. Products include high-performance, high-reliability analogand RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, andcomplete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more atwww.microsemi.com.

Microsemi Corporate HeadquartersOne Enterprise, Aliso Viejo CA 92656 USAWithin the USA: +1 (949) 380-6100Sales: +1 (949) 380-6136Fax: +1 (949) 215-4996

http://www.microsemi.com