External Use

TM

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, MagniiV, mobileGT, PEG, PowerQUICC, Processor

Expert, QorIQ, QorIQ Qonverge, Qorivva, Ready Play, SafeAssure, the SafeAssure logo, StarCore, Symphony, VortiQa, Vybrid and Xtrinsic are trademarks of Freescale Semiconctor, Inc., Reg.

U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MXC, Platform in a Package, QUICC Engine, SMARTMOS, Tower, TurboLink and UMEMS are trademarks of

Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. ARM, Cortex and TrustZone are trademark(s) or registered trademarks of ARM Ltd or

its subsidiaries in the EU and/or elsewhere. All rights reserved. © 2015 Freescale Semiconductor, Inc.

Smart Technology Choices and

Leadership i.MX Applications

Processors

Shanghai FD SOI Forum

S E P T . 1 5 . 2 0 1 5

Ronald Martino | Vice President, i.MX Applications Processor

Business and Advanced Technology Adoption

TM

External Use 1

Smart WorldSECURE, CONNECTED, LOW-POWER, SCALABLE

Technology Innovations

Advanced NVM, RF, Mixed Signal Analog,

and Sensors integration

Powerful, Secure, Low-Power

MCUs & Applications Processors

System Miniaturization & Advanced Packaging

SolutionsEmbedded Processing

Connectivity Protocols

Multi-Sensing Applications

Video | Image | Graphics | Voice

SoftwareEase-of-use

Open-source

Security

Device Management

Professional Services

Internet of Things SmartHomes

SmartHighways

SmartEnergy

SmartCities

Connected

World

Connected

Cars

Smart

Homes

Smart

Hospitals

Smart

Industrial

TM

External Use 2

2007 2008 2009 2010 2011 2012 2013 2014 2015

i.MX i.MX Auto

2010My Ford Touch Introduction

Powered by i.MX

2012eReader

Inventory Correction

Over 200M i.MX SOCs

shipped to date

Over 35M vehicles enabled

with i.MX since 2007

Leader in eReaders and

Auto Infotainment MPU

i.MX Driving Explosive Growth in Smart Vehicles &

Smart Devices

TM

External Use 3

Scalable series of NINE ARM-based SoC Families

i.MX 6Solo i.MX 6Dual i.MX 6Quad

i.MX

6Solo Family

i.MX

6Dual Family

i.MX

6Quad Family

i.MX 6DualLite

i.MX

6DualLite

Family

i.MX

6SoloLite

Family

i.MX 6SoloX

Pin-to-pin Compatible

Software Compatible

i.MX

6SoloX

Family

i.MX

6QuadPlus

Family

i.MX 6DualPlus

i.MX

6DualPlus

Family

i.MX

6UltraLite

Family

i.MX 6QuadPlusi.MX 6SoloLitei.MX 6UltraLite

Expanded series for performance, power efficiency and lower BOM

i.MX 6 Series: Supreme Scalability and Flexibility

Leverage One Design Into Diverse Product Portfolio

TM

External Use 4

Recently Announced i.MX 7D & 7S Advantages

• Advanced Heterogeneous

Architecture

− Single and Dual Cortex-A7

Core up to 1GHz

− Cortex-M4 up to 266MHz

Offload Tasks

Optimize Power

Increase Security

• Unmatched Power Efficiency

− 3x improvement in Power Efficiency

vs i.MX 6

− 100 uW/MHz for Cortex-A7

− 70 uW/MHz for Cortex-M4

− One third the power consumed in

the Low Power suspend mode

(250uW) vs i.MX 6

• Enabling Flexible High

Speed Connectivity

− PCI-e v2.1

− Dual Gbit Ethernet with AVB

− DDR QuadSPI support

− eMMC 5.0

• Complete Security Infrastructure

− Secure Boot

− Crypto H/W Acceleration

− Internal and External Tamper

Detection

− Secure RAM

− DPA attack Resistance

− Secure JTAG

Bus Fabric

Cortex-A7 Cortex-A7Corte

x-M4

TM

External Use 5

Processing Power Efficiency

0

0.4

0.8

1.2

1.6

2

2010 2012 2014 2016 2017 2018

Ac

tive

Po

we

r (

mW

/MH

z )

ARM® Cortex®-M0+ ARM Cortex-M4 ARM Cortex-A9/Ax

28nm for MPU & MCU

Core-only

TM

External Use 6

i.MX Processor RoadmapTwo New i.MX Platforms Based on 28nm FD SOI Technology

i.MX 7 series

i.MX 8 seriesAdvanced Graphics & Performance

Power Efficiency

ARM ® v8-A

ARM® v7-A

ARM® v7-A

i.MX 6QuadPlus

i.MX 6Dual

i.MX 6Solo

i.MX 6DualLite

i.MX 6SoloLite

i.MX 6SoloX

i.MX 6UltraLite

i.MX 6DualPlus

i.MX 6Quad

TM

External Use 7

End Nodes TODAY

Low-

power

Core

Analog

NVM

Narrow-band

RF

Wide-band

RF

Sensors

(MEMS)

Antennas BatteriesPower Management

(PMIC/PMU)

Optics (Camera)

MCU

High-

Performance

Core

Analog

MPU

TM

External Use 8

Increasing Integration of Diverse Components

Diversification

Min

iatu

riza

tio

n

180nm

130nm

90nm

65nm

40nm

28nm

14nm...

RFPrecision

AnalogSensorsNVM BiochipsHV

Leading-edge

process nodes (45, 32…14FF)

driven mainly by

digital SoC

Longer-lasting

shrink nodes (40, 28…??)

offer mixed-signal

integration opportunity

Sense, Acquisition &

Connectivity

Functionality

Computational &

Graphics

Functionality

TM

External Use 9

Low-power

Core

Analog

NVM

Narrow-band RF

Wide-band

RF

Sensors

(MEMS)

Antennas Energy SourcesPower Management

(PMIC/PMU)

Optics (Camera)

High-

Performance

Core

Analog

Complete Integration

Scaled and all-in-one small, thin

form factor package

End Nodes of TOMORROW

TM

External Use 10

Recent scaling and performance improvements driven by

unprecedented technical innovation on silicon

1970 1980 1990 2000 2010 2020

Cu Metallization

(220nm)

Immersion

Lithography

(45/40nm)

Low-k ILD

(130/90nm)Strained Si

(90/65nm)

High k / Metal Gate

(32/28nm)

FD-SOI

(28/22nm)

FinFET

(22/16/14nm)

(from STMicroelectronics)

(from TSMC)

10 mm

1 mm

100 nm

10 nm

1 nm

Moore’s Law

“No Exponential is Forever…but Forever can be Delayed”

TM

External Use 11

Freescale Process Development Strategy

• CMOS Platform-Based

Technologies:

− Leverage foundry standard

technology

− Adapt for targeted applications

• Differentiating Technologies:

− Focus on

performance/features

− High re-use >80%

of the technology

platform

− Wholly-owned

intellectual

property

CMOS

Platform

eNVM

RF

UHV

An

alo

g

CMOS

High

Performance

SOI

RF

CMOS

Packaging

e-Non

Volatile

Memory

Sensors

SmartMOS

Power &

Analog

Fe

atu

re / P

erf

orm

an

ce

Diffe

ren

tia

tio

n

Degree of Partnering

TM

External Use 12

Smart Technology Choices

i.MX

1

2

Which node?

Which process

architecture?

TM

External Use 13

28nm – ‘Last Simple Node?’

11

1.0

6.0

14/16nm(FinFET)

28nm(High-K

Metal Gate)

40nm65nm90nm.13um.18um

50%INCREASE in COST

Wafer Cost

normalized to

0.25um cost

40nm to 28nm will be significant % of worldwide capacity in 2020

TM

External Use 14

Cost Vs. Performance

80%

90%

100%

110%

120%

130%

140%

150%

160%

0.00 25.00 50.00 75.00 100.00 125.00 150.00

Die

Co

st 1

6F

F/2

8F

D

Die Size

i.MX Die Cost Comparison: 16FF vs 28FD

150% 175% 200%

Relative Wafer Price

i.MX Processors• Large range of die size

• Larger amount of analog

• Pads and overhead not scaling

• Future RF integration

TM

External Use 15

Freescale History Leveraging SOI

• Freescale has developed 20+ processors over 3 generations of SOI technology

• Soft Error Rate (SER) is becoming an increasingly significant factor as SoC memory arrays

continue to increase in size & density

• Bulk technology performs successively worse with each technology node

• SOI provides 5 ~ 10x better SER reliability and the gap is widening as geometries shrink

• 28 FD SOI benefits extend to 10-100X better immunity

0

500

1000

1500

2000

2500

3000

3500

4000

4500

130nmSOI 90nmSOI 45nmSOI

So

ft E

rro

r R

ate

(F

ITs/M

b)

Alpha SER

Neutron SER

0

500

1000

1500

2000

2500

3000

3500

4000

4500

130nm (B) 90nm 65nm

So

ft E

rro

r R

ate

(F

ITs/M

b)

Alpha SER

Neutron SER

TM

External Use 16

SER Comparison

Technology Intrinsic (Technology) SER Product-Level SER

28nm Bulk Si Moderate Design techniques / protection

28nm FD-SOI LowProtection techniques depend on amount

of memory and logic content

14/16nm FinFET LowProtection techniques depend on amount

of memory and logic content

TM

External Use 17

Freescale Leveraging SOI for Power Management ICs

• Each component is surrounded on all sides by hard ground plane

• Each component or group of components is surrounded by oxide isolation

• No parasitic components to substrate.

• System-level voltage expansion and physical area shrink by eliminating

substrate injection and device cross-talk concerns in design.

Oxide

Device1 Device2EPI

Dee

p T

ren

ch

Oxid

e

Si

N Silicon Substrate

Bottom Oxide (BOX) SOI

Wafer

Su

bstra

te T

ie / G

rou

nd

Pla

ne

Su

bstra

te T

ie / G

rou

nd

Pla

ne

NSDPSDNSD NSDNSDNSDNSD

Grown

EPI

TM

External Use 18

FD SOI Advantages

i.MX

1

3

Power-Performance BenefitsLow Vdd with Performance

Improved Electrostatics

Scalable Platform

Analog & RF CharacteristicsBetter Gain, Matching, Noise

Gate 1st Integration

2

Lower Risk ManufacturingSimple Integration / Fast TAT

Extends 28nm install base

Low complexity planar device

TM

External Use 19

28nm FD-SOI Platform

Frequency FOM

Lea

kage F

OM

T=25C

Vdd=0.8V, 1.1V

Forward

Back Bias

Reverse

Back Bias

Each point represents simulated average over three X1 library cells from a unique Vt-L combination. Ignores

interconnect impact, which is highly implementation dependent

Logic Gate Leakage/Performance Metric

Back-bias enables large

dynamic operating range

Good power-performance

at low voltages,

temperatures

(IOT standby mode)

TM

External Use 20

Process Technology Implications

28nm & Beyond High-K Metal Gate FD-SOI FinFET

Energy Efficiency

Cost Competitiveness

Ease of Design

Ease of Diversification

MemoryMulti-Cores RF ConnectivityNon-volatile

Memory• Secure Java / OS support

• Connectivity S/W stack

• Power Management

• Performance

• Security / ARM® TrustZone

• Wireless Everywhere

• Program Complexity

• Data Collection

TM

External Use 21

FD SOI Gaps Addressed by Freescale

i.MX

1

3

Utilizing Full Range of

Back-Gate BiasingExtended Bias Range

BEOL TDDB Rules

Enhanced Voltage Management

Expanding Richness

of Design CollateralDDK Enhancements

RAM Compiler Enhancements

IO Enhancements

2

Enabling Auto Quality

and Analog IPUnique Design Rules & Verification

Supporting Multiple IP Vendors

Auto Aging Use Case

TM

External Use 22

Single A53 @ >1.2 GHz

Lower Power & Smaller Area

• Leveraging Bias Range

• Scalable Performance

Subsystem Attributes 28 FD SOI Alternative 28nm

Instances 550K 1250K

Leakage (Typical / WC) 70 / 175mA 125 / 315mA

Normalized dynamic power 0.75 1.0

Area 1.3 sqmm 1.7 sqmm

TM

External Use 23

i.MX 8 Coming Soon…

Leveraging superset design…

• ARM® V8-A 64 bit architecture

• 10+ core complex

− Cortex-A72, Cortex-A53...

• Enhanced graphics

• Leadership 4k video

• Integrated vision

• Low power 4k multi-display

• Mixed signal

• Rich connectivity

• Compelling auto features 28nm Technology

Positioning FD SOI for leadership in broad

market applications processors

Display

Ctrl

DD

R

ss_imaging

MIPI_CSIMIPI_CSI

SCU DB Audio

Display

Ctrl

Imagin

g

Mixed Signal Logic

Multimedia

Digital Logic

Core Complex

(A53/A72)

DD

R

Connectivity

Mix

ed S

ignal L

ogic

Mix

ed S

ignal L

ogic

TM

External Use 24

Summary

• The evolving smart world requires a broad range of applications processors

• I/O counts, integrated PHYs and interface speeds are increasing

• Integration of functions in a cost effective technology is required for success

• 28 FD SOI offers advantages that allows scaling from small power efficient

processors to high performance safety critical processors

• Freescale’s broad i.MX product portfolio and technology adoption strategy

enables cost-effective ground-breaking solutions

• Future roadmap for i.MX will leverage 14nm class devices in order to scale

power-performance when market demand justifies higher cost and expense of

development

TM

© 2015 Freescale Semiconductor, Inc. | External Use

www.Freescale.com