Smart Sensors and Mems || Capacitive sensors for displacement measurement in the sub-nanometer range

© Woodhead Publishing Limited, 2014

63

3 Capacitive sensors for displacement

measurement in the sub-nanometer range

S. XIA, NXP Semiconductors, The Netherlands and

S. NIHTIANOV, Delft University of Technology,

The Netherlands

DOI: 10.1533/9780857099297.1.63

Abstract: The main challenge in designing an interface circuit for capacitive displacement sensors with sub-nanometer resolution is the large offset capacitance of the sensor. This offset capacitance is a result of the relatively large distance between the sensor electrodes, compared with the displacement range to be measured. From the different methods with which to interface capacitive sensors, a charge-balancing technique is used here to demonstrate a power-effi cient way to remove the offset, while maintaining high resolution and short conversion time. As an example, the design of an oversampling capacitance-to-digital (CDC) converter based on a third order sigma/delta modulator is presented.

Key words: capacitive displacement sensor interface, switched-capacitor circuits, offset capacitance cancellation, incremental ΣΔ converter.

3.1 Introduction

Large offset capacitance often presents problems in capacitive sensor mea-

surements. In this chapter, we discuss a capacitive sensor interface circuit,

based on the charge-balancing technique, that removes the effect of offset

capacitance electrically. High resolution is achieved with a relatively short

conversion time.

3.2 Challenges for sub-nanometer displacement measurement with capacitive sensors

In precision mechatronic systems like wafer steppers, electron microscopes

and so on, the position of critical mechanical components must be dynami-

cally stabilized with sub-nanometer precision. This can be achieved with a

servo loop consisting of a displacement sensor and an actuator, as shown in

Fig. 3.1. For this application, capacitive displacement sensors offer a smaller

64 Smart sensors and MEMS


component size and lower cost, compared with other sensors, like optical

interferometers, for example. Another important advantage of capacitive

sensors is that they do not consume or generate electrical energy when

converting displacement into electrical signal and, hence, they do not pro-

duce electronic noise, which is a prerequisite for obtaining extremely high

resolution.

In Fig. 3.2, a parallel plate capacitive sensor is shown, the capacitance

of which is a function of the gap and overlap between its two plates. The

changes in both of these two physical parameters can be used to sense dis-

placement. In both cases, the sensitivity to small displacement x is 1 :

dCdx

Cx

= 0

0

where C 0 is the nominal capacitance at x 0, and x 0 is the gap between the

plates or overlapping width of the plate, respectively. It can be seen that

decreasing x 0 can increase the sensitivity of the capacitive sensor. For typical

geometries, the gap is much smaller than the overlap; thus, for high sensi-

tivity capacitive displacement sensors, the variation in the plate gap is gen-

erally used. Although higher sensitivity comes at the cost of nonlinearity

because, for the gap-closing transducer, the capacitance change is a known

nonlinear function of displacement – if x 0 is known, this nonlinearity can be

accounted for by backend processing.

Residualvibration

Lenscolumn

Readout

Actuator Wafer stage

Cx

3.1 Example of a servo loop with a capacitive displacement sensor.

Capacitive sensors for displacement measurement 65


From the above discussion, it is clear that for maximum sensitivity, it is bet-

ter that the gap between the plates is as small as possible. However, mechan-

ical tolerances limit the minimum gap between the sensor electrodes to a

few micrometers, 2 while in the targeted applications the required resolution

has to be in the sub-nanometer range (typically, below 100 pm). At the same

time, the displacement and/or the vibrations of the target to be measured

are normally much less than 1 μ m. In terms of capacitance values, if the

nominal sensor capacitance at x 0 = 10 μ m is 10 pF, the interface circuit needs

to have an input-referred capacitance resolution of better than 100 aF. As a

comparison, the variation of the sensor capacitance related to the displace-

ment range is going to be much less than 1 pF, due to the low sensitivity of

the capacitive sensor to displacement. So, the sensitivity of the displacement

sensor becomes limited by the realizable gap distance. This also means that

the readout circuit needs to have more than 17-bit resolution with respect

to the nominal sensor capacitance. Furthermore, in servo-loop applications,

often the measurement latency needs to be very low. The main challenge for

the electronic interface is to provide high-resolution capacitance measure-

ment with low measurement latency, which is challenging because of the

trade-off between measurement time and resolution.

Since the nominal capacitance of the sensor is much greater than the sen-

sor capacitance variation, it can be assumed that the sensor has a large offset

capacitance. Luckily, there are ways to deal with this, as will be discussed in

the next section.

3.3 Offset capacitance cancellation technique

The existence of offset capacitance in a capacitive sensor often imposes a

burden on the interface circuit. As the value of the sensor capacitance is

dominated by the offset value, the interface circuit would have to resolve

the relatively small capacitance variation on top of the offset capacitance.

The offset capacitance will consume a large portion of the dynamic range of

x

(a) (b)x

x0

x0

3.2 Parallel capacitive displacement sensors working on changes of (a)

gap closing, (b) overlapping area.



the interface, which would translate into the waste of system resources, such

as power consumption and conversion time.

Fortunately, there are techniques to create circuits that cancel the effect

of the offset capacitance. 3,4 Typically, a capacitive sensor interface would

involve a virtual ground created by an operational amplifi er (opamp) in

order to make the readout of the capacitive sensor interface insensitive to

the parasitic capacitances to ground at each of the two connections. 5,6 Such

a virtual ground can also be used to cancel the effect of the offset capaci-

tance, because a ‘ zoom-in ’ capacitor can be connected to the virtual ground

and driven by an excitation signal that is opposite to that driving the sensor

capacitor. The net charge that gets through the virtual ground and arrives

at the feedback capacitor is then a function of the difference of the sensor

capacitor and the zoom-in capacitor. By establishing the value of the zoom-

in capacitor as equal to the offset capacitance of the sensor, the effect of the

big sensor offset capacitance can be eliminated.

However, it should be noted that this function comes at a price. This is

because the addition of the zoom-in capacitor increases the total capaci-

tance at the input of the amplifi er, which increases the noise gain of the

amplifi er. 7 Whether this penalty will be signifi cant depends on the com-

ponent values. For instance, if the value of the parasitic capacitance at the

input of the amplifi er (due, for example, to a long cable) is much greater

than the sensor capacitance (and, hence, the zoom-in capacitance), then the

penalty of introducing this zoom-in capacitance is negligible. In most cases,

the benefi t of using zoom-in capacitance over-rides the penalty introduced.

However, it is still benefi cial to bear this potential disadvantage in mind.

A typical way to measure capacitance is to compare it with a reference

capacitance, by creating a ratio between them. There are many ways to obtain

the capacitance ratio. However, the most popular method for obtaining high-

resolution capacitive ratio is by using switched-capacitor circuitry combined

with the charge-balancing principle. 8 This is because this method has a proven

record of achieving both high resolution and high accuracy, at the expense

of a generally slower conversion speed, because it basically trades resolution

with time. 9 Figure 3.3a shows a block diagram of a capacitive sensor based

on the charge-balancing principle. It is basically a switched-capacitor incre-

mental ΣΔ converter. 10 In such a system, a virtual ground is also available to

realize offset capacitance cancellation, as shown in Fig. 3.3b.

One of the most important advantages of switched-capacitor circuits in

terms of realization is their relaxed requirement for an excitation signal.

Mismatches in the excitation signals would normally translate into percep-

tions of capacitance difference, and would lead to an error in the readout

circuit. For a switched-capacitor circuit, however, because the circuit is only

sensitive to the fi nal settled voltage values, the exact waveform of the two

anti-phase excitation signals does not need to match perfectly, as long as



there is no charge loss and there is no signal-picking at the input of the con-

vertor. This simplifi es the realization a great deal.

The effective input of the interface becomes the difference between C X

and C Z ; that is, C X − C Z . When the value of C Z is selected such that it equals

the offset capacitance of C X , the effect of the offset capacitance is completely

removed. Then, a much lower C ref can be applied that gives a measurement

range that is just suffi ciently broad to cover the small capacitance varia-

tion ± Δ C X . In this way, the quantization requirement of the interface can

be largely reduced. However, in practice it is diffi cult to ensure that C Z fully

cancels the offset capacitance of C X , so some tolerances need to be kept in

mind when designing the interface. In the next section, a design example

will be given based on the method discussed above.

3.4 Capacitance-to-digital converter (CDC) with offset capacitance cancellation and calibration functions

In this section, a design example is presented that shows the benefi ts of

using the zoom-in technique. The switched-capacitor incremental converter

Vexe

Vexe

Vexe

Vexe

Vexe

Vexe

(a)

(b)

Vexe

Cref

Cref

–

+

–

+

10110···

Bitstream

10110···

Bitstream

Cx(off chip)

Cx(off chip)

Cz

3.3 Block diagram of a capacitive sensor interface based on charge-

balancing principle. (a) Illustrates the regular case, while (b) illustrates

the case where a ‘ zoom-in’ capacitor is added.



digitizes the capacitive ratio. The performance of the interface before and

after using the zoom-in technique will be compared.

In this design example, the specifi cations are taken from a real applica-

tion. The capacitive displacement sensor will have a nominal capacitance of

10 pF. The measurement range, in contrast, is less than 50 fF. The targeted

resolution is better than 100 aF. The noise of the interface can be classifi ed

into thermal noise and quantization noise. Schreier et al . 7 provide an exten-

sive overview on this topic. The total noise power is the sum of the thermal

noise power and the quantization noise power.

Thermal noise in a switched capacitor circuit is directly linked to the size

of the sampling capacitor. 7 For an incremental converter, which utilizes the

oversampling technique, thermal noise can be further reduced by increasing

the oversampling ratio. For a fi xed conversion time, both methods for reduc-

ing thermal noise would require the interface to burn more power, either by

driving larger capacitors or by using a faster clock. For a capacitive sensor

interface circuit based on an incremental converter, the sensing capacitor

acts as a sampling capacitor. 5 Its value is often fi xed and cannot be changed

arbitrarily by the designer. Therefore, the only way to reduce thermal noise

in such an interface is by increasing the oversampling ratio.

Increasing the oversampling ratio reduces also the quantization noise

level. 9 Depending on the loop fi lter structure, the slope at which the quan-

tization noise is reduced will also change. Generally speaking, the higher the

order of the loop fi lter, the faster the quantization noise reduces with the

increasing oversampling ratio. Apart from using higher order loop fi lters,

a multi-bit quantizer can be used, instead of a single-bit quantizer, in order

to increase the speed of operation. Due to the noise-shaping effect on the

quantization noise, the quantization noise decreases more rapidly than the

thermal noise as the oversampling ratio is increased.

As discussed in the previous section, the zoom-in technique does not

help to reduce the thermal noise level. So, basically, the thermal noise of the

interface is determined to some extent by the absolute value of the sensor

capacitor, which in our case is about 10 pF. Zoom-in, however, reduces the

full-scale input range of the interface and therefore reduces the requirement

on the quantization noise of the interface. So, it is important to point out

that using the zoom-in technique only makes sense if, before it is applied,

the quantization noise level is greater than the thermal noise level. In this

example, the estimation of the thermal noise level is performed under the

guidance provided by Schreier et al . 7 This shows that an oversampling ratio

of about 100 is needed to reduce the input-referred thermal noise level to

a suffi ciently low level. So, in order to make the interface is not limited by

quantization noise, we need to achieve a comparably low quantization noise

level within an oversampling ratio of 100.



Without employing the zoom-in technique, the input signal range, includ-

ing the offset capacitance, would be about 10 pF. Achieving capacitance

resolution below 100 aF would require more than a 17-bit dynamic range.

So, the question here is: how much resolution can be achieved with an over-

sampling ratio of 100, and will the corresponding input range be suffi ciently

large to cover the sensor capacitance variation during normal operation.

Although a multi-bit quantizer and a digital-to-analogue converter (DAC)

can be used to reduce the required oversampling ratio, one of the most pro-

nounced problems with this method is that the nonlinearity of the required

multi-bit DAC will limit the linearity of the modulator. This is because the

DAC is in the feedback and its error will be directly added to the error of

the modulator. In order to solve this problem, dynamic element matching

(DEM) has to be used. 9 However, this will lead to hardware complexity. A

1-bit DAC is intrinsically linear and thus does not suffer from this problem.

Mainly, in order to reduce hardware complexity, a higher order loop fi lter is

chosen as the optimum approach.

There is a theory, based on a linearized model, which can predict the nec-

essary oversampling ratio for a particular resolution, with a certain loop fi l-

ter order. However, at low oversampling ratio values, the prediction is often

not very accurate, especially for incremental converters. A dedicated model

was made that leads to complicated results for the prediction of the required

oversampling ratio for an incremental converter. 11 The authors recommend

using these results as guidelines only and rely on system-level simulation to

obtain a better estimation. The conclusion based on the simulations results

is that, with an oversampling ratio in the order of 100:

1. a second order loop fi lter will not meet the requirement of an input

capacitance range of 50 fF, which is not acceptable for this application;

2. increasing the loop fi lter above third order brings negligible improve-

ments. For this reason, a third order loop fi lter is chosen for this design.

With a third order loop fi lter, the input range is selected to be 200 fF, which

brings suffi cient margin to cover the variation of the sensor capacitance,

while also providing some margin for the mismatch between sensor capaci-

tance C X and the offset-cancelling capacitance C Z . This means that better

than 12-bit resolution is needed when the zoom-in technique is applied.

With a third order loop fi lter, a very good quality decimation fi lter has

to be used in the CDC in order to reach the required capacitance resolu-

tion within the limited conversion time. Figure 3.4 shows the achievable

resolution of three different decimation fi lters for a ΣΔ converter with a

third order loop fi lter, as a function of the number of clock cycles in one

conversion, using the formulas given in Marcus (2005). 11 It can be seen



that only a cascade of integrators (CoI) decimation fi lter can reach better

than 12-bit resolution within 100 clock cycles. The normally used sinc3 and

sinc4 fi lters need 240 and 160 clock cycles, respectively, to reach the same

resolution. In order to keep the conversion time low, a higher clock signal

will be needed. For example, for a conversion time below 20 μ s and 100

clock cycles, a 5 MHz clock signal is required.

As a comparison, if the zoom-in technique is not applied, the same third

order incremental converter would need an oversampling ratio larger than

500 in order to reach a quantization noise level equivalent to 17 bits. So, in this

example, by applying zoom-in, the conversion time with the same clock fre-

quency will be fi ve times faster. In addition to this, as will be discussed shortly,

1024

256

Num

ber

of c

ycle

s

64

166 8 10 12 14

Calculated ENOB

16 18 20

COI filtersinc3

sinc4

3.4 Achievable resolution of three different decimation fi lters for a ΣΔ

converter with a third order loop fi lter as a function of the number of

clock cycles.

U

Cap domain Voltage domain

b1 b2 b3 a3

a2

a1

1z - 1

–

1z - 1

1V

z - 1

D2C

3.5 The chosen conventional feed-forward loop fi lter topology.

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oodhead P

ublis

hin

g L

imite

d, 2

014

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Cx

CINT1P+EX

CINT1P

CINT1N_EX

ΦCx

Φdrive

Φ1 & Φd

Φ2 & Φ2d

Φeval

Φdrive

CCref

CINT1P

CXD

CZD

+ –

– +

bs

bs CREFD

CINT2N CINT3N

CINT3P CF3P

CF2P

CF1P

CINT2PCS3P

CS3N CF3N

CF2N

CF1N

chop

bs

CS1P

CS2N

Cz

ΦCx

Φ1

ΦEXΦ2d Φ1

Φ1

Φ2

Φ2

Φ1d

Φ1d

Φ2

Φ1

ΦEX

Φ2d Φ2d

Φ1d

Φ1d

Φ2d

Φ1d

Φ1d

Φ2d ΦevalΦ2

Φ1

Φ1

Φ2Φ1

Φ2

Φ2

Φ1

Φ2d

Φ2ΦCref

bs

bsGND

GND

GND

chop

bs

Normal mode CapDAC calibration mode

+ –

– +

+ –

– +

+ –

– +

3.6 Simplifi ed circuit diagram of the interface, showing different timing diagrams in different operating modes.



using the zoom-in principle also prevents slewing in the amplifi er; this prop-

erty can be further utilized to increase the clock frequency of the converter

with the same level of current consumption of the amplifi ers. In this sense, the

actual benefi t in applying the zoom-in principle is greater than fi ve times.

Based on the above discussions, a capacitive sensor interface was

designed, the block diagram of which is presented in Fig. 3.5. The inter-

face is built around a switched-capacitor sigma-delta converter which

is shown in Fig. 3.6. 12 The zoom-in capacitor C Z is realized with a bank

of on-chip capacitances CapDAC, to be able to easily adjust its value to

match that of the sensor capacitance. CapDAC is basically a binary bank

of capacitors that can be switched in and out by applying a digital code.

The interface is fabricated in a standard 2P4M 0.35 μ m complementary

metal-oxide-semiconductor (CMOS) process and occupies an active area

of 2.6 mm × 2 mm. A micro-photograph of the chip layout is shown in

Fig. 3.7. It draws 4.5 mA from a 3.3 V supply, of which over 3.1 mA is

consumed by the fi rst operational transconductance amplifi er (OTA) due

to the need to drive large capacitances. The CapDAC and all the other

on-chip capacitors are poly-poly capacitors because of their good linear-

ity and temperature stability. For fl exibility, in this design the control logic

and the decimation fi lter were implemented off-chip.

To verify the performance of the CDC with an off-chip sensor, a test set-

up was built. As shown in Fig. 3.8, it consists of a fi xed electrode in close

proximity to an electrode attached to an aluminum rod. Heating the rod, via

an attached resistor, changes its length and thus the capacitance between

the two electrodes. The CDC is connected to the electrode on the rod via

a short shielded cable, which adds extra parasitic capacitance (roughly 10

CapDAC

OTAs and Bias

Comparator

Switches

3.7 Die micrograph.



Vexe

GND

Cap sensor

Fixed plate Moving plate Aluminum rod

Heater

Coaxial cables

Virtualground

Rest ofthe

CDC

Φdrive

3.8 Experimental set-up.

6.6

6.4

6.2

6

5.8

Cap

acita

nce

(fF

)

Cap

acita

nce

(fF

)

5.6

5.4

5.20 2 4 6 8

Time (ms)

10 12

5.9

5.8

5.7

5.6

5.5

5.4

5.33.2 3.4 3.6 3.8 4 4.2

Time (ms)

Noise floor is 65aFrms

4.4 4.6

14 16

3.9 Measurements on a capacitive sensor that is mechanically actuated

at 100 Hz.



pF) to ground. The small capacitance changes created by driving the heater

with a 66 mHz, 8 mW square-wave are shown in Fig. 3.9. The actual value

of the reference capacitor C ref , as shown in Fig. 3.6, was found to be 91.8 fF

by calibrating it against an external 10.3 pF surface-mount capacitor whose

value had been measured by a HP4192A LF impedance analyzer ( ± 100 fF

inaccuracy). The capacitance changes were then found to correspond to

500 fFpp, while the noise on the measurements corresponded to 65 aFrms.

3.5 Conclusion

A practical way of removing the effect of the offset capacitance in a capac-

itive sensor has been presented. The realized interface circuit made use of

the charge-balancing principle and achieved an effective capacitance reso-

lution of 17 bits with a conversion time of 20 μ s.

3.6 References 1. B. Boser, Capacitive Interface Electronics for Sensing and Actuation , Berkley:

University of California, 21st Workshop on Advances in Analog Circuit Design,

AACD, Valkenburg aan de Geul, The Netherlands (2012).

2. J.P. van Schieveen, J.W. Spronck, S. Nihtianov and R.H. Munnig Schmidt,

‘ Integrated Auto Alignment and Calibration For High Resolution Capacitive

Sensor System, ’ Proc. EUSPEN, pp. 188–191 (2010).

3. J. Markus, J. Silva and G.C. Temes, AD7746 datasheet, Analog Devices, avail-

able online through http://www.analog.com.

4. D.Y. Shin, H. Lee and S. Kim, ‘ A delta-sigma interface circuit for capacitive

sensors with an automatically calibrated zero point,’ IEEE Trans. Circuits and System II , Vol. 58 , No. 2, pp. 90–94, February (2011).

5. J.O’Dowd, A. Callanan, G. Banarie and E. Company-Bosch, ‘ Capacitive sen-

sor interfacing using sigma-delta techniques,’ Proc. IEEE Sensors , October–

November, pp. 951–954 (2005).

6. L.K. Baxter, Capacitive Sensors: Design and Applications , New York: John

Wiley (1996).

7. R. Schreier, J. Silva, J. Steensgaard and G.C. Temes ‘ Design-oriented estimation

of thermal noise in switched-capacitor circuits,’ IEEE Trans. on Circuits and Systems , Vol. 52 , No. 11, pp. 2358–2368 (2005).

8. B. Wang, K, Tetsuya, T. Sun and G. Temes, ‘ High-accuracy circuits for on-chip

capacitive ratio testing and sensor readout,’ IEEE Trans. Instrum. Measur. , pp. 16–20, February (1998).

9. S.R. Norsworthy, R. Schreier and G.C. Temes (eds), Delta-Sigma Data Converters: Theory, Design and Simulation , Piscataway, New York: IEEE Press

(1997).

10. J. Markus, J. Silva and G.C. Temes, ‘ Theory and applications of incremental ΣΔ

converters, ’ IEEE Trans. on Circuits and Systems , Vol. 51 , No. 4, pp. 678–690

(2004).



11. J. Markus, PhD Thesis, Budapest University of Technology and Economics,

Department of Measurement and Information Systems, Budapest, Hungary

(2005).

12. S. Xia, K. Makinwa and S. Nihtianov, ‘ A Capacitance-to-Digital Converter for

Displacement Sensing with 17b Resolution and 20 μ s Conversion Time,’ Digest

of technical papers, ISSCC, 2012.

Documents

Smart Sensors and Mems || Capacitive sensors for displacement measurement in the sub-nanometer range