Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007

Slides to Accompanya Video Tutorial on

Harry Porter’s Relay Computer

Harry Porter, Ph.D.Portland State University

November 7, 2007

+V

Double Throw Relay

+V

Double Throw Relay

Four Pole, Double Throw Relay

+V

Four Pole, Double Throw Relay

Schematic Diagrams

Assume other terminalis connected to ground

Schematic Diagrams

Assume other terminalis connected to ground

+V

The “NOT” Circuit

in out

in

out+V

in out 0 1 1 0

0

1

Convention: “1” = +12V “0” = not connected

The “NOT” Circuit

in out

in

out+V

in out 0 1 1 0

1

0

Convention: “1” = +12V “0” = not connected

c

The “OR” Circuit

b b or c

+V

+V

b c OUT0 0 0 0 1 11 0 11 1 1

bc b or c

An Optimization?

c

b

b or cb or cbc

c

An Optimization?

b b or c

b

b or cc

c or dd

d

c or d

c

An Optimization?

b b or c

b

b or cc

c or dd

d

c or d

Whoops!

An Optimization?

b or c

c

b

+V

d

c or d

b b or c

c

c or dd

1-Bit Logic Circuit

b

c

NOT

b c NOT AND OR XOR0 0 1 0 0 00 1 1 0 1 11 0 0 0 1 11 1 0 1 1 0

AND

OR

XOR

1-Bit Logic Circuit

b

VNOT

AND

OR

XOR

c

b c NOT AND OR XOR0 0 1 0 0 00 1 1 0 1 11 0 0 0 1 11 1 0 1 1 0

1-Bit Logic Circuit

b

V

c

NOT

AND

OR

XOR

b c NOT AND OR XOR0 0 1 0 0 00 1 1 0 1 11 0 0 0 1 11 1 0 1 1 0

1-Bit Logic Circuit

b

V

c

NOT

AND

OR

XOR

b c NOT AND OR XOR0 0 1 0 0 00 1 1 0 1 11 0 0 0 1 11 1 0 1 1 0

1-Bit Logic Circuit

b

V

c

NOT

AND

OR

XOR

b c NOT AND OR XOR0 0 1 0 0 00 1 1 0 1 11 0 0 0 1 11 1 0 1 1 0

1-Bit Logic Circuit

b

V

c

NOT

AND

OR

XOR

b c NOT AND OR XOR0 0 1 0 0 00 1 1 0 1 11 0 0 0 1 11 1 0 1 1 0

AND7

OR7

Eight 1-bit circuits can be combinedto build an...

8-Bit Logic Circuit

LogicCircuit

NOT7

B7 C7

• • •

XOR7

AND1

OR1

LogicCircuit

NOT1

B1 C1

XOR1

AND0

OR0

LogicCircuit

NOT0

B0 C0

XOR0

The “Full Adder” Circuit

CarryinCarryout FullAdder

Sum

B CCyin B C Cyout Sum

0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1

8 full-adders can be combined to build an...

8-Bit Adder

CarryFull

AdderFull

Adder

B0 C0

Sum0Sum1

B1 C1

CarryFull

Adder

Sum7

B7 C7

• • •

+B

88

8C

SumCarry

Carry0

The Zero-Detect Circuit

ResultBus

Zero V+

The Zero-Detect Circuit

ResultBus

Zero V+

Sign

Enable Circuit

Enable

Enable Circuit x7 x6 x5 x4 x3 x2 x1 x0

ResultBus

B XOR C

Enable

Enable

Shift Left Circular (SHL) b7 b6 b5 b4 b3 b2 b1 b0

ResultBus

B

3-to-8 Decoder

f1

Vf0

f2

INCANDORXORNOTSHL<unused>

ADD

f0 f1 f2 OUTPUT

0 0 0 1 0 0 0 0 0 0 00 0 1 0 1 0 0 0 0 0 00 1 0 0 0 1 0 0 0 0 00 1 1 0 0 0 1 0 0 0 01 0 0 0 0 0 0 1 0 0 01 0 1 0 0 0 0 0 1 0 01 1 0 0 0 0 0 0 0 1 01 1 1 0 0 0 0 0 0 0 1

CarrySign

Arithmetic Logic Unit (ALU) B 8

8

8C

Data Bus

3

Zero

8-bitLogic

8-bitAdder

Enable En En En En EnEn

AN

D

OR

XO

R

NO

T

SH

L

INC

AD

D

Function

3-to-8Decoder

Zero-Detect

CarrySign

An 8-Bit ALU

ALUB

8

8

8C

Result

Function Code 000 add 001 inc 010 and 011 or 100 xor 101 not 110 shl 111 <nop>

3

Zero

Register Storage

+VA

Register Storage

+V

• • •

A7 A0A6

Register Storage

+V

Bus

• • •

Enable

A7 A0A6

Select

Register Storage

A7

Select

Load A0

• • •

Enable

A6

Bus

Register Storage

A7

Select

Load A0

• • •

Enable

A6

Bus

8-Bit “Data” Bus

LoadSelect

LoadSelect

“X” Register “Y” Register

8-Bit Registers

16-Bit “Address” Bus

8-Bit “Data” Bus

“X” Register “Y” Register

LoadSelect

LoadSelect

LoadSelect

16-bitIncrement

Inst

M1

M2 M

X

Y XY

J1

J2 J

PC

Inc

8-bitALU

Memory

AddrData

Z Cy S

SystemArchitecture

8-b

it D

ata

Bu

s

A B C D

16-b

it A

dd

ress

Bu

s

QuickTime™ and aTIFF (LZW) decompressor

are needed to see this picture.

32K Byte Static RAM Chip

LEDs

8 FET Power Transistors(to drive relays during

a memory-read operation)

16-bitIncrement

Inst

M1

M2 M

X

Y XY

J1

J2 J

PC

Inc

8-bitALU

Memory

AddrData

Z Cy S

8-b

it D

ata

Bu

s

A B C D

16-b

it A

dd

ress

Bu

s

Example:The ALU

Instruction

16-bitIncrement

Inst

M1

M2 M

X

Y XY

J1

J2 J

PC

Inc

8-bitALU

Memory

AddrData

Z Cy S

Step 1:Fetch Instruction

8-b

it D

ata

Bu

s

A B C D

MEM-READSELECT

LOAD

16-b

it A

dd

ress

Bu

s

Inst

M1

M2 M

X

Y XY

J1

J2 J

PC

Inc

8-bitALU

Memory

AddrData

Z Cy S

8-b

it D

ata

Bu

s

A B C D

Step 2:Increment PC

SELECT

LOAD 16-bitIncrement

16-b

it A

dd

ress

Bu

s

16-bitIncrement

Inst

M1

M2 M

X

Y XY

J1

J2 J

PC

Inc

8-bitALU

Memory

AddrData

Z Cy S

8-b

it D

ata

Bu

s

A B C D

LOAD

SELECT

Step 3:Update PC

16-b

it A

dd

ress

Bu

s

16-bitIncrement

Inst

M1

M2 M

X

Y XY

J1

J2 J

PC

Inc

Memory

AddrData

Z Cy S

8-b

it D

ata

Bu

s

A

D

Step 4:Execute Instruction

FUNCTION

LOAD

LOAD

B C

8-bitALU

16-b

it A

dd

ress

Bu

s

Clock

Switch

+V Output

+V

Clock

Switch

+V Output

+V

Charging

Clock

Switch

+V Output

+V

Discharging

Clock

Switch

+V Output

+V

+V +V

Clock

+V +V

A B C D

+V +V

Clock

Charging

+V +VOnOn

Discharging

A B C D

+V +V

Clock

Charging

+V +VOn

Discharging

On

A B C D

+V +V

Clock

Charging

+V +VOn

Discharging

On

A B C D

+V +V

Clock

Charging

+V +VOn

Discharging

On

A B C D

+V +V

Clock

Charging

+V +VOn

Discharging

On

A B C D

Clock Timing Diagram

A

B

C

D

Clock

Clock = (A and B) or (C and D)

t7t5t4t3t2t1

Finite State Machine

1 2 3 4 5 6 7 8

t6 t8

Outputs

clock

Output from FSA

2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 31

t1

t2

t3

t4

t5

t6

t7

t8

Instruction Timing - ALU Instruction

Select PC

Memory Read

Load Instr

Load Inc

Select Inc

Load PC

ALU Function

Load A

Load Cond.Code Reg.

2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 31


Select PC

Memory Read

Load Instr

Load Inc

Select Inc

Load PC

ALU Function

Load Cond.Code Reg.

2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 31

Fetch

Load A


Select PC

Memory Read

Load Instr

Load Inc

Select Inc

Load PC

ALU Function

Load Cond.Code Reg.

2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 31

Increment

Load A


Select PC

Memory Read

Load Instr

Load Inc

Select Inc

Load PC

ALU Function

Load Cond.Code Reg.

2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 31

Load A

Execute

Instruction Decoding

Instruction RegisterFinite State Machine

Control Signals(Load, Select, Mem-Read, etc.)

CombinationalLogic

1 2 3 4 5 6 • • • 7 6 5 4 3 2 1 0

1 2 3 4 5 6 7 8 9 10

Instruction Timing - 16-bit Move

Select PC

Memory Read

Load Instr

Load Inc

Select Inc

Load PC

Select Source-Register

2 3 4 5 6 7 8 11

Load Dest-Register

(Same asbefore)

Finite State Machine

1 2 3 4 5 6 7

9 11 13 15 16

17 18 19 20 21 22 23

10 12 14

24

8

Instruction Decoding and Control

Clock

InstructionRegister

Finite StateMachine

Control Lines

Instruction Decoding

Dat

a B

us

The Instruction Set

0 0 d d d s s s

1 0 0 0 r f f f

0 1 r d d d d d

1 0 1 1 0 0 0 0

Move

ALU

Load Immediate

16-bit Increment

ddd = destination registersss = source register (A, B, C, D, M1 ,M2 ,X or Y)

r = destination register (A or D)fff = function code (add, inc, and, or, xor, not, shl)

r = destination register (A or B)ddddd = value (-16..15)

XY XY + 1

The Instruction Set

1 0 0 1 0 0 r r

1 0 0 1 1 0 r r

1 1 0 0 0 0 0 0

1 0 1 0 1 1 1 0

Load

Store

Load 16-bit Immediate

Halt

rr = destination register (A, B, C, D)reg [M]

rr = source register (A, B, C, D)[M] reg

Load the immediate value into M (i.e., M1 and M2)

v v v v v v v v v v v v v v v v

The Instruction Set

1 1 1 0 0 1 1 0

1 0 1 0 d s s 0

1 0 1 0 1 0 1 0

Goto

Call

16-Bit Move

Return / Branch Indirect

a a a a a a a a a a a a a a a a

Branch to the given address

1 1 1 0 0 1 1 1 a a a a a a a a a a a a a a a a

Branch to the given addressSave return location in XY register

PC XY

d = destination register (PC or XY)ss = source register (M, XY or J)

The Instruction Set

1 1 1 1 0 0 0 0

Branch If Negative

Branch If Carry

Branch If Zero

Branch If Not Zero

a a a a a a a a a a a a a a a a

Branch to the given address if S = 1


Branch to the given address if Cy = 1

Branch to the given address if Z = 1

Branch to the given address if Z = 0



An Example Program

address instr assembly comment 0000 0000 0011 1001 Y=B Y B 0000 0001 0011 0110 X=0 X 0 0000 0010 1000 0101 A=¬B If sign(Y)==1 0000 0011 1111 0000 BNEG Else . 0000 0100 0000 0000 . . 0000 0101 0000 0111 . . 0000 0110 0011 0010 X=C X C Else: . 0000 0111 0101 1001 A=-7 D -7 0000 1000 0001 1000 D=A . Loop: Loop: 0000 1001 0000 1110 B=X Shift X left (circular) 0000 1010 1000 0110 A=B<<1 . 0000 1011 0011 0000 X=A . 0000 1100 0000 1111 B=Y Shift Y left (circular) 0000 1101 1000 0110 A=B<<1 . 0000 1110 0011 1000 Y=A . 0000 1111 0000 1111 B=Y If sign(Y)==1 0001 0000 1000 0101 A=¬B . 0001 0001 1111 0000 BNEG Else2 . 0001 0010 0000 0000 . . 0001 0011 0001 0111 . . 0001 0100 0000 1110 B=X X X + C 0001 0101 1000 0000 A=B+C . 0001 0110 0011 0000 X=A . Else2: . 0001 0111 0000 1011 B=D D D + 1 0001 1000 1000 1001 D=B+1 . 0001 1001 1110 0010 BNZ Loop If D != 0 goto Loop 0001 1010 0000 0000 . . 0001 1011 0000 1001 . . 0001 1100 1010 1110 HALT HALT

Documents

Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007