Slide001 Semiconductor Review

8/11/2019 Slide001 Semiconductor Review

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Ana ogIntegrate E ectron cs

EE 4223


2/154

Textbook:

1. P. R. Gra P. J. Hurst S. H. Lewis R. G. Me er "Anal sis

and Design of AnalogIntegrated Circuits," 4th Edition,WILEY.

2. Sergio Franco,Design with Operational Amplifiers and

Integrated Circuits, 2nd edition McGraw Hill.

Reference Books:

D. Johns & K. Martin,

nalog Integrated Circuit Design, JohnWiley & Sons.


3/154

Review of BJTs and MOS models

Op-amp stages and design:

Stability compensation and slew rate of op-amp

Op-amp as an amplifier

Non-linear Circuits

Monolithic Timers:

Active and switched capacitor filters:

Phase Locked Loop (PLL)


4/154

MidtermExams/Tests: 45

%

Fina : 40%

Total: 100%

Theremaybeminorchangeinthegrading

olic .


5/154

Tutorials may be arranged to compensate for any deficiency.

No any excuse will be accepted for any absence from theclass/test/quiz or late submission of homework/assignments.

Maximum absentees allowed in the course are six. No

You are expected to bring your text book/notes to class every

me.


6/154

You are expected to read the appropriate sections of

material.

Assignments,noticesoranyotherinformationwillbe

announced in the class or will be ut inJuweb

Jinnah/MRiaz/AnalogICs.Youmustcheckit

periodically.

Turnoffallelectroniccommunicationdeviceswhen

youentertheclassroom.


7/154

Academic

integrity/honesty

is

expected

ofstudents

IfIsuspect

you

of

cheating

during

a

quiz/test

nocreditwillbeawardedto ouandthecase

maybereportedtohigherauthorities.

workandfailuretocomplywiththis

.


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-W1 W2FromPoissonsEquation:

+

+

+ +2

2

AqNd V

dx

= = 1 0W x

Chargedensity

x1AqNdV

x Cdx = +

Efield( )1

AqNdV

E x W= = +

1, at x= =

x

10,V at x W = =

22

Potential11

2 2A

q xV W x

= + +

x11

2

AqV

= 0at x=


31/154

Depletionwidths2

11

2

AqN WV

= Fromconservationofcharge

( )1A

x

qNdVE x W= =

2similarly for 0


32/154

JunctionCapacitance

1dWdQ dQC = = A

P N

1R RdV dW dV

= dW

12

12

Depletion

region

( )

( )

21 0

1

02 1

VR

NAqNR R AA ND A R

dW d

dV dV NqN V

+ +

= =

+ + D

12

1A Dq N NC

=0

2 A D RN N V+ +


33/154

JunctionCapacitance

12

N N

( )00

2 1

j

A D D

C

N N V

=

+

12

02

A D

j

A D

q N NC

N N

=

+ 0

1

j

j

D

CC

V=

0


34/154

GradedJunction ax=

apac ance

x

0j

j

D

CCV

=

0


35/154

MinorityCarriersconcentrations

PN-Junction under

no as

pn

np

x=-W1xn=0

x=W2xp=0

0px nx

: equilibrium concentration of electrons in P-regionpn

: equilibrium concentration of holes in N-regionnp


36/154

PNJunction

PN-Junction under

Reversed Biased( )pn x ( )np x

Depletionregion

npRV V=

pn

x=-W1 x=W20px nx

( )1R TV Vp p pn n e n =

xn= xp=n n

V V0 0=


37/154

1( ) pp W p =Minority Carriers Concentration

PN Junction Forward Biased

2( np W p=

10 atpx x W= = n p

TV

kT

= ( ) p nx Lp p

n x n e =

( ) n px L

n np x p e

= pn

2n

( )Excess carriers N side =

x=-W1xp=0

x=W2xn=0

0px

nxpL

Depletionregion

nL

0

T

V V

p Vnp n

e

= =( )Excess carriers P side =

( )0( ) 1TV Vn n n np p x p p e = = Theequilibriumconcentrationof

holesandelectrons

n p

( )0( ) 1T

V V

p p p pn n x n n e = =

oneither

side

is

1TV VI I e= ( ) 1 p nT

x LV V

p pn x n e e =

( )( ) 1 n pT x LV Vn np x p e e =


38/154

Junction Forward Biased Static Diffusion Capacitance

ThediffusioncapacitanceCDistherateofchangeofinjectedchargew.r.t.

voltage.Largechargeispresentacrossthejunctionduetoforwardbiased.

Staticdiffusion

Capacitance DynamicdiffusionCapacitance

DC gdV dV r

= = = =

1TV VI I e=

n

DC

=

g

AtLowfrequency

D

T

IC

V

=

g=Lowfreqconductance

At hi h fre uenc

DC I1

2n =

2D

oean e t me o carr ers=


39/154

Junction Forward Biased Static Diffusion Capacitance

For transistors, the diffusion capacitance CD is measured from unity current

gain frequencyfTas

2D

Tf


40/154

Junction breakdown

I( )

12

max

2A D R

A D

qN N VE

N N

=

+

At a critical field (3x105 V/cm) the carrierstraversing the depletion region acquire sufficient

ener to create new holeelectron airs in

V

collisions with silicon atoms. This is called

avalanche process. The newly created carriers

are also capable of producing avalanche.

RA RI MI=

1n

MV

=

veryheavily

doped

junction

where

theelectric fieldbecomeslarge

enoughtostriptheelectronsaway

BV

fromvalenceband.Thisiscalled

tunneling.


41/154

Concentration Profile n-p-n Transistor

Active re ion

x=0

x=WB

CBV

n p n CC

BEV

CEV

BEV

V

B

nDepletion

Carrier Concentration

0p p= nnEpp(x)

p

np(0)

Region

Depletion Region NANDBE Tn po V VqAD n

=

Base CollectorEmitter

xx=0 x=WB

n

pnE np(x)A ABE T

B A

V V

C S

W NI I e=

n po

S

B A

qAD nI

W N

=


42/154

1BE T

B po p V ViqAW n qAD n

I e

= +2 b p D

C

B

L N

II

=F

1n po

B

qAD n

W = =

2 2

B po p i pB B A

b p D b n n p D

q n q n

L N D D L N + +

1 I+E C B C

F F

I I I I

= + = =

211 12

FpF B B A

F b n n p D

DW W N

D D L N

= = =+ + +


43/154

svery arge,t an

Where

F T

2

1

2

T

B

b n

W

D

=

+

1

1 p B AD W N

=

+n p D


44/154

NPN Transistors Large Signal Model

B C B C

VI I

B B

E E

BE T

BFI e=


45/154

PNP Transistors Large Signal Model

B C B CBI

BI

BEV ( )BE onVF BI F BI

E E

BE TV VS

B

II e

=

O tp t Characteristics of CE Amplifier


46/154

Output Characteristics of CE Amplifier

C

4BEV

5BEV

2BEV

3BEVxtrapo ate

xtics

Earl volta e

0 CEVAV

1BEV

1 B E TV VC E

C S

A

VI I e

V

= +

Thedecreaseineffectivebase

reversevoltage

is

called

early

effectofbasewidthmodulation.

Asaresult,therecombinationin

thebasedecreasesandand

henceIC=IBincreases.


47/154

NPN transistor in saturation region

( )C satIBI

B C

Vsat


48/154

Common Base Configuration

CI

EI

CBV

C E itt C fi ti


49/154

Common Emitter Configuration

Basic BJT Small Signal Model


50/154

Basic BJT Small Signal Model

cbB C

r or1mg vC vv

+

Basechar in E

0

i iv v

r = = C C

o

I I

r

= C

m

I

=g

Capacitance

change in base charge

change in BE voltage

h

b

i

qC

v

= =

0

b c

i

i

vr

v =

mg

1

CE CE

C C

CE A o

I I

V V r

= =

BE T

BE

V V

m S

BE

I eV

=

g

e h C F

h c F

Q Q I

q i

i

= =

=

0r

=mg

A

or

kT

kT

= =

=

m mg g

C

m

T

C

m

V

qI

=

=

g

g b F mC = g

b F F m

i iv v

= = = g

Fis the base transit time of the

carriers in the forward direction.


51/154

Vertical PNP BJT


52/154

VerticalPNPBJT

Lateral PNP BJT


53/154

LateralPNPBJT


54/154

Parasitic Elements in the Small-Signal Model

C B E

C

n+ n+

C C

je

3cr b

rp

csC csC1c

2cr n

+

n

cs p

Complete BJT Small Signal Model


55/154


B Cbr C

r

cr

r 1mvgC csC1v or

exr

m

r

=g

1o

m

r

=g A

kT

qV= CEVr

=

CollectorBaseResistance

0

n

CC

=

je bC C C= +

1

1

B

CE C

C B

V IrI I

=

=

0

1

0 o



56/154


B Cbr C

r

cr

r 1mvgC csC1v

exr

m

r

=g

1o

m

r

=g

A

kT

qV= CEVr

=

CollectorBaseResistance

0

n

CC

=

je bC C C= +

1

1

B

CE C

C B

V IrI I

=

=

0

1

0 o


57/154

1 kTCqI=m

r=g

o

m

r

=g

AqV

=

0C

je b= + 0 or r =m

kTb F m

C = g

0

1

n

V

=


58/154

Complete Small Signal Model


59/154

Complete Small Signal Model

20M

B C300 5.6 fF 50

2.6k10.038v0.4pF

10.5fF1v 20k

5

E

Short Circuit unity gain frequency and forward current


60/154

transfer ratio sin le Pole a oximation

B Cbr C cr

r

1mvgC csC

1

v

E

B C

r

oi

Neglecting rc

1o mi vgr 1mvgC C

1vii

( )1 1

ii

v

j C C

=+ +

0

1 m

C C

=+

gE

( ) ( )1 1

i i

o m m

i ii r

j r C Cj C Cr

=+ ++ +

g g

1

2

m

Tf

C C =

+

g

( )

( )

1

1

o

m

i

ij r

i j r C C

= =

+ +

g ( )

( )

11o m

i T

ij r

i j r C C

= = =

+

g


61/154

( ) ( )0

1 1mj sj r C C

= =+ + + ( )

0 0m

Half Power frequencyr C C

A r

= = +

= =g

( )10log j mT

gUnityGain frequency

C C = =

+

60

020log

40

0

20

0.1T T 0.01T


62/154

TheMetal

Insulator

Semiconductor

FET

62


63/154

AnenhancementtypenchannelMOSFET:(a)isometricviewofdeviceand

equilibriumbanddiagramalongchannel;(b)draincurrentvoltageoutput

characteristicsasafunctionofgatevoltage.

63


64/154

oxox

oxt=12

0

1

1

R

AA

D

W

NqNN

=

+

0GS TV V

2

D A

SiX

=

0

A

RV = +

IdealizedNMOSdevice crosssectionwithpositivevoltageappliedshowing

depletionregionsandtheinducedchannel.

64

MOSFET Threshold VoltageNq


65/154

ANq

2

g

fi

E

kTf i c v

kT n

n N N e

=

MOS threshold voltage (sufficient

large VGS for strong inversion):

0

2

2

A A Si

b A Si f

Q qN X qN

Q qN

= =

=. ms ga esu s ra e wor

function difference;2. Qss oxide and interface

charge;

( )2

2

b A Si f SB

b ss

T ms

Q qN V

Q Q

V

= +

= + + . b sur ace po en a aninduced depletionlayer charge offset;

4. f Fermi potential0 02

ox ox

b ss b bms f

ox ox ox

Q Q Q Q

C C C

= + + +

.

6. VSB substrate-bias( )0 2 2

2

t f SB f

Si A

V V

q N

= + +

=ox

C

65

MOS Substrate Bias Effect Example Plot - 2N t HJS E mple 2 5 (pp 51 52)


66/154

NoteHJS Example 2.5 (pp. 5152).

For the example we have been working, plot VT versus VSB.

[Calculate VT0 at VSB = 0 V for a polysilicon gate NMOS transistor with the followingparameters: NA (substrate) = 1 x 1016 cm-3; ND (gate) = 2 x 1020 cm-3; tox = 500 , oxide-

10 -2ox . . .

66

MOSFET Operation


67/154

p

67

NMOS FET Regions of Operation


68/154

VGS > VT0 shifts Ei below Ef,making s positive andinverting the surface.

Linear region

VDS > 0

IDS (drift current)

V

Source-drainsubstrate

,sa

junction never forward-biased.

68

NMOS FET Gradual Channel Approximation

V V hif E b l E ki


69/154

V > V shifts E below E makin

s positive and inverting the surface. VDS > 0 IDS (drift current).

VDS wider depletion region atdrain, but we assume that thedifference is small.

Source-drainsubstratejunction never forward-biased.

ra ua c anne approximation 1D I-V :VT0 is constant from y = 0 to y = LE >> EVGD = VGS VDS VT0

69

NMOS FET Gradual Channel Approximation


70/154

( ) ( )n ox GS T Q y C V V y V = ; Vchannel-to-source = V(y); 0 V(y) VDS; VGC = VGS V(y)

( ) ( )( )

DS nI xWJ xW v x vW Q y vWdV y

v E

= = = == =

; charge/unit area (yz) x carrier velocity x channel width

- -

( )DS ox GS T y

y

I C V V y V W E= ; drain current in long channel approximation

70

NMOS FET Linear Region, First Order


71/154

I C V V V W E= Only V(y) on the rhs depends on y ( )DS ox GS T

L V

I dy W C V V y V dV=

0 0

2

DS ox

DS

GS TI dy

VW

W VC V V dV =

=

V(y=0) = 0; V(y=L) = VDS

Drain current: linear region;radual lon -channel a roximation

2DS ox GS T DS

L

71

NMOS FET Linear Region, First Order


72/154

2

DSVW

I C V V V

= 2

' ox

L

k C

= =Process transconductance parameter (A/V2)

'k k L=Device transconductance parameter

22

DS GS T DS DSI V V V V=

Drain current: linear region;gradual, long-channel approximation

72

NMOS FET Saturation Region, First Order


73/154

What happens as VDS isincreased?

Drain current saturatesand "rolls over" with

increasing drain voltage.

us, D,sat an D,sat.

( )[ ]222

DSDSTGSDS VVVVk

I =

2

, TGSsatD

kVVV

=

,2

TGSsatDS

73

NMOS FET Saturation Region, First Order


74/154

pinchoff (no inversion layer) when VDS VGS VT0 ( )2

,2

DS sat GS T

kI V V=

( ),2

DS sat GS TkI V V= ( ) ( )[ ]TGSoxn VyVVCyQ =[Vchannel-to-source = V(y); 0 V(y) VDS; VGC = VGS V(y)]

74

NMOS FET I-VIDS versus VDS


75/154

IDS versus VGS

( )[ ]DSDSTGSDS VVVVk

I = 2 2

( )TGSsatDS VVkI =2

2

, ; (Ids)0.5 versus VDS is linear

; slope = k/2, x-intercept = VT

( )TGSsatDS VVk

I =

2

,

75

NMOS FET Channel Length Modulation


76/154

ID,sat

is in fact dependent on VDS

:

1. Depletion region shortens

k 2

effective channel length;

2. Channel charge densityincreases.

TGSsatDS

VVVk

I +=

=

1

2

2

,

2,

; lambda channel length modulation parameter(empirical approximation); units are V-1

76

NMOS FET Channel Length Modulation


77/154

IDS versus VDS

( ) DSDSTGSDSk

VVVVI = 22

2

2

DSTGSsatDS =2

,

77


78/154

interact

with

one

another.

velocitysaturation)earlythanpredictedby

.

78


79/154

=

The

horizontal

field

was

105

V/cm

up

to

1995.

theirvelocitylimitandmobilityofcarriers

decreases. Theverticalfieldcanbeapproximatedas

E =V t .

Exproducesmore

carriers

at

oxide

interface,

where the mobilit is reduced.

79


80/154

3.3V 1.2V10 /

5y

E V cmm

= = .0.35

y cmm

= = .0.1

y cm

m= =

45 50 10 /x o

VE V cm= = 63.3 4.4 10 /

x o

VE V cm= =

61.2 5.5 10 /x o

VE V cm= =

75A

80


81/154

0

+

=

ox

TGS

e

t

VV

1

0isnominalmobilityforlongchannel.

.

thehorizontalfieldactstoreducethemobilityevenfurther.

7

10 /satv V cm=

81

Short-Channel Devices (< 1 m) --- A New Regime


82/154

VT0 is constant from y = 0 to y = LEy >> ExVGD = VGS VDS VT0

submicron devices.

Ex is larger relative to Ey, and Eyapproaches 10 MV/m, the limit of

Saturation occurs before pinchoff.High fields velocity saturation.

effxj

1980 1995 2005

Ey 5.0 V / 5.0 m 3.3 V / 0.35 m 1.0 V / 0.07 m1 MV/m 10 MV/m 14 MV/m

Ex

5.0 V / 100 nm 3.3 V / 75 nm 1.0 V / 1.7 nm50 MV/m 440 MV/m 590 MV/m

VGD = VGS VDS VT0

Ex produces more carriers at oxide interface, where themobility is reduced.

Ey, exceeds Ecritical where velocity saturates. 82

Carrier Velocity SaturationMobility reduction at high vertical field (Ex)

.


83/154

=

TGS

e

VV

0

oxt

Mobility reduction at high lateral field (Ey)results from velocit saturation which we canrepresent in a piecewise linear function of Ey.

Cy

y

e EE

E

Ev


84/154

DS nI WQ v=

( )( ) e yDS ox GS T EI WC V V V y E

=

( )

CE

dV y

E

+

=y dy

DSI =

DS

DS e ox GS T

e C

L VDS

W E

II d W C V V V dV

=

84

0 0e ox

e CW E

NMOS FET Linear Region, Short Channel


85/154

DSL V DSI

= 0

2

0

2e ox

DS e ox GS T

e C

CWI V V V V

W E

=

; drain current in linear region with velocity saturation2 1 DS

C

L V

E L+

85

NMOS FET Saturation Region, Short Channel


86/154

( )DS n sat

DS ox GS T DS sat

I WQ vI WC V V V v

==

( )

, ,DS linear DS sat

GS T c

I I

V V E LV

=

=

( )

,

2

GS T c

GS T

V V E L

V V

+

=

( ),

1

cD sat GS T

GS T c

c

V V VV V E L

E L

= +

>

Very short channel device linear, not quadratic

VVLE


87/154

. ,

Low-Field MobilityNMOS PMOS Units

cm - s-

87

0.13 m NMOS, PMOS Saturation Currents

. .


88/154

technology. Assume a channel length of 100 nm, tox = 22 , VTN = 0.4 V, VTP = -0.4 V,VDD = 1.2 V, vsat= 8 x 106 cm/s.

( )2

4.2104.260.0100.6

=

==

VVCv

I

VcmVEVcmVE

TGSDS

CPCN

( )226116 40.02.1

106.1100.8

=

+

VV

cmFscmNMOS

LEVVW CTGS

1590

...=

+mA

[ ] ( )( )( )26116

4.240.02.1

40.02.1

106.1100.8

+

= VVVVV

cmFscmPMOS

= m

88

NMOS FET Subthreshold Region


89/154

1

=

eeII Tk

qV

Tnk

VVVq

ssubB

DS

B

offsetTGS

( )10ln==q

TnkVS BGS

; slope factor, mV/decade89

e a van age o av ng e ga e op ng e n+ or an p+ or

could be seen from analysis above Doping the gates in such a way leads to


90/154

could be seen from analysis above. Doping the gates in such a way leads to

devices with lower threshold voltages, but enables the implant adjustment with

the same kind of impurities that used in the bulk (ptype for NMOS and ntype for

PMOS). If we were to use the same kind of doping in gate as in the body (i.e. n+

for PMOS and p+ for NMOS) that would lead to higher unimplanted threshold

voltages. Adjusting them to the required lower threshold voltage would

interface. This is not desirable. Also, the doping of the poly gate can be carried out

at the same time as the source and drain and therefore does not require an extra

step.

90


91/154

= 0

+

ox

TGS

e

t

VV1

91

MOS Capacitance

, , .

For digital designs almost all capacitances are parasitic and each individual


92/154

For digital designs, almost all capacitances are parasitic, and each individualelement is small femtofarads or attofarads. Interconnect capacitances tend to bevoltage-independent. MOS capacitances are voltage-dependent (and non-linear).

Thin-oxide capacitances Cg(Cgs, Cgd, Cgb)

Gate overlap capacitances Col

Junction capacitances Cj(Csb, Cdb)

Depletion layercapacitance Cjc

92

MOS Capacitance


93/154

Junction capacitanceGate-channel capacitance

Gate overlap capacitance

93

MOS C-V Measurement Gate Oxider A0

CGCGoxoxg

t


94/154

CGCG

Accumulation AccumulationInversion

Low frequency

High frequency

Deep depletion

VG

n-Si

VG

-Si

- " - "G ,frequencies with a superimposed small AC signal (< 100mV, 0.110 MHz).

94

MOS C-V Measurement Gate Oxide


95/154

CGLow frequency

Cox

Cox Cs / (Cox+Cs)

VG

High frequency

p-Si

T

95

DiffusionCa acitance

( ) ( )Q Q V Q V


96/154

Channel-stop implantNocapacitance

forconducting

( ) ( )j j high j low

eq jo

D high low

Q Q V Q V Ceq K C

V V V

= = =

AN+

Side wall

Source

s e

Bottom

ND

Side wall

Channel

Substrate N

xj

LD oR

jo

jV

CC

/1 +=

Capacitanceis

( )1

100 0( )

mm

m

eq high lowK V V

=

voltage

high low m

96

Dynamic Behavior of MOS Transistor


97/154

DynamicBehavior

of

MOS

Transistor

C C C C C C = + = +

; ;GB GCB SB Sdiff DB Ddiff C C C C C C = = =

DS

CGDCGS

CSB CDBCGB

B

97

Ca acitance


98/154

98

MOS Gate Capacitance In Operating Regions

CC 0

, ,connection from channel surface to source and drain.


99/154

CC gdgs == 0

oxgb =

Linear region, conducting inversion layer shields substrate

0Cgb=

from gate charge; source and drain "share" the distributedoxide capacitance.

Linear

2CC oxgdgs

0CC bd ==

Saturation region, inversion layer does not extend to

drain, which is pinched off. As an approximation...Saturation

3

2 LWCC oxgs

99

MOS Gate Capacitance In Operating Regions


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Worst case (from Cgc,sat = 0.66 CoxWL and Cgc,linear = Cgc,cutoff= CoxWL) will beC C C C C C= + + = +

( )j jsw ox DC Area C Perimeter C W L 2L= + = +100


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MOS Capacitor in Depletion

Depletion condition: M O S


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pVG > 0 p-type Si

CG

is Cox

in series

with Cs where Cs can

G

WQM

be defined as

semiconductor

Depletion of

holesCo Cs

Cox=ox A /xox

2 SiW

=

x

s Si

CG = Cox Cs/(Cox + CS)

s

AqN

where s is surface potential

In this case, the gate capacitance decreases as the gate voltage is

increased. Why? 102

MOS Capacitor in Inversion

M O SG=

T

anG

>T

Inversion condition = 2 F


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p-SiInversion condition s 2 F

VG >>021

FA

Si

T2

2

qNWW

==

Depletion of

WQMAt high frequency, inversion

electrons are not able to respond

o esInversion electrons

- function

. ,charge on the metal, the depletion

layer width will vary with the ac.

Co

x

Cs

Cox

=ox

A/xox

Cs = SiA/WTCG ( ) = Cox Cs / (Cox + CS)

So, CG will be constant for VG VT103

Example n

- = 16 3 .

thickness is 100 nm. Plot the CG vs. VG characteristics when VG isvaried slowly from 5 V to +5 V Assume MOS has area of 1 cm2


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varied slowly from 5 V to +5 V. Assume MOS has area of 1 cm2,= 0.357 V.

Find Cox.

F1047.3cm1

cm101000

F/cm109.89.3 828

14

=

=oxC

n s m n w enxd=xd,T. o e a s ecreases as edepletion layer width increases. It is minimum when the depletionlayer width is maximum, i.e. whenxd=xd,T).

2/1

m298.0357.02cm10C106.1

F/cm1085.89.11231619,

=

=

Vx thresholdd

12

F1035.3cm1

cm10298.0

(min) 824s

=

=C

CG(min) = (3.4710

8

3.35) / (3.47+3.35) F = 1.7 108

F

CG = Cs in series with Cox.

104

21

Example n, continued

FssSi

AoxSioxsTG 2when =

+== qxVV


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Siox

= .

Plot the C-V characteristics 34.7 nF

CG

34.7nFow-

Explain why CG does notvary for VG > VT.

17nFhigh-fQuestion: How will you calculate

VG2.17 V

G w en G =

Answer: Calculate s when VG =1 V using the equation above.-s ,

Cs. Then, calculateCG = (Cox Cs) / (Cox + Cs) 105

MOS Junction Capacitance

, - ,

and three-dimensional view


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swjswbjb ACACC +=

Bsw

J

Bb

J VV

11

( )mj

swbjb

J

jswjb

AACC +=

B

J

1

106

MOS Junction Capacitance

, -

( ) ( )2 1j jQ V Q V QC

= =


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2 1

eqCV V V

= =

( )2 2

1 1

1

mV V

jbV V

B

VQ C V dV C dV

= =

( ) ( )

1 1

2 1

2 1

1 11

m m

jb B eq

eq

B B

C A V VC

V V m

=

1 21 2 1 2

1

2

2eq B

m

C

=

( ) ( )

2 1

2 1

eq B B

jb

J eq jb jb j eq jb j

C V V

C K C WY C Wx K C Y x W

= =

= + = +

107


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Cutoff Linear Saturation

0GSC 12 oxC WL 2

3 oxC WL


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3

0 0

GDC

C C WL

2 oxC WL

109

Transconductancegm

( )

2

2DS GS TI V V

I W=


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DI W= = m ox

GSV L

Body

transconductance

gmb

0 2 2

2

t t f SB f

Si A

V V V

q N

= + +

=

( )( )1

ox

tDmb ox GS T DS

BS BS

VI WC V V V

V L V

= = +

g

( )2 2t

BSf SB

V

V V

=

+

( )2 2ox DD

mb

BS f SB

C W L I I

V V

= =

+g


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TheSiliconWafer

Waferissin lecr stalline li htl do edmaterial.


128/154

Diameterofwaferisbetween4and12inches.

Thicknessat

most

1mm.

Aptypedopedwaferisapproximately,21021 imputies/m3.

Oftentheoppositetypeisgrownoverthesuffacebeforethe

y.

128

ThewholeSiliconingot:


129/154

Siwafers

sliced

from

ingot

:

129


130/154

Siliconcrystal.Thislargesinglecrystalingotprovides300mm(12in.)diameter

waferswhen

sliced

using

a

saw.

The

ingot

is

about

1.5

m

long

(excluding

the

taperedregions),andweighsabout275kg.(PhotographcourtesyofMEMC

130

ElectronicsIntl.)


131/154

PatterningofSiO2

SisubstrateHardenedresist

Chemicalor

plasma

etch

2


132/154

(a)Siliconbasematerial

Photoresist

SiO 2

Sisubstrate

(d)Afterdevelopmentandetchingofresist,

(b)Afteroxidationanddepositionofnegativephotoresist

Sisubstrate

SiO2

chemicalorplasmaetchofSiO2

Hardenedresist

UVlight

Patternedopticalmask

su s ra e

(e)Afteretching

Si

substrate Sisubstrate

SiO2

(f)Finalresultafterremovalofresist

132

c epperexposure


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IntegratedcircuitLateralPNPTransistor


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Slide001 Semiconductor Review