Slide Set Data Converters ————————— Digital Enhancement ...ims.unipv.it/Courses/download/ACD/CAD_SlidesVIII.pdf · ) 0DOREHUWL '$7$&219(57(56 6SULQJHU OHW[LY ',,7$/(1+$1&(0(177(&+1,48(6

F. MalobertiDATA CONVERTERS Springer2007

Chapter 8

DIGITAL ENHANCEMENT TECHNIQUESF. MalobertiDATA CONVERTERS Springer2007

Chapter 8

DIGITAL ENHANCEMENT TECHNIQUES0

Slide Set

Data Converters

—————————

Digital Enhancement Techniques


Chapter 8


Chapter 8


Chapter 8

DIGITAL ENHANCEMENT TECHNIQUES


Chapter 8


Chapter 8


SummaryIntroduction

Error Measurement

Trimming of Elements

Foreground Calibration

Background Calibration

Dynamic Matching

Decimation and Interpolation


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Introduction

The rapid advancement of digital technology motivates an increasing useof digital techniques that improve the ADC or the DAC design by the cor-rection or calibration of static and possibly dynamic limitations.

The methods studied in this chapter can be classified into the followingcategories:

• Trimming of elements.

• Foreground calibration.

• Background calibration.

• Dynamic matching.


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Error Measurement

The basis of digital assistance methods is in the measurement of errors.

LOGIC

DAC

Fs Fe Fe Fs Fs Fe

Fs

C1 C2 C3

Vref Vref

ErrorA

Mesure of the mismatch between capacitors with extra DAC.


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VA = VBC2 − C1

C1 + C2 + C3(1)

VA =VB(C2 − C1) + (VDAC + εQ)C3

C1 + C2 + C3(2)

|(C2 − C1)|max =Vref

VBC3; ∆Cmism =

∆

VBC3. (3)


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Off-line error mismatch of current sources.

Fm,1 F1,1 F1,2 Fm,i Fi,1 Fi,2 Fm,N FN,1 FN,2

Vth

FR

COUNTStart

Stop

LOGIC

Iu,1 Iu,i Iu,N

Iref

Error

Iout,1Iout,2

C

_+

VAG

VDD

DI

Use of one extra current source and periodic error measurement of one element.

Tstop = kmeasTck =CVth

∆I + δIu,i; δIu,i = Iref − Iu,i (4)


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Trimming of ElementsAdjust a component value by discrete steps using fuses or anti-fuses that permanentlyopen or close connections.

MOS switches state is stored in a memory.

Array of small elements, possibly binary weighted, connected in series or in parallel forconnecting or disconnecting them according to a suitable control algorithm.

Trimming suitably adapted to the design target and the algorithm used.

The capacitor mismatch on a pipeline converter is critical in the first few stages.

Some errors are acceptable other are not acceptable→ focus on the critical error.


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Vres =Vin∑N

1 CU,i − VRef∑N

1 CU,ibi

CU,f(5)

Vres = Vin

[N +

N∑1

εi

]− VDAC

[k +

N∑1

εibi

](6)

VRES

-+

CU,1 CU,fFS

FS

FR

VRef

VIN

FS

FR FR

CU,NFS

FS

FR

CT

FS

FRFR

FS

FS

FR,1FR,1

FR,N FR,N

VRES

-+

CU,1 CU,fFS

FS

FR

VRef

VINFS

FR FR

CU,2FS

FS

FR

FSFR,1FR,1

FR,2 FR,2

CU,NFS

FS

FR

FR,N FR,N

(a) (b)


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Trimming and measure of Offset

DAC UP/DOWNCOUNTER

Vos

S+

DAC UP/DOWNCOUNTER

Vos

(a) (b)

-

The measured offset is then used for a digital correction of results.


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Foreground CalibrationTrimming of elements or the mismatch measurement by a dedicated calibration cycle.

Normally performed at power-on or during periods of inactivity of the converter.

ADC

CalibrationSignal

DIGITALLOGIC

ADDER

Memory

VinOUT

Yout =YC2nc(1 + εk) + YF

(1 + εk)(7)

Processing required to correct the interstage gain in a two-step converter.


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Foreground calibrated DAC

ADDER

Memory DIGITALLOGIC

DAC

ADC

CalibrationSignal

VoutIN

The ADC can be slow but must be precise.


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Background CalibrationUse of redundancy (one extra ADC or part of ADC)

ANALOG

SELECTOR

ADC

ADC

ADC

ADC

ADC

DAC

DIGITAL

INTERFACE

Logic Memory

ADDERVin OUT

1

2

3

4

5


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Background CalibrationUse of two converters one fast and one slow.

VinS/H ADC1

M ADC2 DIGITALLOGIC

n-bit

(n+p)-bit

Addition

Memory

OUTfs fs

fs /M

The slow converter determines the accuracy (it may provides more bit to have a moreaccurate correction of the INL)


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Skip and fill method: replaces one out of a given number of input (p) samples with a testsignal.

The missing conversion is recovered by digital interpolation, for example, using an FIRfilter.

tk+8 k+16k k+1 k+12..... ..... .......... k+4

p=8

The error power in the recovery process must be lower than the LSB

ε2sk <

p

12 · 22n; (8)


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This method obtains the necessary room for background calibration by using a conversionrate higher than the sampling rate.

The lower sampling frequency accommodates for n + 1 conversions in n sampling peri-ods, thus making the converter available one extra slot every n+ 1.

The shift between sampling and conversion times is managed by a queue block.

OUT

Sampling

Conversion t

t

ADCQueue M

UX

fconvfsCAL

X

Cal

(a)

(b)

1 2 3 4 5 6 7 8

1 2 3 4 5 6 7


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Gain and Offset in Interleaved ConvertersHow to measure the Gain and offset mismatch?

ANALOG

SELECTOR

ADC

ADC

ADC

ADC

ADC

DAC

DIGITAL

INTERFACE

Logic Memory

ADDERVin OUT

1

2

3

4

5

Place the extra path, used as a reference, in parallel with one of the interleaved convert-ers.


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Assuming zero the offset and 1 the gain of the reference path

yref(i) = xin(i) + εQ,r(i)

yp(i) = xin(i)δG,i +OG,i + εQ,p(i)

yp(i)− yref(i) = xin(i)δG,i +OG,i + εQ,p(i)− εQ,r(i) (9)

<yref>M=<xin>M

<yp − yref>M=<xin>M δG,i +OG,i (10)

A second average over another series of samples gives

<yp − yref>N=<yref>N δG,i +OG,i (11)

That makes a system of two equations with two unknowns δG,i and OG,i.


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Offset Calibration without Redundancy

A

OUT

ADC

LOGIC

ffff

(a)

(b)

Vin

Vin

fff f f

Chopper stabilizer and spread-spectrum chopping.


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Gain Calibration in Interleaved Converters

ADCS+

DAC

SIGGEN

S

T

X

+

X+T Y' Y

X DSP

+

- T eG

T

SY' Y

+ -X

T' X

DSP

(a) (b)

Y"

z-kT'

Addition of a test signal T to the input and subtraction after the A/D conversion.

Y = X(1 + δG) + TδG + εQ (12)

Signal processing enables calibration.


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Digital gain mismatch correction for a two-channel time-interleave.

The gain mismatch is equivalent to the multiplication of the input by a square-wave→ theoutput spectrum Y contains an image of the input at fN − fin.

fin fNfin -fN fin fNfin -fN

Signal Signal

Image ImageChopping

Ampl

itude

f f

Ampl

itude

2

2X

z

S+

+X

X DSP

-1

Y1

Y2 fN /2

Y

(b) (c)

(a)

YM

G1 /G2

ADC

ADC

X1

X2

Y YM


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Dynamic MatchingConsider two nominally equal inter-changeable elements X1 and X2. Assume X2 =X1(1 + δ) and X1 +X2 = 1.

Y1 =1

2 + δor Y2 =

1 + δ

2 + δ(13)

ε1,2 = ∓δ

2 + δ(14)

The method is to use sequentially or randomly the elements X1 and X2.

With many elements the approach can be extended ...


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Dynamic matching of two elements

Iref

I1 I2

R1 R2

M1 M2

SW

VB

VR

VR

1 0 0 1 1 0 1 0 1 0 0 1

I1I2

Iout

(a) (b)


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Example: Generation of a pseudo-random bit-stream (7-bit binary divided DAC)

z-1 z-1 z-1 z-1 z-1 z-1 z-1 z-1

S

PROC

if X > 2n-1; Y=X - 2n

if X < -2n-1; Y=X+ 2n

XYn-bit

sign-bit

n-bit


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Butterfly RandomizationToo many combinations of unity elements ....

ThermometricDecoder

RANDOMIZER

Sel Unity ElementSel Unity ElementSel Unity ElementSel Unity ElementSel Unity ElementSel Unity ElementSel Unity ElementSel Unity ElementSel Unity ElementSel Unity ElementSel Unity Element

Sel Unity Element

1

M

SYoutY


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01234567

01234567

B0B1B2

X =1

M

M∑1

Xi; (15)

Y (N) =M∑1

di ·Xi (16)

di is the Xi element flag.

εY (N) =M∑1

di ·Xi −NX =M∑1

di ·Xi −N

M

M∑1

Xi. (17)


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Assume the value of Xi isXi = X + δXi (18)

δXi is a random variable with variance X2σ2X .

σ2y = E

{[εY (N)]2

}= (N −

N2

M)X

2σ2X (19)

which is is zero for zero or M elements, and has its maximum at N = M/2.

The SNR determined by just the mismatch error and an OSR oversampling results

SNR =3M

OSR · σ2X

(20)

With M = 8, OSR = 1 (Nyquist-rate converter), δ = 0.002, the SNR = 65 dB. IfOSR = 32 SNR = 80 dB.


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Example 8.2Use of the butterfly randomization in a 3-bit second order Σ∆

Without randomization


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With randomization

Tones are transformed into white noise!


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Individual Level AveragingThe (ILA) approach aims at exercising each unity element with equal probability for eachdigital input code.

I6 I7563523655

11

I1 I3I2 I4 I511

111

3

111111111

122233334

112222233

111111111

1 11 11 11 11 11 11 1

22233

INDEXES ELEMENT

I6 I711

I1 I3I2 I4 I511

111

7

111111111

166644441

117777766

111111111

1 11 11 11 31 31 31 3

44477

INDEXES(a)

(b)

1 2 3 4 5 6 7

ELEMENT1 2 3 4 5 6 7

In

Time-index

123456789

563523655

In

Time-index

123456789

Rotation or addition approach.


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1

2

3

4

5

6

7

1

2

3

4

5

6

7

ELEM

ENT

ELEM

ENTtime time

(a) (b)

Use of elements with rotation and addition ILA (sequence 5-6-3-5-2-3-6-5-5)


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Example 8.3Use of ILA in the DAC of a 3-bit second order Σ∆.

104 105 106 107−140

−130

−120

−110

−100

−90

−80

−70

−60PSD of the Mismatch Error (no DEM)

Frequency [Hz]

PSD

[dB]

104 105 106 107−140

−120

−100

−80

−60

−40

−20

0PSD of the Output

Frequency [Hz]

PSD

[dB]


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104 105 106 107−140

−130

−120

−110

−100

−90

−80

−70

−60PSD of the Mismatch Error (ILA−R, 8 elements)

Frequency [Hz]

PSD

[dB]

104 105 106 107−140

−120

−100

−80

−60

−40

−20

0PSD of the Output

Frequency [Hz]

PSD

[dB]


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104 105 106 107−140

−130

−120

−110

−100

−90

−80

−70

−60PSD of the Mismatch Error (ILA−A, 8 elements)

Frequency [Hz]

PSD

[dB]

104 105 106 107−140

−120

−100

−80

−60

−40

−20

0PSD of the Output

Frequency [Hz]

PSD

[dB]


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Data Weighted AveragingThe method uses just one index, in common with all the input codes updated by theaddition of the new input code to the content of the index register.

UU

U

U

U

U10

U9 U8 U7

U6

U5

U4

U3

U2

U1

11

12

13

1415

INDEX

S


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165161431

INDEX ELEMENT1 2 3 4 5 6 7 1

2

3

4

5

6

7

ELEM

ENT

time(b)(a)

563523655

In

Time-index

123456789

DWA: Use of elements for a given input sequence.


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The DWA method determines a first order shaping of the mismatch error.

M∑1

δXi = 0 (21)

∆i(k) =i+k−1∑

i

δXk for i+ k − 1 < M

∆i(k) =M∑i

δXk +i+k−1−M∑

1

δXk for i+ k − 1 > M (22)

OUTDAC

fs

S+

+

1

k1 k2 k3

k3 k4 k5

2 3 4 5 6 7 8 1 2Cycle 1

k6(a) (b)

1 2 3 4 5 6 7 8 1Cycle 2

Dk(nT)


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The noise injected in the first time-slot is ∆1(k1) = δX1 + δX2 + δX3; in the secondtime-slot is ∆2(k2) = δX4 + δX5 + δX6 + δX7.

∆3(k3) split in two parts ∆′3(k3) = δX8 and ∆′′

3(k3) = δX1 + δX2.

∆1(k1) + ∆2(k2) + ∆′3(k3) = 0 (23)

∆2(k2) = −[∆1(k1) + ∆′

3(k3)]. (24)

∆1(k1)−[∆1(k1) + ∆′(k3)

]z + ∆′(k3)z2 (25)

that rearranged yields

−z−1∆1(k1)(1− z−1) + ∆′3(k3)(1− z−1) (26)

Similar considerations for the next clock periods obtain ∆4(k4), ∆5(k5) and the fractionof ∆6(k6) pertinent the second time slot.

∆4(k4) = −[∆′′

3(k3) + ∆5(k5) + ∆′6(k6)

](27)

∆4(k4)z2 −[∆′′

3(k3) + ∆5(k5) + ∆′6(k6)

]z3 + ∆5(k5)z4 + ∆′

6(k6)z5 (28)[z−1∆5(k5)−∆′′(k3)z−3

](1− z−1) + ∆′

6(k6)(1− z−2) (29)


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The mismatch error passes through shaping function (1 − z−d), where d is the distancein clock-periods between the sample and the one almost halfway the considered cycle.

(1− z−d) ' d · (1− z−1); z → 1, (30)

OUT DAC S

+

+

Dk(nT)Logic

n

3

2

SmartSwiching

1-z-1

IN

a smart switch directs the error to the proper amplification block before the (1−z−1) filter.


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Example 8.4Comparing Butterfly and DWA

——————–

104 105 106 107−140

−130

−120

−110

−100

−90

−80

−70

−60PSD of the Mismatch Error (Butterfly with 8 elements)

Frequency [Hz]

PSD

[dB]

104 105 106 107−140

−120

−100

−80

−60

−40

−20

0PSD of the Output

Frequency [Hz]

PSD

[dB]


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104 105 106 107−140

−130

−120

−110

−100

−90

−80

−70

−60PSD of the Mismatch Error (DWA with 8 elements)

Frequency [Hz]

PSD

[dB]

104 105 106 107−140

−120

−100

−80

−60

−40

−20

0PSD of the Output

Frequency [Hz]

PSD

[dB]


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Decimation and InterpolationThe digital signal at the output of a Σ∆ modulator removes the out-of-band shaped noiseand reduces the clock-rate by decimation.

The interpolation increases the sampling frequency and obtaining oversampling as re-quired by a Σ∆ DAC.

Decimation

Shaping leaves little noise in the signal band → total aliased noise power much smallerthan the in-band noise.

V 2FS

810−SNR/10 >> H2

dec(fs/2)22LV 2

FS

12 · k2 ·OSR(31)

for SNR = 104 dB L = 3, OSR = 32 and k = 8, stop-band gain much lower than−87 dB.


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With large decimation factors the operation in done in successive steps.

Decimation factor KD (KD = 2kd) is divided into the product

KD = 2kd12kd2 · · ·2kdp , (32)

Possible architecture

M1n-th SINCFILTER

M2FIR

half-band

M3FIR

half-band

DROP

CORRECTION

M1=4-32 M2=2-8 M3=2-4

fs/(M1M2M3)fs/M1 fs/(M1M2) fs/(M1M2M3)fs


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Ysinc(n) =1

N

N−1∑0

X(n− i). (33)

Hs(z) =1

N

N−1∑0

z−i =1

N

1− z−N

1− z−1; (34)

0 0.5 1 1.5 2 2.5 3 3.5 40

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1Sinc Magnitude Response

8f/fs

Ampl

itude

[dB

]

sinc

sinc2sinc3


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A sinc filter attenuates only at the required frequencies but the attenuation must ensuringthe desired noise rejection.

For an L-th order modulator it is required using a sincL+1 filter.

——————–

For example, a sinc filter is not an adequate for a first order Σ∆.

The spectrum of the quantization noise, shaped by (1− z−1)2 and filtered by H2n(z), is

v2n,out(z) = v2

n,Q(1− z−1)2 1

N2

[1− z−N

1− z−1

]2

=v2n,Q

N2(1− z−N)2. (35)

The use of the z → ejωT transformation obtains

v2n,out(ω) = v2

n,Q

[2sin(NωT/2)

N

]2

(36)

using sin(NωT/2) ' ±NωT/2

v2n,out(2πf) = v2

n,Q [2πfT ]2 (37)

Hs(z) = (1 + z−1 + z−2 + z−3)3 (38)


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The sincL+1 filter is a transversal structure.

For example for L = 3 and N = 4 the filter is

= 1 + 3z−1+6z−2+10z−3+12z−4+12z−5+10z−6+6z−7+3z−8+z−9

The coefficients can be stored in a memory or generated step by step during the filteringoperation.

For large values of N the number of coefficients and the number of taps of the transversalfilter can become impractical. A possible alternative architecture is

REGS REGS REGS

REG

S

REG

S

REG

S N

IN

OUT

Integrators

Differentiators


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InterpolationSingle stage is practical only for for relaxed transitions between pass-band and stop band.

A transition region 0.45− 0.55 fs with more than 100 dB of attenuation in the stop bandand a ripple of about 0.0001 dB in the pass band requires a 125 taps FIR filter.

0 0.1 0.2 0.3 0.4 0.5!180

!160

!140

!120

!100

!80

!60

!40

!20

0

20Magnitude Response

f/fs

Ampl

itude

[dB]


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FIR1

FIR2

FIR3

S&H

100-140 taps 25-50 taps 4-16 taps

2fs 4fs 8fs 64fs (128fs)

2 2 2 8 (16)

0 1 2 3 4 5 6 7 8

−100

−80

−60

−40

−20

0

Magnitude Response FIR1

f/fs

Ampl

itude

[dB]

0 1 2 3 4 5 6 7 8

Magnitude Response FIR2

f/fsMagnitude Response FIR3

0 1 2 3 4 5 6 7 8f/fs

−100

−80

−60

−40

−20

0

Ampl

itude

[dB]

Magnitude Response S&H

0 1 2 3 4 5 6 7 8f/fs


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Wrap-upThe use of digital techniques improves the data converter performances.

The static accuracies are improved by measuring the error or by calibrating elements. Wehave seen various approaches for obtaining the results.

The foreground calibration requires a specific time-period during which the converter innot used. Background calibration is more complex as it is done while the converter worksnormally.

We have seen that calibration can be very expensive and it is worth to limit the correctionto the critical limits (for example, gain error or offset can be acceptable).

The dynamic matching of elements is appropriate for sigma-delta modulators, especiallywhen they grant a shaping of the mismatch error.

Digital techniques are necessary for the pre and the post-processing of data. Low-passfiltering, decimation and interpolation have been briefly discussed. More details are foundon specific courses on digital signal processing.


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Documents

Slide Set Data Converters ————————— Digital Enhancement ...ims.unipv.it/Courses/download/ACD/CAD_SlidesVIII.pdf · ) 0DOREHUWL '$7$&219(57(56 6SULQJHU *OHW[LY ',*,7$/(1+$1&(0(177(&+1,48(6

Slide Set Data Converters ————————— Digital Enhancement ...ims.unipv.it/Courses/download/ACD/CAD_SlidesVIII.pdf · ) 0DOREHUWL '$7$&219(57(56 6SULQJHU OHW[LY ',,7$/(1+$1&(0(177(&+1,48(6